Capacitorless 1T-DRAM Research Articles

Energy-Band-Engineered Unified-RAM (URAM) Cell on Buried $\hbox{Si}_{1 - y}\hbox{C}_{y}$ Substrate for Multifunctioning Flash Memory and 1T-DRAM

A band-offset-based unified-RAM (URAM) cell fabricated on a Si/Si1-yCy substrate is presented for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating-body are combined in a FinFET structure to perform URAM operation in a single transistor. The O/N/O layer is utilized as a charge trap layer for NVM, and the floating-body is used as an excess hole storage node for capacitorless 1T-DRAM. The introduction of a pseudomorphic SiC-based heteroepitaxial layer into the Si substrate provides band offset in a valence band. The FinFET fabricated on the energy-band-engineered Si1-yCy substrate allows hole accumulation in the channel for 1T-DRAM. The band-engineered URAM yields a cost-effective process that is compatible with a conventional body-tied FinFET SONOS. The fabricated URAM shows highly reliable NVM and high-speed 1T-DRAM operations in a single memory cell.

Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications – 2-bits for nonvolatility and 1-bit for fast operation.

Gate-Induced Drain-Leakage (GIDL) Programming Method for Soft-Programming-Free Operation in Unified RAM (URAM)

A soft-programming-free operation method in unified RAM (URAM) is presented. An oxide/nitride/oxide (O/N/O) layer and a floating-body are integrated in a FinFET, thereby providing the versatile functions of a high-speed capacitorless 1T-DRAM, as well as nonvolatile memory, and the mode of the memory cell can be selected and independently utilized according to the designer's demand. With the utilization of the impact ionization method for 1T-DRAM programming, undesired soft charge trapping into O/N/O gradually shifts the threshold voltage, resulting in an unstable operation in the URAM. In order to avoid such problems associated with soft programming, a gate-induced drain-leakage (GIDL) program method is proposed for improved immunity to disturbance. It is found that the GIDL method effectively suppresses soft programming without sacrificing the sensing current window.

A Capacitorless 1T-DRAM on SOI Based on Dynamic Coupling and Double-Gate Operation

The scaling requirements of conventional DRAMs lead to the recent developments of capacitorless single-transistor (1T) DRAM in SOI technology. We propose a new concept of 1T-DRAM (named MSDRAM), which is simple to fabricate, program, and read. Its basic mechanism is the metastable dip hysteresis effect, which takes advantage of the dynamic coupling between front and back interfaces in SOI transistors. Systematic measurements and simulations show that MSDRAMs are suitable for low-power applications, as they exhibit negligible off-state current and long retention time even for 50-nm devices.

Partially Depleted SONOS FinFET for Unified RAM (URAM)—Unified Function for High-Speed 1T DRAM and Nonvolatile Memory

Unified random access memory (URAM) is demonstrated for the first time. The novel partially depleted (PD) SONOS FinFET provides unified function of a high-speed capacitorless 1T DRAM and a nonvolatile memory (NVM). The combination of an oxide/nitride/oxide (O/N/O) layer and a floating-body facilitates URAM operation in PD SONOS FinFETs. An NVM function is achieved by FN tunneling into the O/N/O stack and, a 1T-DRAM function is achieved by excessive-hole accumulation in the PD body. The fabricated PD SONOS FinFET shows retention time exceeding 10 years for NVM operation and program/erase time below 6 ns for 1T-DRAM in a single-cell transistor. These two memory functions are guaranteed without disturbance between them.

A Bulk FinFET Unified-RAM (URAM) Cell for Multifunctioning NVM and Capacitorless 1T-DRAM

A bulk FinFET-based unified-RAM (URAM) cell technology is demonstrated for the fusion of a nonvolatile-memory (NVM) and capacitorless 1T-DRAM. An oxide/nitride/oxide layer and a floating-body are combined to perform a URAM operation in a single transistor. A buried n-well technology for NMOS allows hole accumulation for the 1T-DRAM operation in a p-type bulk substrate. The bulk FinFET URAM offers a cost-effective and fully compatible process with a conventional FinFET SONOS, and it also expedites heat dissipation. Highly reliable NVM and high-speed 1T-DRAM operation are confirmed, and it was also verified that there is no disturbance between the two memory functions.

A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory

A capacitorless one-transistor (1T)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude and a write speed within several nanoseconds. The capacitorless 1T DRAM is the most promising technology for high-performance embedded-DRAM large-scale integration.

A study of highly scalable DG-FinDRAM

This letter reports the scalability of a capacitor-less 1T-DRAM, and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less than 50 nm. Superior characteristics such as long retention time and large sense margin even for gate lengths around 50 nm can be obtained with a double-gate fully depleted FinFET DRAM. Considering capacity, speed, power, and structural complexity of embedded memory, the capacitor-less 1T-DRAM has the possibility of playing the leading role among other memories.