Cross-coupling Capacitance Research Articles

A 5.15–7.125-GHz Differential Power Amplifier With Enhanced Linearity of Average Power Region Using Dynamic Cross-Coupled Capacitor

A 5.15–7.125-GHz Differential Power Amplifier With Enhanced Linearity of Average Power Region Using Dynamic Cross-Coupled Capacitor

Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique

A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<−10 dB and an IIP3 from −7.5 dBm to −10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<−10 dB, and an IIP3 from −21 dBm to −17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage.

A Reconfigurable RF Filter With 1%–40% Fractional Bandwidth for 5G FR1 Receivers

This paper presents a radio frequency front-end (RFFE) for 5G New Radio (NR) receivers operating in Frequency Range 1 (FR1). The core of this RFFE is a synthetic fourth-order Q-enhanced RF filter employing gm-boosting, noise-cancelling, capacitive cross-coupling, and forward body-biasing techniques to achieve 1.7 GHz to 6.4 GHz operating range and 1 adjustable fractional bandwidth (FBW). The function of the filter is based on subtracting out-of-phase signals in the passband and in-phase signals in the stopband. Two Q-enhanced LC resonators are utilized for outphasing. The filter is preceded by a low-noise transconductance amplifier, and it is followed by a programmable gain amplifier and a differential buffer stage for the measurement purposes and gain equalization. The experimental results demonstrate that the voltage gain is tunable between 18 and 47 dB with 0.2 dB steps, which leads to an equalized output power in all the filter configurations. Fabricated in 22 nm Fully Depleted Silicon on Insulator (FD-SOI) technology, the RFFE achieves 4.6 dB NF, -14 dBm IB-IIP3, and 26 dBm IB-IIP2 at 4 GHz. Notably, the fourth-order steep roll-off provides 22 dBm OOB-IIP3 at 2WBW frequency offset. The entire RFFE draws 22-45 mA from a 1 V supply and the filter core occupies 0.11 mm2 chip area.

고선형성 저전력 24-GHz 저잡음 증폭기 개발

This paper presents a high-linearity low-power 24-GHz CMOS low noise amplifier (LNA). The LNA was designed and implemented using 65 nm RF CMOS technology. The circuit was powered by a 1.2 V supply and operated at a frequency of the 24 GHz. To reduce noise and nonlinearity, an inductor was connected to the gate of the cascode transistor and combined with capacitive cross-coupling. The proposed LNA was fabricated with a maximum OIP3 of 21.8 dBm, lowest power consumption of 6 mW, lowest noise figure of 2.9 dB, and smallest die size of 0.31×0.34 mm².

An AM-PM Compensation of Cross-Coupled Capacitance Neutralization Technique in a Differential Power Amplifier

An AM-PM Compensation of Cross-Coupled Capacitance Neutralization Technique in a Differential Power Amplifier

A 21–41-GHz Common-Gate LNA With TLT Matching Networks in 28-nm FDSOI CMOS

A wideband common-gate (CG) cascode low-noise amplifier (LNA) is demonstrated with a 28-nm fully depleted silicon on insulator (FDSOI) CMOS process. Wide bandwidth is achieved with a CG structure in the first stage and tightly coupled ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k=0.86$ </tex-math></inline-formula> ) transmission line transformer (TLT) matching networks. A gm-boosting technique with cross-coupled capacitors improves the gain and noise figure (NF) of the CG amplifier. A high-input 1-dB gain compression point (IP1 dB) can be achieved by introducing an inter-stage inductor at the second-stage cascode amplifier. The LNA shows 19.3 dB gain, 3.1 dB NF, 19.8 GHz (63%) of 3 dB bandwidth, and −15.7 dBm IP1 dB at 28 GHz.

Design and Characterization of 10 Gb/s and 1 Grad TID-Tolerant Optical Modulator Driver

This paper presents the design and the experimental characterization of a 10 Gb/s electronic driver for silicon Mach-Zehnder modulators (MZMs). This driver is able to operate in harsh environments characterized by radiation levels up to 1 Grad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) total ionizing dose (TID). To compensate for the detrimental effects that radiation produces on the target 65 nm bulk silicon technology both device- and circuit-level radiation hardened by design (RHBD) techniques are developed and implemented. Extreme TID levels are faced using long-channel transistors with enclosed layout, avoiding the use of p-MOSFETs, and implementing a differential self-biased cascode architecture with common-mode feedback. Band-widening techniques, e.g., inductive peaking, cross-coupled capacitors, and buffer chaining, have been used to improve the driver’s frequency response and reach the targeted data rate. Electrical measurements show 10 Gb/s waveforms with an eye diagram amplitude suitable for MZM driving. Electro-optical measurements performed connecting the electronic driver to a silicon photonic MZM confirm the achievement of a 10 Gb/s system-level operability. The radiation hardness of the driver is verified by exposing the integrated circuit to X-rays. The measurements confirm the ability of the driver to work up to 1 Grad with an eye amplitude reduction of only 10% and a 7% increment in the rise and fall times, validating the effectiveness of the implemented RHBD techniques.

Feasibility Analysis of a Reduced Capacitive Wireless Power Transfer System Model for Transportation Electrification Applications

A practical approach in modeling a capacitive wireless power transfer (CPT) system that utilizes an electrostatic field for the power transfer is presented in this article. The reduced capacitance model (RCM) is derived from the conventional six capacitance model (SCM) for the CPT system in view of the large charging area applications, such as electric vehicle charging. The effect of the same side and cross-coupling capacitances diminishes when the separation distance between the same side plate pair is large enough, and the reduced capacitance model (RCM) is obtained. A bipolar capacitive-link dispersion distance proposed in this article acts as an indicator to decide the use of RCM or SCM depending on the application. Furthermore, RCM attains unity voltage gain and load-independent operation at the designed single resonant frequency, unlike the SCM, where the influence of multiple resonant frequencies is predominant. An experimental validation is performed to determine the effectiveness of the RCM.

Concurrent-Mode CMOS Detector IC for Sub-Terahertz Imaging System.

A CMOS detector with a concurrent mode for high-quality images in the sub-terahertz region has been proposed. The detector improves output-signal coupling characteristics at the output node. A cross-coupling capacitor is added to isolate the DC bias between the drain and gate. The detector is designed to combine a 180° phase shift based on common source operation and an in-phase output signal based on the drain input. The circuit layout and phase shift occurring in the cross-coupled capacitor during phase coupling are verified using an EM simulation. The detector is fabricated using the TSMC 0.25-μm mixed-signal 1-poly 5-metal layer CMOS process, where the size, including the pad, is 1.13 mm × 0.74 mm. The detector IC comprises a folded dipole antenna, the proposed detector, a preamplifier, and a voltage buffer. Measurement results using a 200-GHz gyrotron source demonstrate that the proposed detector voltage responsivity is 14.13 MV/W with a noise-equivalent power of 34.42 pW/√Hz. The high detection performance helps resolve the 2-mm line width. The proposed detector exhibits a signal-to-noise ratio of 49 dB with regard to the THz imaging performance, which is 9 dB higher than that of the previous CMOS detector core circuits with gate-drain capacitors.

Integrated-Designs of Filtering Circuits Based on Adjustable Dielectric Waveguide Resonators

This brief presents a new kind of adjustable dielectric waveguide resonator (DWR), based on which integrated designs of filtering circuits are conducted. The DWR is composed of a dielectric part as the main resonating body and a printed circuit board (PCB) part as the cover. An unmetallized blind hole is carved at the upper surface of the dielectric part. A tuning screw is installed on the PCB and inserted into the unmetallized blind hole to adjust the resonant frequency the DWR. This adjusting method is flexible and reversible. By using the proposed adjustable DWR, a fourth-order bandpass filter (BPF) is designed, fabricated and measured. The measured results show that the BPF is with an in-band insertion loss of 0.8 dB and an in-band return loss better than 19 dB. A capacitive cross coupling structure is constructed on the PCB so that two transmission zeros are introduced close to the passband to improve the filtering selectivity. In addition, a Wilkinson power divider is realized on the PCB and integrated with the above BPF, forming a filtering power divider. The measured in-band insertion loss of the filtering power divider is 1.1 dB. The isolation is better than 24 dB and the maximum phase imbalance is 1° in the passband.

"A Novel Capacitive Cross - Coupling for Enhancement of Microwave Cavity Filter"

Normally, the microwave cavity filter is cast and gilded, which causes a fixed transmission zero point. Thus, the specifications of the filter cannot be turned during its operation. A novel enhancement capacitive cross-coupling structure is proposed to fabricate a microwave cavity filter with a turnable transmission zero point. This structure is implemented by adding a new tap screw to the center of the supporting Teflon piece of cross-coupling dumbbell resulted in an adjustable capacitor. The capacitive cross-coupling factor is achieved a greater value leading to an improved slope of the cavity filter. The simulation results show that cross-coupling bandwidth can be varied in the range from 35.4 MHz to 40 MHz by changing the screw length from 0 mm to 7 mm, respectively. To verify the efficiency of the novel design, this structure is used to fabricate a microwave cavity filter in eNodeB for Band 3 - Long Term Evolution (LTE) application. The filter is built up of 10 coaxial resonator cavities with two new capacitive cross-couplings. The simulation results of the filter fully meet specification requirements including a band of 1805 to 1880 MHz, return loss below -12.7 dB, passband ripple of 0.1 dB, and insertion loss below 0.2dB. For a bandwidth below 20 MHz, the signal rejection reduces 1 dB by changing the screw length from 0 mm to 6 mm. In addition to Band 3, this structure can be developed for different frequency bands.

Harmonic biasing in a double-sided comb-drive resonator, for resolving feed-through issues in low-power driving

We demonstrate a novel technique for operating a differentially-driven and differentially-sensed double-sided comb-drive resonator. The resonator is driven by application of two out-of-phase ac signals to the drive stators, while the rotor is subjected to a pure harmonic signal at the same frequency as of the ac driving signals. In this mode of operation, no dc bias is necessary. This strategy results in two frequency-mixing operations, such that a clear response can be sensed at the 3rd harmonic of the drive signal. Besides the responses in the 1st and 3rd harmonics of the drive frequency, no other higher-harmonic components are predicted from the analysis or observed in the measurements. With harmonic biasing, the resonator is insensitive to both feed-through currents that result from direct capacitive cross-coupling of sense and drive pads, and to feed-through currents that result from imbalanced sense ports due to packaging and setup. We show that a clear response can be achieved for low-power drive signals, whereas if the system were driven as a classic resonator with a dc bias on the rotor, the response would have been overshadowed by feed-through. We also demonstrate that the phase of the sensed response can be modified by varying the phase of the harmonic bias on the rotor.

Design of High Performance Low-Noise Amplifier Circuit Based on Complementary Metal Oxide Semiconductor Technology

This paper designs a body-biased (BB) differential cascode low-noise amplifier (LNA) with current bias (CR) and capacitor cross-coupling (CCC) technology that meets the bandwidth requirements of 5 GHz wireless applications. In the design, the CCC technology in the differential cascode topology is used to effectively suppress the common mode noise, thereby improving the noise figure. The series resonant network eliminates parasitic capacitance at the input and output ends, thereby improving the power transmission efficiency. The CR technology formed by the intermediate capacitor shares the DC current input to the output device, thereby increasing the gain. This paper uses BB technology in the design to lower the threshold of the cascode device and improve the transconductance, which further improves the gain and reduces the power consumption. The CCC technology used in the paper improves linearity by eliminating the non-linear components present in the input device, which will not interfere with the transconductance of the output stage. This article has obtained excellent performance parameters including gain, noise figure (NF) and linearity without affecting the power consumption, integration and cost of the proposed design.

An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

Integrated multi-band RF transceiver design for multi-standard applications using 130 ​nm CMOS technology

This paper presents high efficiency, high integration, and wideband low-IF radio frequency transceiver for multi-standard applications using 130 ​nm CMOS technology. The proposed low-IF transceiver includes receiver, transmitter, and quadrature voltage-controlled power oscillator (QVCO). The proposed receiver consists of a low-noise driver stage designed using Capacitive Cross-Coupling (CCC) common-gate configuration, and I/Q demodulator. While, the proposed transmitter composes of an I/Q modulator and an RF power amplifier, where the I/Q modulator consists of two up-conversion mixers, a five ports transformer along with switched capacitors bank for reconfigurable RF output matching. The proposed receiver has a frequency band of 0–10 ​GHz, while the operating frequency of the proposed transmitter equals 1.5–4 ​GHz. The proposed RF transceiver design is suitable for multi-band LTE, IOT, WSN, and multi-standard applications. The proposed receiver achieves a power gain of 15.4 ​dB, noise figure (NF) equals 3.8 ​dB, sensitivity equals −100.2 dBm and a dynamic range of 92.2 dBm. On the other hand, the proposed transmitter has a saturated output power of 23 dBm, power added efficiency (PAE) equals 41%, the power gain of 25 ​dB, and adjacent channel power ratio (ACPR) of equals −31.8dBc. The proposed receiver and transmitter consume 10.85 ​mW, and 180.95 ​mW, respectively, including the QVCO. The receiver and transmitter Figures of Merit (FoM) equal 191.5 ​dB and 2.45 ​dB respectively. The active areas of the proposed receiver and transmitter equal 0.56mm2 and 1.6mm2, respectively while the chip areas are1.6mm2 and 2.4mm2, respectively.

C3PU: Cross-Coupling Capacitor Processing Unit Using Analog-Mixed Signal for AI Inference

This paper presents a novel cross-coupling capacitor processing unit (C3PU) that supports analog-mixed signal in-memory computing to perform multiply-and-accumulate (MAC) operations. The C3PU consists of a capacitive unit, a CMOS transistor, and a voltage-to-time converter (VTC). The capacitive unit serves as a computational element that holds the multiplier operand and performs multiplication once the multiplicand is applied at the terminal. The multiplicand is the input voltage that is converted to a pulse width signal using a low power VTC. The transistor transfers this multiplication where a voltage level is generated. A demonstrator of 5×4 C3PU array that is capable of implementing 4 MAC units is presented. The design has been verified using Monte Carlo simulation in 65 nm technology. The 5×4 C3PU consumed energy of 66.4 fJ/MAC at 0.3 V voltage supply with an error of 5.7%. The proposed unit achieves lower energy and occupies a smaller area by 3.4× and 3.6×, respectively, with similar error value when compared to a digital-based 8×4-bit fixed point MAC unit. The C3PU has been utilized through an iris flower classification utilizing an artificial neural network which achieved a 90% classification accuracy compared to ideal accuracy of 96.67% using MATLAB.

A Novel Capacitive Cross-Coupling Structure for Ceramic-Filled Cavity Filters

Since the probe coupling for cavity filters is unsuitable for ceramic-filled cavity filters, a novel capacitive cross-coupling structure is proposed to improve stopband suppression by introducing transmission zeros. This structure is implemented by first etching a coupling window on the silver-plated layer on the ceramic surface between two resonant cavities and then placing an isolated metal strip in the window. This structure enjoys high design freedom. Thus, the coupling coefficient between the two cavities is readily adjusted. Moreover, the structure has the advantages of a compact size and simple fabrication and tuning processes. For validation, a ten-pole ceramic-filled cavity filter for 5G applications is designed and evaluated. The proposed cross-coupling technology is used to introduce a pair of symmetrical transmission zeros at the band skirts to increase the frequency selectivity. The measured results are consistent with the simulated ones.

Multi-conductor coaxial cavity resonators for miniaturization of UHF bandpass filters

In this paper, we present the compact bandpass cavity filters for UHF range. We investigate the properties of coaxial resonators with various numbers of tubular posts from one to four. We show that the resonant frequency can be four times smaller for the four-post resonator in comparison with the single post resonator with the same cavity dimensions. We synthesized and manufactured fifth-order bandpass cavity filter on four-post coaxial resonators for the 690–806 MHz frequency range with 20-dB return loss. The filter dimensions were 30 mm × 44 mm × 127 mm. We also synthesized and manufactured the fifth-order bandpass cavity filter on four-post coaxial resonators with inductive and capacitive cross-coupling between first and fifth resonators to provide transmission zeros in amplitude–frequency characteristic in lower- and upper-frequency band, respectively. Comparison with the standard double-post coaxial cavity filters demonstrates more than 30% volume reduction with similar transmission characteristics.

Separated Circular Capacitive Coupler for Reducing Cross-Coupling Capacitance in Drone Wireless Power Transfer System

Capacitive power transfer (CPT) system can be employed for wireless charging of drone applications. However, in the CPT system, cross-coupling capacitance caused by coupling of the two pairs of plates on different sides, which do not form the main capacitance must be considered. Designs that do not properly consider the cross-coupling capacitance can cause decrease in the efficiency of the system. In this article, we propose a separate circular capacitive coupler for the CPT system. To reduce the cross-coupling capacitance in drone applications, the plates on the same side are separated. The circuit model of the coupler is presented; it considers a total of six coupling capacitances. For maximum power transfer efficiency, impedance of the receiver is considered to determine the parameter value of the LC resonance. Through simulation and measurement, we verified that the proposed separated circular coupler can reduce the cross-coupling capacitance. The plate-to-plate power transfer efficiency is maintained at 89.4% with 100-W output power.

Analysis of top- and side-contact MLGNR interconnects: impact on crosstalk, stability, and electromigration

In a recent nanoregime, the cross-coupling capacitance plays an important role due to the high packing density of integrated circuits. It can significantly affect the overall interconnect performance of an IC that can reduce the reliability, durability, and stability of silicon technology. In order to alleviate these problems, this work demonstrates shielded side-contact (SC) and top-contact (TC) multilayered graphene nanoribbon (MLGNR) interconnect to demonstrate stability and cross talk reliability issues. At 32 nm technology, an equivalent single-conductor Pi-type network is proposed for shielded SC- and TC-MLGNR for different spacing and interconnect lengths. Besides, the impact of temperature and higher current density is demonstrated. It is observed that the conventional interconnect material such as Cu exhibits 52.31% faster electromigration breakdown as compared to graphene at 1000 K. Further, the cross talk-induced delay is analyzed for shielded TC-and SC-MLGNR using driver–interconnect–load arrangement. An improved crosstalk-induced delay of 59.36% and 95.97% is observed for SC-MLGNR as compared to a TC-MLGNR with active shielding for an average spacing range of 5–20 nm at local and global lengths, respectively. Furthermore, the power delay product and peak noise of active-shielded SC-MLGNR exhibit on an average 96.82% and 38.20% improvement in comparison with active-shielded TC-MLGNR for the spacing of 5 nm at global length. Moreover, the Nyquist plot is used to demonstrate higher stability of SC-MLGNR than TC-MLGNR at 32 nm technology. Therefore, the overall system performance demonstrates that the active-shielded SC-MLGNR can be treated as a suitable choice for future VLSI technology.