Oxide Capacitance Research Articles

Compact device modelling of interface trap charges with quantum capacitance in MoS2-based field-effect transistors

An effective way to obtain interface trap density in transition metal dichalcogenide field-effect transistors (FETs) via compact device modelling is presented in this study. A computationally efficient model is utilised to evaluate the interface trap charges in a MoS2-based FET device. This model improves the accuracy of the computed surface potential, which is affected by trap charges. The existence of trap states on the interface level can be confirmed by studying the capacitance versus gate voltage () relationship. Most of the previously proposed models ignore the effect of the quantum capacitance when predicting the electrical performance of MoS2-FETs. The electrical performance of a metal-oxide-semiconductor FET with a two-dimensional (2D) molybdenum disulphide (MoS2) channel that introduces a quantum capacitance by including a gate is evaluated. The gate quantum capacitance in parallel with the interface trap capacitance is a second capacitance in series with the gate oxide capacitance and MoS2 capacitance This research explores the process of evaluating the interface trap density from published experimental data of MoS2-based FETs. Using the evaluated trap density values, the device parameters are calculated by considering the relative permittivity of the dielectric hafnium oxide (HfO2) layer, surface potential, interface trap charge and interface trap capacitance Finally, the calculated and experimental data are compared through the normalised root-mean-square deviations (RMSD) to validate the accuracy of the model.

High areal capacitance of vanadium oxides intercalated Ti3C2 MXene for flexible supercapacitors with high mass loading

Flexible all-solid-state supercapacitors (ASSSs) have caught the scientific attention to meet the explosive demand for portable and wearable electronic devices. However, it is difficult for flexible electrode materials to obtain a high areal capacitance at a high mass loading, which limits their commercial applications. In this study, vanadium oxide (V2O5) nanoparticles are introduced into Ti3C2 flakes with the aid of cetyltrimethylammonium bromide (CTAB). The intercalation of V2O5 particles in the interlayer of Ti3C2 establishes a hierarchical structure and facilitates the electrolyte penetration. As a result, the prepared CT-Ti3C2@V2O5 composite electrode achieves a high areal capacitance of 2065 mF cm−2 at 3 mA cm−2 and superior active mass loading (15 mg cm−2). Meanwhile, over 93% capacitance is maintained after 6000 cycles at 18 mA cm−2. The ASSS based on CT-Ti3C2@V2O5 delivers a high areal capacitance of 477 mF cm−2 at 1 mV s−1 and exhibits stable performance at different bending states, which reaches to the advanced level for the ASSSs based on MXenes.

The rate of Cu doped TiO2 interlayer effects on the electrical characteristics of Al/Cu:TiO2/n-Si (MOS) capacitors depend on frequency and voltage

In order to determine the surface states (Nss), series resistance (Rs), and (Cu:TiO2) interlayer effects on the electrical characteristics of the Al/Cu:TiO2/n-Si metal oxide semiconductor (MOS) capacitors, both capacitance (C) and conductance (G) values were measured for frequency ranges of 10 kHz–1 MHz and ±5 V voltage ranges. In addition, to know Cu doping concentration effect on the MOS capacitor, the Al/Cu:TiO2/n-Si was fabricated with various rates Cu:TiO2 interlayer (5, 10, 15%) grown on n-Si susbtrate by spin-coating. The increase in capacitance via decreasing frequencies was attributed to the existence of Nss and their relaxation time. The frequency dependent diffusion potential (Vd), doping of donor atoms (Nd), Fermi energy (EF), barrier height (Фb) and depletion layer width (Wd) values were extracted from the linear part of reverse bias C−2-V curves. While the value the Rs decreased with increasing frequency, the Nss values increased for the three MOS capacitors. The profiles of Nss and Rs depending on voltage were also plotted by Nicollian-Brews methods and using high-low frequency (CHF-CLF) capacitance, respectively. The mean values of Nss for three capacitors were found at about 1012 eV−1cm−2 as suitable electronic devices. The lower values of the Nss can be attributed to passivation effect of Cu:TiO2 interlayer.

Cu Doped Zinc Cobalt Oxide Based Solid-State Symmetric Supercapacitors: A Promising Key for High Energy Density

Improvement in the capacitance and energy density of zinc cobalt oxide based materials is vital for creating supercapacitors with excellent electrochemical performance. We synthesized Cu doped zinc...

Characterization of Oxide Film of Implantable Metals by Electrochemical Impedance Spectroscopy.

The oxide film resistance (RP) and capacitance (CCPE) diagrams of implantable metals (commercially pure Ti, four types of Ti alloys, Co–28Cr–6Mo alloy, and stainless steel) were investigated by electrochemical impedance spectroscopy (EIS). The thin oxide film formed on each implantable metal surface was observed in situ by field-emission transmission electron microscopy (FE-TEM). The Ti–15Zr–4Nb–1Ta and Ti–15Zr–4Nb–4Ta alloys had higher oxygen concentrations in the oxide films than the Ti–6Al–4V alloy. The thickness (d) of the TiO2 oxide films increased from approximately 3.5 to 7 nm with increasing anodic polarization potential from the open-circuit potential to a maximum of 0.5 V vs. a saturated calomel electrode (SCE) in 0.9% NaCl and Eagle’s minimum essential medium. RP for the Ti–15Zr–4Nb–1Ta and Ti–15Zr–4Nb–4Ta alloys was proportional to d obtained by FE-TEM. CCPE was proportional to 1/d. RP tended to decrease with increasing CCPE. RP was large (maximum: 13 MΩ·cm2) and CCPE was small (minimum: 12 μF·cm−2·sn−1, n = 0.94) for the Ti–15Zr–4Nb–(0 to 4)Ta alloys. The relative dielectric constant (εr) and resistivity (kOX) of the oxide films formed on these alloys were 136 and 2.4 × 106–1.8 × 107 (MΩ·cm), respectively. The Ta-free Ti–15Zr–4Nb alloy is expected to be employed as an implantable material for long-term use.

Facile synthesis of carbon nanotube-supported NiO//Fe2O3 for all-solid-state supercapacitors.

We have successfully prepared iron oxide and nickel oxide on carbon nanotubes on carbon cloth for the use in supercapacitors via a simple aqueous reduction method. The obtained carbon cloth–carbon nanotube@metal oxide (CC-CNT@MO) three-dimensional structures combine the high specific capacitance and rich redox sites of metal oxides with the large specific area and high electrical conductivity of carbon nanotubes. The prepared CC-CNT@Fe2O3 anode reaches a high capacity of 226 mAh·g−1 at 2 A·g−1 with a capacitance retention of 40% at 40 A·g−1. The obtained CC-CNT@NiO cathode exhibits a high capacity of 527 mAh·g−1 at 2 A·g−1 and an excellent rate capability with a capacitance retention of 78% even at 40 A·g−1. The all-solid-state asymmetric supercapacitor fabricated with these two electrodes delivers a high energy density of 63.3 Wh·kg−1 at 1.6 kW·kg−1 and retains 83% of its initial capacitance after 5000 cycles. These results demonstrate that our simple aqueous reduction method to combine CNT and metal oxides reveals an exciting future in constructing high-performance supercapacitors.

Nonvolatile reversible capacitance changes through filament formation in a floating-gate metal-oxide-semiconductor capacitor with Ag/CeOx/Pt/HfOx/n-Si structure

Nonvolatile and reversible capacitance changes are demonstrated in a floating-gate metal-oxide-semiconductor (FG-MOS) capacitor with a Ag-control-gate/CeOx-control-oxide/Pt-floating-gate/HfOx-tunneling-oxide/n-Si structure. Different from the conventional floating-gate MOS field-effect-transistor (MOSFET) operating with a threshold voltage shift by electrical charging in the floating-gate (charge storage node), the proposed device operates with the change of gate oxide capacitance as one of the parameters determining the electrical properties of MOSFET. Applying positive voltage to the Ag control-gate forms a conducting filament in the Ag/CeOx/Pt stack and consequently increases the gate oxide capacitance. The accumulation capacitance increases from the capacitance of serial capacitors consisting of Ag/CeOx/Pt and Pt/HfOx/n-Si before the filament formation to that of a single capacitor of Pt/HfOx/n-Si after the filament formation. The capacitance is reversibly decreased to the initial value by rupturing the filament upon applying negative voltage. The change of capacitance is stable over time with the retention >90% for 12 h of measured time. These noncharge-storage-based nonvolatile and reversible changes in the gate oxide capacitance through the filament formation would modulate the MOSFET properties with the advantages of better uniformity, superior immunity to the radiation, and less cross talk between adjacent devices for the application to nonvolatile memory and programmable logic devices.

Highly-dispersed Fe2O3@C electrode materials for Pb2+ removal by capacitive deionization

Capacitive deionization (CDI) is increasingly being considered as an effective solution for treating heavy-metal contaminated water. Surface modification of electrode materials with metal oxides is the key to yield high specific capacitance of transition metal oxides for enhancing the efficiency of CDI processes. In this study, we proposed a simple and effective strategy to produce a new, well-ordered Fe2O3@C composite for Pb2+ removal via CDI technology. Through controlling hydrofluoric acid-inducing solvothermal carbonization, Fe2O3 dots were highly dispersed in carbonized substrates without using traditional high-temperature calcination. The products possessed regular octahedral morphology with a uniform distribution of α-Fe2O3 in nearly quantum scale (∼20 nm) throughout the carbon matrixes. Compared with other similar materials, the well-dispersed Fe2O3 in carbon matrixes significantly increased the surface areas (∼1832 m2 g−1) and specific capacitance (115.6 F g−1) of Fe2O3@C composites. Using the composites as electrodes, the Pb2+ adsorption capacity reached 830.17 mg g−1, which is 28% higher than reported materials. Furthermore, the composites electrode possess a high regeneration efficiency, after 10 cycles, 90.3% of the initial performance is still retained. Our study demonstrated great potential of the novel Fe2O3@C composites for the removal of heavy metal ions using CDI processes.

Enhanced capacitance of hydrous ruthenium oxide based all-solid-state interdigital in-planar micro-supercapacitors

Pattern design is a critical strategy to improve the performance of interdigital in-planar micro-supercapacitors (μ-SCs) in a fixed footprint area. Pattern optimization can synchronously achieve sufficient improvement without changing the materials used or the fabrication technologies. A simple adjustment of the interdigitated-electrode width-to-length ratio without changing the widths of gaps or the interdigitated electrodes themselves is reported for pattern design in this study. The results show that the geometric configuration plays a key role in improving the electrochemical performance of the interdigital in-planar μ-SCs. Nanocomposites exhibit properties different from those of their individual constituents, leading to new properties. The utilization of hydrous ruthenium oxide/reduced graphene oxide (hRuO2/rGO) composites integrating the merits of both pseudocapacitors and electrical double-layer capacitors is another important strategy for fabricating high-performance μ-SCs. In this report, we investigated the influence of the geometric configuration of interdigitated electrodes and the utilization of a hRuO2/rGO composite for interdigital in-planar μ-SCs. Through the combination of the advantages of both strategies (i.e., pattern design and hRuO2/rGO composite), all-solid-state interdigital in-planar μ-SCs assembled using the hRuO2/rGO composite and a gel electrolyte and constructed with the optimal pattern process exhibited a low electrical resistance, good frequency response and relaxation constant, high areal capacitance, good rate capability, and excellent capacitance retention.

The Effect of Macroheterocyclic Compounds and Their Metallocomplexes on Temperature-Frequency Characteristics of Aluminum Oxide Electrolytic Capacitors

The effect of addition of mactoheterocyclic compounds of the ABAB and A′BBB types, in which A (1,3-phenylene or 2,6-pyridine)moiety, A′ (1,3-phenylene)moiety, and A′ (1,3-isoindoline)moiety are interlinked by aza-bridges, and also of their complexes with copper(II) and cobalt(II) on the temperature-frequency characteristics of small-scale aluminum oxide capacitors with the vertical chip design is studied in the temperature range from −60°C to +100°C and the frequency range from 50 Hz to 200 kHz. It is shown that under conditions studied, the addition of macroheterocycles and their complexes decreases the resistance and the leakage currents of capacitor.

Modulating the electronic structure and pseudocapacitance of δ-MnO2 through transitional metal M (M = Fe, Co and Ni) doping

The experimental capacitance of manganese oxide (MnO2) is ordinarily less than 100 F/g due to their poor electronic conductivity and low structural stability. Herein, we demonstrate the design and synthesis of doped δ-MnO2 with enhanced electronic conductivity by the introduction of transitional metal Fe, Co and Ni. Structural characterizations shown that the Raman spectra of doped MnO2 has obviously blue shifted, as well as the separation values of Mn 3s XPS spectra has expanded, which indicate the transitional metal doping successfully changes the crystal lattice of δ-MnO2. The I-V measurements confirm that the electronic conductivity of MnO2 is significantly improved after doping. As a result, the Fe doped δ-MnO2 with a 0.5% doping amount displays the highest specific capacitance of 157 F/g at 0.5 A/g, by increasing 50.4% of the specific capacity than non-doped MnO2. Simultaneously, the Co doped δ-MnO2 exhibits the superb cycling stability (almost no degradation). Furthermore, the assembled 0.5% FeMO//AC, 1% CoMO//AC and 1% NiMO//AC asymmetric supercapacitor provide a specific energy densities of 30.3, 25.2 and 23.6 Wh/kg at a power density of 1000 Wh/kg. The excellent properties of as-prepared MnO2 are due to the enhanced conductivity after doping, which can ascribed to the forming of intermediate bands, or changing the intensity of valence band/conduction band as demonstrated by spin-polarized density functional (DFT) calculations. Thus, the current work will provide a pathway for the development of high-performance pseudocapacitive materials, as well as for other energy storage systems.

Low-cost spray-deposited ZrO2 for antireflection in Si solar cells

Low-cost spray deposition is employed to investigate the possibility of using earth-abundant ZrO2 as the antireflection coating in Si solar cells. Structural, optical, and electrical properties of spray-deposited ZrO2 films are investigated. Spray-deposited ZrO2 is highly transparent with a refractive index of 2.0 at 600 nm. Reflection and transmission spectra of ZrO2 films reveal that the optical properties of spray-deposited ZrO2 are comparable to SiNx deposited by plasma-enhanced chemical vapor deposition. Atomic force microscopy studies show that spray-deposited ZrO2 is crack/pore-free and its surface roughness has a root-mean-square value of 0.7 nm for a 75-nm film. Spray-deposited ZrO2 at 550 °C is polycrystalline with a cubic lattice but largely amorphous at 450 °C as determined by X-ray diffraction. Capacitance-voltage measurements indicate that spray-deposited ZrO2 has a negative charge density of 8.19 × 1011 cm−2 for a 75-nm film. Post-deposition annealing results in a significant decrease in oxide capacitance which is attributed to the formation of SiO2 at the ZrO2/Si interface. The resistivity of as-deposited ZrO2 is 3.69 × 1012 Ω-cm and it improves to 2.46 × 1013 Ω-cm after post-deposition annealing in air at 600 °C for 1 h.

Studies of radiation effects in Al2O3-based metal-oxide-semiconductor structures induced by Si heavy ions

The radiation effects of metal-oxide-semiconductor (MOS) capacitors based on an Al2O3 gate dielectric were studied using 30 MeV Si heavy ions. To give insights into the types of defects induced by Si ion irradiation in the gate oxide, synergistic experiments involving γ-ray irradiation and Si ion irradiation were carried out. The results revealed that the defects in the as-grown Al2O3 layer were found to be hole trapping centers, whereas Si ion induced new defects were electron trapping centers. The experimental and simulation data of current density-voltage (J-V) curves confirmed that the transmission mechanism of leakage current in the Al2O3 layer was mainly dominated by the Frenkel-Poole mechanism. In detail, the variations of leakage current were mainly due to the attributions of the local built-in electric field-assisted current leakage and the conductive path-assisted current leakage and were found to be dependent on the irradiation condition and Al2O3 thickness. Lastly, the decrease of the gate oxide capacitance of MOS capacitors was attributed to the increase of the series resistance and leakage current in MOS capacitors.

Graphene Oxide as a Dielectric and Charge Trap Element in Pentacene-Based Organic Thin-Film Transistors for Nonvolatile Memory.

In this report, the dielectric nature of graphene oxide (GO) was exploited for the successful implementation of low-power pentacene thin-film transistors suitable for nonvolatile memory applications. Two different types of devices were fabricated on indium tin oxide-coated glass substrates with two different metals, viz., gold and aluminum, as the source and drain contacts. The performance of the devices was analyzed from their field-effect characteristics. Both the devices showed dominant p-type charge transport behavior. The breakdown electric field was determined to be 1.02 × 108 V/m. The current transport mechanism was explained from the output characteristics using the Fowler–Nordheim tunneling theory. Capacitance–voltage (C–V) measurements have been employed to determine the value of the oxide capacitance and to examine the memory effect. The hysteresis behavior observed from the C–V characteristics show the suitability of the device for memory applications with a low operating voltage of 3 V. The charge trapping behavior of GO was explained by the energy band diagram. Frequency-dependent C–V measurements in the range 100 kHz to 1 MHz were also performed to account for the memory window obtained in the devices. The charge retention and endurance characteristics were evaluated under a constant voltage stress to check the reliability of device operation.

Structural engineering to maintain the superior capacitance of molybdenum oxides at ultrahigh mass loadings

An ultrahigh loaded MoO3−x electrode was developed with improved rate capability through incorporating layered structure graphite sheets and oxygen functional groups.

A Substrate Model for On-Chip Tapered Spiral Inductors With Forward and Reverse Excitations

In this brief, closed-form analytical expressions are obtained to accurately calculate the oxide and substrate (both lateral/vertical) capacitances of the $\pi $ -equivalent circuit model for on-chip tapered spiral inductors. A lateral RC substrate network using the above-mentioned expressions is shown to significantly improve the model accuracy, especially with lower substrate resistivities. Furthermore, improvement in Qmax with reverse excitation in tapered spirals is also accurately predicted by the proposed model. The accuracy of the proposed model is validated till 15 GHz using several inductor geometries across process parameters suitable for the design of RF circuits. Excellent agreement is observed between the model, electromagnetic simulations, and measurements.

Large Errors from Assuming Equivalent DC and High-Frequency Electrical Characteristics in Metal–Multiple-Insulator–Metal Diodes

Metal–insulator–metal (MIM) tunnel diodes are essential for ultra-high-speed rectification. We review an erroneous method for distributing DC voltage drops across multiple insulator layers that is used in all the published literature on these devices. It has resulted in large errors between designed and fabricated multi-insulator diodes. For multi-insulator MIM diodes, voltage division is dependent on both tunneling resistances and oxide capacitances. We demonstrate that correct voltage division at DC is determined by the rectification resistance, as opposed to the commonly used capacitive voltage division. We find that DC characteristics of multi-insulator diodes cannot be used to predict high-frequency behavior.

Three-Dimensional Transport Simulations and Modeling of Densely Packed CNTFETs

Carbon nanotube (CNT) field-effect transistor (FET) based applications require multiple CNTs with small tube pitches for competing with existing silicon technologies. The associated dense packing of CNTs leads to electrostatic interactions between the tubes also known as screening effects. In this paper, the impact of the latter on the CNT current and charge density has been investigated by means of three-dimensional (3D) device simulation (TCAD), in which the CNT is represented by its actual 3D structure rather than by a one-dimensional (1D) line, allowing to include the effects of an inhomogeneous charge and current density distribution along the CNT circumference. Different analytical models describing the impact of the oxide thickness, CNT diameter and CNT pitch on the oxide capacitance are compared. Using the most accurate model, the dependence of drain current, transconductance, subthreshold slope and transit frequency on the above mentioned parameters has been determined using TCAD simulations.

A Novel DRAM Cell Structure with Parasitic Storage Capacitance for SoCs on SoI Wafer in 65nm Planar MOS Technology

A novel 65nm Dynamic Random access memory (DRAM) cell, namely capacitor less RectFET based DRAM cell (CLRDC) is explored in silicon-on-insulator (SoI) wafer for embedded-DRAM (eDRAM) for system-on-chip (SoC), applications with Rectangular FET (RectFET) as its pass-transistor (PT). This CLRDC exploits its parasitic surround buried oxide capacitance (SBC) of SoI-wafer around RectFET (source) for realizing its ‘charge storage capacitance (Cs). For Cs=30fF (femtoFarad) target, it’s found to need an area factor of 4.3µm2 with 5nm thick SoI buried-oxide. This SoI wafer is explored to yield a capacitance density Cbuox=6.91 fF/µm2. The DC parameters of the PT are found to be very sensitive to process anneal temperature (Ta) and so are its DC characteristics too. A 2% increase in the Ta from a nominal 1000oC has resulted in an increase of 30% and 1.1% in the RectFET’s leakage (Idsat-off=I-off) and on-state (Idsat-on=I-on) currents respectively. The CLRDC cell transfer ratio T is also found to be a function of small signal frequency (f), Ta, and source/drain bias voltages Vs/Vd, respectively. And finally the retention characteristics of this CLRDC is again found to be a function of I-off and I-on currents of RectFET, when studied at RectFET’s (drain) supply voltage VDD=1.2V.

A Novel DRAM Cell Structure with Parasitic Storage Capacitance for SoCs on SoI Wafer in 65nm Planar MOS Technology

A novel 65nm Dynamic Random access memory (DRAM) cell, namely capacitor less RectFET based DRAM cell (CLRDC) is explored in silicon-on-insulator (SoI) wafer for embedded-DRAM (eDRAM) for system-on-chip (SoC), applications with Rectangular FET (RectFET) as its pass-transistor (PT). This CLRDC exploits its parasitic surround buried oxide capacitance (SBC) of SoI-wafer around RectFET (source) for realizing its ‘charge storage capacitance (Cs). For Cs=30fF (femtoFarad) target, it’s found to need an area factor of 4.3µm2 with 5nm thick SoI buried-oxide. This SoI wafer is explored to yield a capacitance density Cbuox=6.91 fF/µm2. The DC parameters of the PT are found to be very sensitive to process anneal temperature (Ta) and so are its DC characteristics too. A 2% increase in the Ta from a nominal 1000oC has resulted in an increase of 30% and 1.1% in the RectFET’s leakage (Idsat-off=I-off) and on-state (Idsat-on=I-on) currents respectively. The CLRDC cell transfer ratio T is also found to be a function of small signal frequency (f), Ta, and source/drain bias voltages Vs/Vd, respectively. And finally the retention characteristics of this CLRDC is again found to be a function of I-off and I-on currents of RectFET, when studied at RectFET’s (drain) supply voltage VDD=1.2V.