Capacitance Bridge Research Articles

A Nine-Level Inverter Topology for Medium-Voltage Induction Motor Drive With Open-End Stator Winding

A new scheme for nine-level voltage space-vector generation for medium-voltage induction motor (IM) drives with open-end stator winding is presented in this paper. The proposed nine-level power converter topology consists of two conventional three-phase two-level voltage source inverters powered by isolated dc sources and six floating-capacitor-connected $H$ -bridges. The $H$ -bridge capacitor voltages are effectively maintained at the required asymmetrical levels by employing a space vector modulation (SVPWM) based control strategy. An interesting feature of this topology is its ability to function in five- or three-level mode, in the entire modulation range, at full-power rating, in the event of any failure in the $H$ -bridges. This feature significantly improves the reliability of the proposed drive system. Each leg of the three-phase two-level inverters used in this topology switches only for a half cycle of the reference voltage waveform. Hence, the effective switching frequency is reduced by half, resulting in switching loss reduction in high-voltage devices. The transient as well as the steady-state performance of the proposed nine-level inverter-fed IM drive system is experimentally verified in the entire modulation range including the overmodulation region.

Semi-conducting carbon nanotube as variable capacitor

This paper proposes a novel, one-part, variable capacitor, using semi-conducting carbon nanotube (CNT). This variable capacitor works based on the change in the electronic structure of CNTs under applied voltage and deformations. Positive and negative charges are stored at both ends of a non-zero band gap nanotube which works as metallic electrodes in parallel plate capacitors. Also the neutral strip in the middle acts as the dielectric part of a conventional capacitor under the influence of an external electric field. Mechanical strains on carbon nanotube change its band gap energy and thus the length of neutral strip and charged regions. The lengths of these parts are primarily dependent on the nanotube chirality, deformation mode and applied voltage. This way, different parts of a conventional cantilever, parallel plate or bridge capacitor are reduced to a one part semi-conducting CNT capacitor. Analytical calculations based on classical electrostatics and density of states (DOS) relations are employed to investigate the effect of CNTs geometry, applied voltage and deformations on capacitive features. The proposed CNT-variable-capacitor can be useful for nano-electromechanical systems (NEMS), including displacement measurement sensors and tunable capacitor in integrated circuits.

Electrodeposition and characterization of magnetostrictive galfenol (FeGa) thin films for use in microelectromechanical systems

In this paper, we investigate the challenges related to electrodeposition and characterization of magnetostrictive galfenol thin films as well as techniques used to overcome these issues. Successful deposition and evaluation of galfenol thin films is necessary for the design of galfenol based microelectromechanical devices. Stress is a primary concern because thick films and poor adhesion to substrates (e.g., silicon oxide) can lead to delamination and peeling. In addition, magnetostriction measurements require films that are uniform in thickness and composition over the sample area. Various adhesion layers were tested, and delamination was eliminated with Cr/Cu, which provided robust adhesion to the glass substrates used in capacitance bridge measurements. Uniformity and composition were controlled by the use of a rotating disk electrode for electrodeposition, which created a uniform boundary condition across the sample during deposition. The capacitance bridge technique was calibrated with Ni/glass samples, after which a magnetostriction of 140 ppm was measured for Fe83Ga17 films. These results represent the first magnetostriction measurements of electrodeposited galfenol.

A Method for Supply Voltage Boosting in an Open-Ended Induction Machine Using a Dual Inverter System With a Floating Capacitor Bridge

An operational approach to an induction machine is presented that uses an open winding connected to a dual inverter system. A floating capacitor inverter bridge boosts the fundamental voltage available to the machine and arbitrarily sets the operating power factor of the main inverter bridge connected to the dc battery power source. During operation, the motor current charges the floating bridge dc capacitor voltage to a naturally stable dc voltage level and the ac voltage delivered to the machine is the resultant sum of the two inverter bridge voltages. Machine voltage boosting is then achieved by adjusting the fundamental phase angle difference between the two inverters to control the charge stored in the floating bridge capacitors. With the floating bridge providing reactive voltage support and therefore boosting the available supply voltage to the induction machine, there are two main outcomes: minimization of the supply current required for operation beyond the base speed of the electric machine, and supply voltage regulation of the drive system. Experimental results are used to verify the operation of the floating bridge arrangement by examining the load power factor angle and the phase difference between the two bridges. Results are presented for a passive RL load to illustrate the supply current reduction at high fundamental frequency operation, and a modified 2-hp, 1800-r/min induction to illustrate the dc voltage supply droop compensation.

Ku-band RF MEMS tunable comb line band reject filter on coplanar transmission line

A band reject filter with tuning capability is presented on a CPW transmission line on silicon substrate using comb line and RF MEMS variable capacitor, enabling compatibility with planar IC technology. A conventional CPW on a substrate consists of a central strip conductor with semi-infinite ground planes on either side. A comb line is etched on the signal line of the CPW and the MEMS bridge capacitor is put on the same line in shunt. Tunability of the filter is achieved by putting the MEMS bridge in either up or down state. The rejection at the centre frequency of stop bands are around −40.24dB for down state and −38.21dB for up state of the bridge. A low insertion loss, as low as −0.68dB, is obtained in the pass band. The proposed device structure is simulated using ANSOFT HFSS v13® for RF analysis and COVENTORWARE (2008)® for mechanical and electromechanical characterization, both static and transient analysis.

Unit capacitor array based SAR ADC

This paper proposes a new successive approximation register analog-to-digital converter by using a unit capacitor array to implement the digital-to-analog converter. Under the same differential non-linearity specification, the proposed method can consume orders of magnitude less switching power and chip area than all existing solutions, including those using a binary weighted capacitor array (with or without a bridge capacitor) and those using a split capacitor array. The claimed benefits of the proposed method are verified by behavioral simulations.

A compact and miniaturized high resolution capacitance dilatometer for measuring thermal expansion and magnetostriction

We describe the design, construction, calibration, and two different applications of a miniature capacitance dilatometer. The device is suitable for thermal expansion and magnetostriction measurements from 300 K down to about 25 mK, with a resolution of 0.02 Å at low temperatures. The main body of the dilatometer is fabricated from a single block of a Be-Cu alloy by electrical discharge milling. This creates an extremely compact high-resolution measuring cell. We have successfully tested and operated dilatometers of this new type with the commonly used physical property measurement system by quantum design, as well as with several other cryogenic refrigeration systems down to 25 mK and in magnetic fields up to 20 T. Here, the capacitance is measured with a commercially available capacitance bridge. Using a piezoelectric rotator from Attocube Systems, the cell can be rotated at T = 25 mK inside of an inner vacuum chamber of 40 mm diameter. The miniaturized design for the one-axis rotation setup allows a rotation of 360°.

Integration of Microfabricated Capacitive Bridge and Thermistor on the Alumina Substrates

This paper describes a thin film fabrication technique of planar metallic microstructure with geometries between 10 and 20μm on 96% alumina substrate. This technique integrates a microfabricated capacitive bridge and thermistor on the same substrate employing metal and vacuum deposition. The procedure showed good resolution using a substrate with medium grain size between 3-5μm and average peak to valley surface roughness (Ra) 0.1μm. The film adhesion was tested by soldering metallic wires on the capacitor electrodes. These structures can be used for thin film characterization. We also deposited an oxide thin film (TiO2:WO3) by using polymeric precursors method.

‘Galileo Galilei’ (GG): space test of the weak equivalence principle to 10−17 and laboratory demonstrations

The small satellite ‘Galileo Galilei’ (GG) will test the universality of free fall and hence the weak equivalence principle which is the founding pillar of general relativity to 1 part in 1017. It will use proof masses whose atoms differ substantially from one another in their mass energy content, so as to maximize the chance of violation. GG will improve by four orders of magnitude the current best ‘Eöt-Wash’ tests based on slowly rotating torsion balances, which have been able to reach their thermal noise level. In GG, the expected violation signal is a relative displacement between the proof masses of ≃ 0.6 pm caused by a differential acceleration aGG ≃ 8 × 10−17 ms−2 pointing to the center of mass of the Earth as the satellite orbits around it at νGG ≃ 1.7 × 10−4 Hz. GG will fly an innovative acceleration sensor based on rapidly rotating macroscopic test masses weakly coupled in 2D which up-converts the signal to νspin ≃ 1 Hz, a value well above the frequency of natural oscillations of the masses relative to each other νd = 1/Td ≃ 1/(540 s). The sensor is unique in that it ensures high rotation frequency, low thermal noise and no attenuation of the signal strength (Pegna et al 2011 Phys. Rev. Lett. 107 200801). A readout based on a very low noise laser interferometry gauge developed at Jet Propulsion Laboratory (≃ 1 pm Hz−1/2 at 1 Hz demonstrated) allows the short integration time to be fully exploited. A full scale sensor with the same degrees of freedom and the same dynamical features as the one to fly in GG has been setup on ground (GGG). The proof masses of GGG are affected by acceleration and tilt noise acting on the rotating shaft because of ball bearings and terrain microseismicity (both absent in space). Overall, by means of appropriate 2D flexure joints, these noise sources have been reduced by a factor almost 105 down to a differential acceleration between the proof masses of ≃ 7 × 10−11 m s−2 (at 1.7 × 10−4 Hz up-converted by rotation to ≃ 0.2 Hz). The corresponding noise in the relative displacements of the proof masses, read by co-rotating capacitance bridges, is ≃ 180 pm, which is 300 times larger than the target in space. GGG error budget shows that it can reach a differential acceleration sensitivity aGGGgoal ≃ 8 × 10−16 m s−2, not limited by thermal noise. This value is only a factor 10 larger than what GG must reach in space to meet its target, and slightly smaller than the acceleration noise of the torsion balance. It can be achieved partly by means of weaker joints and an optimized mechanical design—so as to improve the attenuation factor—and partly by replacing the current ball bearings with much less noisy air bearings (also used in torsion balance tests) so as to reduce input noise. A laser gauge readout with noise level rlaser-ro ≃ 30 pm Hz−1/2 at 0.2÷3 Hz will be implemented.

A Two-Stage, Guarded Inductive Voltage Divider with Small Ratio Errors for Coaxial Bridge Applications

The traceability chain to derive the capacitance unit from the quantum Hall resistance comprises some coaxial bridges. These bridges employ a main two-stage inductive voltage divider to provide the voltage ratio needed. One such divider has been recently constructed and calibrated at Inmetro. The design techniques responsible for the small ratio errors of the device and the calibration method employed are both detailed. The new divider was installed in Inmetro's two terminal-pair coaxial capacitance bridge with significant improvements in the bridge resolution and accuracy.

Embryonic assembly of auditory circuits: spiral ganglion and brainstem

During early development, peripheral sensory systems generate physiological activity prior to exposure to normal environmental stimuli. This activity is thought to facilitate maturation of these neurons and their connections, perhaps even promoting efficacy or modifying downstream circuitry. In the mammalian auditory system, initial connections form at embryonic ages, but the functional characteristics of these early neural connections have not been assayed. We investigated processes of embryonic auditory development using a whole-head slice preparation that preserved connectivity between peripheral and brainstem stations of the auditory pathway. Transgenic mice expressing fluorescent protein provided observation of spiral ganglion and cochlear nucleus neurons to facilitate targeted electrophysiological recording. Here we demonstrate an apparent peripheral-to-central order for circuit maturation. Spiral ganglion cells acquire action potential-generating capacity at embryonic day 14 (E14), the earliest age tested, and action potential waveforms begin to mature in advance of comparable states for neurons of the ventral cochlear nucleus (VCN) and medial nucleus of the trapezoid body (MNTB). In accordance, auditory nerve synapses in the VCN are functional at E15, prior to VCN connectivity with the MNTB, which occurs at least 1 day later. Spiral ganglion neurons exhibit spontaneous activity at least by E14 and are able to drive third-order auditory brainstem neurons by E17. This activity precedes cochlear-generated wave activity by 4 days and ear canal opening by at least 2 weeks. Together, these findings reveal a previously unknown initial developmental phase for auditory maturation, and further implicate the spiral ganglion as a potential controlling centre in this process.

A compact capacitive dilatometer for thermal expansion and magnetostriction measurements at millikelvin temperatures

We describe a compact capacitive dilatometer for measuring thermal expansion and magnetostriction below 1K using a home-made capacitance bridge with long-term stability of ΔC/C∼1.6×10−7. We measured the thermal expansion and magnetostriction of a heavy-Fermion compound CeRu2Si2 and those of a standard copper sample to clarify the dilatometer cell effect. The temperature-dependent cell effect of our dilatometer, ΔL/L, was less than 10−8 below 0.2K. The magnetic-field-dependent cell effect was not observed below 52.6mT at 85mK, and was less than −2×10−9 up to 10T at 4.2K. Our dilatometer provides precise thermal expansion and magnetostriction measurements at millikelvin temperatures.

Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits

Three-dimensional stacked IC (3D-SIC) is a hot topic in both research and engineering circles alike. Multiple dies in a single package are not an entirely new phenomenon, as we already witnessed the use of Multi-Chip Modules (MCMs) two or three decades ago. We have even utilized vertical stacking of multiple chips, under terms as Package-onPackage (PoP) and System-in-Package (SiP). Recently however, a new and strong boost has been given to 3D die stacking with the advent of process technologies that enable the manufacturing of wafers containing Through-Silicon Vias (TSVs). TSVs allow architecting single-package multi-chip products using vertical interconnects with unprecedented density, performance, and low-power dissipation, thereby enabling the creation of a new generation of ‘super chips’. Test challenges are often considered as major obstacles to be resolved before bringing 3D-SICs to market. The readers of JETTA probably know better than others that a semiconductor product is not ready for volume production, if it cannot be adequately tested for manufacturing defects. The fact that today many researchers and practitioners from the test community are working on these 3D-SIC test challenges is a positive sign indicating that the TSV-based stacking technology is preparing itself for prime-time. The level of professional activities has drastically increased, as we witnessed the increase from a single conference paper in 2007 to now numerous publications, conference sessions, tutorials, a thriving 3D test access architecture standardization working group: IEEE P1838 (http://grouper.ieee.org/ groups/3Dtest), and even a dedicated workshop: the IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (http://3dtest.tttc-events.org). The 3D-TEST Workshop has already had two very successful editions in 2010 and 2011, and its third edition is scheduled for November 2012, again in conjunction with ITC. What was so far still missing in this palette of activities was a journal special issue. That is now a reality with this February 2012 edition of JETTA. We find it quite appropriate for JETTA to be the first to publish a special issue on 3D-SIC testing, as after all this is the only journal devoted to test technology. The open Call for Papers for this special issue was first published at the 3D-TEST Workshop 2010 with its submission deadline in January 2011. We received a good set of submissions, which were all subjected to a thorough peer review process with, in most cases, multiple iterations between authors and reviewers. The result is in front of you: a special issue with ten articles covering 3D-SIC testing from various angles. This special issue starts off with a paper on test economics by Mottaqiallah Taouil et al. (Delft University of Technology and IMEC), entitled ‘Test Impact on the Overall Dieto-Wafer 3D Stacked IC Cost’. The authors evaluate various test flows that include or exclude pre-, mid-, and post-bond tests with respect to their impact on overall product costs. This is followed by two articles on defect-oriented testing. Yi Lou et al. (North-Carolina State University) compare sense amplification, leakage current monitors, and capacitance bridge methods as three pre-bond TSV test methods in ‘Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect E. J. Marinissen (*) IMEC, Kapeldreef 75, B-3001 Leuven, Belgium e-mail: erik.jan.marinissen@imec.be

Tunable Lowpass Filter with RF MEMS Capacitance and Transmission Line

We have presented an RF MEMS tuneable lowpass filter. Both distributed transmission lines and RF MEMS capacitances were used to replace the lumped elements. The use of RF MEMS capacitances gives the flexibility of tuning the cutoff frequency of the lowpass filter. We have designed a low-pass filter at 9–12 GHz cutoff frequency using the theory of stepped impedance transmission lines. A prototype of the filter has been fabricated using parallel plate capacitances. The variable shunt capacitances are formed by a combination of a number of parallel plate RF MEMS capacitances. The cutoff frequency is tuned from C to X band by actuating different combinations of parallel capacitive bridges. The measurement results agree well with the simulation result.

Erratum: “An integrated capacitance bridge for high-resolution, wide temperature range quantum capacitance measurements” [Rev. Sci. Instrum. 82, 053904 (2011)

Arash Hazeghi, Joseph A. Sulpizio, Georgi Diankov, David Goldhaber-Gordon, and H. S. Philip Wong Citation: Rev. Sci. Instrum. 82, 129901 (2011); doi: 10.1063/1.3665097 View online: http://dx.doi.org/10.1063/1.3665097 View Table of Contents: http://rsi.aip.org/resource/1/RSINAK/v82/i12 Published by the AIP Publishing LLC.

Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods

Three methods have been proposed to test Through-Silicon-Vias (TSV) electrically prior to 3D integration. These test methods are (1) sense amplification; (2) leakage current monitor; and (3) capacitance bridge methods. These tests are aimed at detecting one or both of two failure types, pin-holes and voids. The test circuits measure capacitance and leakage current of the TSVs, and generate a 1 bit pass/fail signal. The outputs are streamed out through a scan chain. The test time is 10 μs for the leakage test and the sense amplification methods, and is 15 μs for the capacitive bridge method. All these methods can be implemented for test-before-stacking, which will increase assembled yield. Resolution, power and area of these TSV test circuits were compared. The performance of each circuit was studied at PVT corners. The IMEC TSV technology was assumed, and the designs were simulated using the 32 nm predicted device model. Without any failure, the TSV capacitance's mean value is 37 fF, and its leakage resistance is higher than 850 M?. With respect to 37 fF standard capacitance, resolution for the sense amplification method is 3.3 fF (8.9%); it is 0.16 fF (0.4%) for the capacitance bridge method. Although the capacitance bridge method has relatively better resolution, it takes 4x area and 10x power than the other two, and is also more sensitive to PVT variation. Resolution of the leakage current monitor method is 10 M? (1.1%) with respect to its threshold 850 M?, and use 42.5aJ power in normal case. Sense amplification circuit can be modified to detect equivalent leakage resistance under 2K?.

Determination of the Boltzmann constant by dielectric-constant gas thermometry

Within an international project directed to the new definition of the base unit kelvin, the Boltzmann constant k has been determined by dielectric-constant gas thermometry at PTB. In the pressure range from about 1 MPa to 7 MPa, 11 helium isotherms have been measured at the triple point of water (TPW) by applying a new special experimental setup consisting of a large-volume thermostat, a vacuum-isolated measuring system, stainless-steel 10 pF cylindrical capacitors, an autotransformer ratio capacitance bridge, a high-purity gas-handling system including a mass spectrometer, and traceably calibrated special pressure balances with piston–cylinder assemblies having effective areas of 2 cm2. The value of k has been deduced from the linear, ideal-gas term of an appropriate virial expansion fitted to the combined isotherms. A detailed uncertainty budget has been established by performing Monte Carlo simulations. The main uncertainty components result from the measurement of pressure and capacitance as well as the influence of the effective compressibility of the measuring capacitor and impurities contained in the helium gas. The combination of the results obtained at the TPW (kTPW = 1.380 654 × 10−23 J K−1, relative standard uncertainty 9.2 parts per million) with data measured earlier at low temperatures (21 K to 27 K, kLT = 1.380 657 × 10−23 J K−1, 15.9 parts per million) has yielded a value of k = 1.380 655 × 10−23 J K−1 with uncertainty of 7.9 parts per million.

A Modified Technique for Calibration of Current-Comparator-Based Capacitance Bridge and Its Verification

A modified technique for calibrating both the capacitance-ratio and dissipation-factor (DF) dials of a current-comparator-based high-voltage capacitance bridge has been developed at the Korea Research Institute of Standards and Science (KRISS). The capacitance-ratio and DF dials are calibrated in the ratio range from 1/1 to 1000/1 and in the DF range from 10 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> to 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> for both positive and negative polarities. From the calculated and measured values of the corresponding dial balanced readings, the errors in the capacitance-ratio- and DF-dial readings are derived. The relative uncertainty of the modified calibration technique is also obtained to be not more than 10 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> of unity for the ratio-dial calibration, whereas the relative uncertainty of the DF dials from 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> to 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> is not more than 0.4% of the dial indication except the dissipation lower than 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> for which the corresponding absolute uncertainty is 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> . The comparison results of the calibration performed at KRISS and the National Research Council of Canada show a good consistency with the measurement uncertainty.

High-Precision Capacitance Bridge for Dielectric-Constant Gas Thermometry

A high-resolution and high-precision autotransformer ratio capacitance bridge is described that has been built and tested at the Physikalisch-Technische Bundesanstalt for dielectric-constant gas thermometry. Its main component is a homemade high-precision 1 : 1 inductive voltage divider used in a autotransformer configuration. For balancing the bridge, adjustable in-phase and quadrature currents can be injected. A detailed uncertainty budget is presented for measuring small capacitance changes. Considering correlations between main terms in the mathematical model, it is shown that it is possible to measure capacitance changes of at most a few 0.1% with a relative standard uncertainty below one part per million, i.e., with an uncertainty relative to the capacitance value of order one part per billion.

$RLC$ Bridge Based on an Automated Synchronous Sampling System

An RLC bridge based on an automated synchronous sampling system has been developed using commercially available high-resolution analog-to-digital and digital-to-analog converters. This bridge allows the comparison of any kind of impedance standards in the four-terminal-pair configuration at frequencies between 50 Hz and 20 kHz within a range from 1 Ω to 100 kΩ. An automatic balance of the bridge is carried out using a downhill simplex algorithm. Consistency checks have been realized by comparing resistance, inductance, and capacitance standards at different frequencies. The consistency of the measured voltage ratio is better than 20 μV/V over the whole frequency range and even smaller than 5 μV/V around 1 kHz. Finally, the results of the calibration of a 10-nF capacitance standard have been compared to those obtained using a commercial high-accuracy capacitance bridge. The difference is smaller than the commercial bridge specifications over the whole frequency range.