CAD Simulation Research Articles

Learning complex nonlinear dynamics of a 3D translational parallel manipulator using neural network

This study investigates modeling the dynamics of a 3D translational parallel manipulator with closed chains using feedforward neural networks (FFNNs). The dataset exceeds 50,000 samples, incorporating experimental data collected from a robot prototype using MATLAB® real-time workshop and the National InstrumentsTM DAQ toolbox, as well as CAD simulation data from MSC ADAMS software. While achieving satisfactory mean squared error (MSE), some predictions did not fully capture the manipulator's dynamics, with small overfitting observed. A Deep Neural Network (DNN) was tested but faced overfitting and high computational costs, despite being trained on a subset of the dataset. This highlighted the limitations of DNNs for modeling such complicated parallel robots with closed chains and parallelograms. FFNNs were preferred for their simplicity and lower overfitting risk. L2 regularization and k-fold validation were applied to improve performance. Transfer learning (TL) was also employed, fine-tuning a new network with weights from pre-trained FFNNs using a smaller, unseen dataset. This approach significantly reduced MSE and completely eliminated overfitting, demonstrating the effectiveness of TL in refining model performance for forward and inverse dynamics. These findings suggest that FFNNs, combined with TL, L2 regularization, and k-fold validation, offer a robust method for accurately modeling complex robotic dynamics, enhancing control and optimization strategies for complicated robotic systems. Training for all networks was conducted within the MATLAB® environment.

Simulation and Comparative Study of Propagation Delay in Multi-Channel Quantum SWS-CMOS-Based Inverters Using II–VI Gate Insulator

This paper investigates the effect of lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator on the propagation delay of a 4-state quantum spatial wavefunction-switched (SWS)-CMOS-based inverters and SRAMs. The novelty is the smaller density of interface states which reduces the fluctuations in the various threshold voltages of the SWS-FETs and logic and memory devices using them. Two SWS-CMOS-based inverter models using SiO2 and lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator, are presented. Cadence simulations are used for comparing the single stage propagation delay of each inverter and their four-state logic transitions.

Reduction of Input Torque and Joint Reactions in High-Speed Mechanical Systems with Reciprocating Motion

In high-speed machinery, the variable inertia forces generated by reciprocating masses often introduce undesirable effects, such as a significant increase in the required input torque and joint forces. This paper addresses the challenge of reducing input torque and joint reaction forces in such mechanisms by employing two compression linear springs positioned between the slider and the frame. These springs counterbalance the slider's inertia force, thereby diminishing both the input torque and joint reactions. It is important to note that the elastic forces exerted by these springs remain internal to the mechanical system, preserving the balance of shaking forces and moments of the mechanism on the frame. The analytical framework developed in this study focuses on minimizing the root mean square and maximum values of the inertia force effects. A significant scientific achievement is attaining a given goal through an analytical solution. Notably, this is the first instance where this problem has been formulated and solved using explicit expressions. The effectiveness of the proposed technique is also demonstrated through CAD simulations, showing a substantial reduction in input torque and joint reactions.

Automated optimization of gating system through numerical simulation

Casting is a process for the production of complex shapes. Defects are unavoidable in any casting process. An efficient method of eliminating such defects can improve the process capability of the casting system. Computer simulation can save time, resources, and money in foundry trials, but it necessitates more human effort in terms of preparing the inputs and appropriately interpreting the results. In this work, a new method for evaluating and optimizing gating system design utilizing a simulation tool is proposed. It is possible to automatically modify the gating design with the help of CAD and casting simulation software from a given initial design and boundary conditions, and to check whether the design is effective to eliminate defects. Further this takes less human effort, making it more useful for industrial applications. The suggested methodology is demonstrated by autonomously optimizing the gating system for two industrial components and validated by producing actual castings made in sand molds.

A novel design of hysteretic comparator circuit towards GaN-based power IC

This paper proposes a hysteretic comparator circuit employing a positive feedback loop composed of all N-type devices towards GaN-based power integration circuits. By combining a source follower with comparator, the proposed hysteretic comparator circuit avoids the dependence on resistors, thus improving the integration density. To demonstrate the novelty, feasibility, and advantages of the proposed circuit, not only GaN-based but also Si-based circuits are investigated by simulations in ADS and Cadence, respectively. Simulated by the cadence virtuoso tool using TSMC 180 nm technology, it exhibits a layout area of 171.08 μm2, signal gain of 55.74 dB at low frequency, and maximum static power dissipation of 364.6 μW when the power supply is 3.3 V. In addition, it's verified that a signal gain of 55.11 dB at low frequency, transition time of 0.2 ns, and maximum static power dissipation of 2.064 W when the power supply is 12 V are achieved in GaN-based circuit according to simulation results in ADS. Consequently, compared with other mainstream or previously reported circuit in the same conditions, more ideal working performance and compact size are achieved by the proposed circuit, providing an advantageous strategy for monolithically integrating hysteretic comparator circuit in GaN-based power IC.

Geometric Modelling of a Family of 3-point Quaternary Subdivision Schemes Rζ

Computer-aided geometric design combines mathematical concepts and computing skills that smooth curves through subdivision schemes. Subdivision schemes perform smoothing by turning the control polygon into a limit curve under a refinement rule, a prime example of which is improving the signal-to-noise ratio in modern devices. Because of the importance and location of subdivision schemes, mathematicians use them in CAD, computer graphics and advanced simulation methods. In this research, a family of 3-point Quaternary approximating subdivision scheme $R_{\zeta}$ is presented with its properties and analysis, including necessary conditions for convergence, Laurent polynomial, degree of the generation and polynomial reproduction, continuity analysis, Hölder regularity, and limit stencils. The visual performance of the proposed scheme is also presented to highlight the importance of this research and to validate the scheme.

Design and Analysis of a High-Gain, Low-Noise, and Low-Power Analog Front End for Electrocardiogram Acquisition in 45 nm Technology Using gm/ID Method

In this work, an analog front-end (AFE) circuit for an electrocardiogram (ECG) detection system has been designed, implemented, and investigated in an industry-standard Cadence simulation framework using an advanced technology node of 45 nm. The AFE consists of an instrumentation amplifier, a Butterworth band-pass filter (with fifth-order low-pass and second-order high-pass sections), and a second-order notch filter—all are based on two-stage, Miller-compensated operational transconductance amplifiers (OTA). The OTAs have been designed employing the gm/ID methodology. Both the pre-layout and post-layout simulation are carried out. The layout consumes an area of 0.00628 mm2 without the resistors and capacitors. Analysis of various simulation results are carried out for the proposed AFE. The circuit demonstrates a post-layout bandwidth of 239 Hz, with a variable gain between 44 and 58 dB, a notch depth of −56.4 dB at 50.1 Hz, a total harmonic distortion (THD) of −59.65 dB (less than 1%), an input-referred noise spectral density of <34 μVrms/Hz at the pass-band, a dynamic range of 52.71 dB, and a total power consumption of 10.88 μW with a supply of ±0.6 V. Hence, the AFE exhibits the promise of high-quality signal acquisition capability required for portable ECG detection systems in modern healthcare.

A Comparative Analysis on the Optimization of Carbon Fibre Reinforced Polymer and Glass Fiber Reinforced Polymers as Wrapping Structures on Defected Piping System using Computational Simulation Approach

This study examined the application of carbon fiber reinforced polymer (CFRP) and glass fiber reinforced polymer (GFRP) as wrapping structures for defective pipe systems. The structural behavior and performance of the CFRP and GFRP wrapping structures were assessed using computational simulation methodologies. The goal of the study was to determine the best wrapping material for strengthening the integrity and reliability of piping systems with defects by comparing the results of the simulations. The study evaluated the capability of the proposed composite wrapping structure through CAD simulation. The simulations provided preliminary analysis and visually depicted deformations, aiding in the selection of an optimized lamination orientation for the composite wrapping structure in real-world applications. Eventually, this approach could have alleviated two primary failure modes that were common in composite repair: composite overloading due to excessive thickness and composite delamination from the substrate. The results of this study would have helped enhance effective and efficient pipe repair techniques in a variety of industries by offering useful insights into the selection and use of suitable wrapping structures for repairing defective pipes.

Beyond conventional: An integrated aerostructural optimization approach for innovative tailplane configurations

This research paper presents a comprehensive study focused on optimizing innovative tailplane configurations for transport jet aircraft. This study aims to enhance the aerodynamics of the aircraft's rear end by introducing a novel tail arrangement. The ultimate goal is to reduce the size of the horizontal empennage, which will have a positive impact on aircraft fuel efficiency. To fulfill its objectives, this work develops a systematic approach, integrating advanced methodologies such as the Design of Experiments and Response Surface Models for both aerodynamics and structural disciplines. By levering response surfaces methodology, the aerostructural optimization has been performed towards a size reduction of the horizontal tail. Results indicate a potential 9% reduction in the tailplane reference area, which could result in enhanced aerodynamic performance and weight saving. This target would only be achievable if the innovative design includes a Leading Edge Extension device to maintain the stability and handling characteristics of a conventional reference aircraft. The impact of the innovative optimized tail arrangement developed in this study at the aircraft level resulted in a 1% reduction in block fuel for a mission range of approximately 3,400 nautical miles for a 180-seat capacity jet aircraft (similar to A320neo). Furthermore, from an industrial perspective, this paper also demonstrates how an automated workflow assists with CAD modeling, mesh creation, simulation execution, and surrogate models to accelerate complex multidisciplinary optimization processes, thereby reducing the time and costs associated with the development of a new aircraft configuration.

Low power 7T SRAM cell optimization with 45nm Technology

A new low power SRAM cell introduced that promises improved performance by adding extra circuitry to a 6T-SRAM cell. This new design features a 7T(seven-transistors) cell at 45nm size CMOStechnology, aiming to enhance power efficiency,stability, overall performance compared to older designs for low power memory operations. By optimize the size and implementing a novel write circuitry scheme, new (seven transistor)7T SRAM cell fullfill a significant 45% reduction in power consumption during memory operations when compared to the traditional 6T SRAM-based design. Furthermore, through CADENCE simulations, it is shown that this 7T SRAM cell is highly resistant to process variations, highlighting its robustness and reliability in real-world applications.

Disain CAD Mekanisme Paralel Tiga Derajat Translasi Murni Dengan Rantai Kinematik Kombinasi Sambungan Revolut dan Prismatik


 
 
 
 In this study it was discussed kinematic design of a 3-RRRPP translational parallel mechanism. The design was carried out by using simulation performed using CAD software. Motion platform was analyzed based on screw and reciprocal screw theory. The evaluation mechanism performance was determined by introducing the stages of research in the form to determine mechanism parts such as base, links, and platform. The work was continued with the assembly process of each part. Furthermore, kinematic response represented by displacement of platform positions was figured out by a CAD simulation. Based on the results of the simulation, it was successfully designed the mechanism performing the translational motion of the Platform.
 
 
 
 
 

Neuronal axon action circuit based on memristor

Memristors have been increasingly valued by researchers nowadays, and using the unique properties of memristors to build brain-like large-scale integrated circuits has great potential in the development direction of high energy efficiency peak neural networks in the future. Simulating brain function has far-reaching implications for the development of computers. This paper describes a synaptic circuit based on a memristor and amplifier to simulate axonal mounds’ action potential. A Cadence simulator was used to simulate synaptic current flowing out from dendrites in axonal colliculus and the relationship between the membrane voltage and the output voltage with time. This circuit can greatly reduce the mismatch of the circuit and has good matching characteristics. It also reduces the area of the circuit.

On-chip ESD Protection Design Methodologies by CAD Simulation

Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

Design of integrated voltage multipliers using standard CMOS technologies

Results of the design of the integrated multistage voltage multipliers as components of supply modules for wireless passive microdevices are presented. Parameters of MOS transistors significant for the multipliers design and presented in three standard CMOS technologies, CM018G 180 nm, HCMOS8D 180 nm and C250G 250 nm, are considered. CAD Cadence simulation results have demonstrated that in the case of eight-stage multiplier implementation using CM018G technology minimum output voltage level requisite for microchip operation is achieved at input amplitude 250 mV and in the case of the similar device implementation using HCMOS8D technology - at 375 mV. Using sixteen-stages multiplier as example it is shown that voltage multiplication efficiency is from 20% to 54% for wide range of the input voltage, and the efficiency decreases only by 1-3% compared to eight-stage implementation. Proposed recommendations for the integrated voltage rectifiers-multipliers design could be applied at development of the passive supply units for microelectronic devices.

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm.

The purpose of this communication is to present the modeling of an Artificial Neural Network (ANN) for a differential Complementary Metal Oxide Semiconductor (CMOS) Low-Noise Amplifier (LNA) designed for wireless applications. For satellite transponder applications employing differential LNAs, various techniques, such as gain boosting, linearity improvement, and body bias, have been individually documented in the literature. The proposed LNA combines all three of these techniques differentially, aiming to achieve a high gain, a low noise figure, excellent linearity, and reduced power consumption. Under simulation conditions at 5 GHz using Cadence, the proposed LNA demonstrates a high gain (S21) of 29.5 dB and a low noise figure (NF) of 1.2 dB, with a reduced supply voltage of only 0.9 V. Additionally, it exhibits a reflection coefficient (S11) of less than -10 dB, a power dissipation (Pdc) of 19.3 mW, and a third-order input intercept point (IIP3) of 0.2 dBm. The performance results of the proposed LNA, combining all three techniques, outperform those of LNAs employing only two of the above techniques. The proposed LNA is modeled using PatternNet BR, and the simulation results closely align with the results of the developed ANN. In comparison to the Cadence simulation method, the proposed approach also offers accurate circuit solutions.

An Adjustable deadtime Control Circuit for LLC Resonance Control Circuit

This study introduces the principle of deadtime generation and gives a deadtime control circuit. The deadtime can be adjusted by the current generated by the MOS transistor in the subthreshold region to control the charging and discharging speed of the capacitor dynamically, and the whole circuit is simulated in the cadence simulation environment. The simulation results show that the designed circuit can manually adjust the dead time in the range of 70 ns-1, 650 ns depending on external settings, and greatly reduce the complexity of the circuit.

High-Performance Charge Pump Regulator with Integrated CMOS Voltage Sensing Control Circuit

This paper introduces a design for a charge pump DC-DC boost regulator with an integrated low-voltage control circuit. With a charge pump and feedback circuits implemented in 0.35 µm CMOS technology, the proposed DC-DC boost regulator offers an efficient device solution for low-power applications. The proposed design employs an error amplifier, oscillator, and comparator in the control circuit which is designed with a supply voltage of 1.8–3.5 V and 2 MHz frequency. Stability is obtained via a pole-zero compensation in the feedback circuit. The charge pump regulator with four pump stages and the whole regulator circuit are analyzed using the Cadence simulation tool. Measurements of the fabricated 0.35 µm CMOS regulator show that the transient time of the error amplifier is controlled within 1.0 µsec and the output voltage is accurately controlled from 7.8 V to 9.4 V with 27–38 mV ripple and 4.5 mA maximum current.

A Surrogate Modeling Approach for Frequency-Reconfigurable Antennas

A novel generalizable surrogate modeling approach is specifically developed for frequency reconfigurable antennas. The generalizable modeling processes is based on the rigorous mathematical derivation, including the solution of a non-linear overdetermined system, the optimization in the complex field, and the interpolation in multi-dimensional continuous space. As a post-processing method, the approach can convert the discrete data of CAD simulation to a surrogate model. Subsequently, a reconfigurable UWB antenna with a tunable notch-band is taken as an example to demonstrate that the surrogate modeling approach is feasible, effective, and precise. It also has the flexible ability to adapt to strict requirements and complicated scenarios. The proposed surrogate model is a good candidate for the interface standard between a reconfigurable antenna and signal processing part in a Cognitive Radio system.

Tuning the Legacy Survey of Space and Time (LSST) Observing Strategy for Solar System Science

The Vera C. Rubin Observatory is expected to start the Legacy Survey of Space and Time (LSST) in early to mid-2025. This multiband wide-field synoptic survey will transform our view of the solar system, with the discovery and monitoring of over five million small bodies. The final survey strategy chosen for LSST has direct implications on the discoverability and characterization of solar system minor planets and passing interstellar objects. Creating an inventory of the solar system is one of the four main LSST science drivers. The LSST observing cadence is a complex optimization problem that must balance the priorities and needs of all the key LSST science areas. To design the best LSST survey strategy, a series of operation simulations using the Rubin Observatory scheduler have been generated to explore the various options for tuning observing parameters and prioritizations. We explore the impact of the various simulated LSST observing strategies on studying the solar system’s small body reservoirs. We examine what are the best observing scenarios and review what are the important considerations for maximizing LSST solar system science. In general, most of the LSST cadence simulations produce ±5% or less variations in our chosen key metrics, but a subset of the simulations significantly hinder science returns with much larger losses in the discovery and light-curve metrics.

A novel approach for design energy efficient inexact reverse carry select adders for IoT applications

Low cost, low form factor and highly energy efficient VLSI design is the key for the success of internet of things (IoT) paradigm. Approximate computing is one of the major techniques used to achieve high performance and energy efficiency in error resistant computationally intense applications. Low power VLSI design is one of the important factors in the designing of new IoT system or reconstructing the existed IoT system. An inexact reverse carry select adder (IRCSLA) with back carry propagation is presented in this work. Three different types of adder implementations were presented in IRCSLA. The method of back carry propagation is applied to the design of both 16-bit ripple carry adder (RCA) & 16-bit carry select adders. These adders were designed in CADENCE schematic tool and simulations were done in Analog Design Environment with 45 nm CMOS technology. The design parameters such as delay and power of the three IRCSLA designs were compared with the existed back carry propagate full adders. IRCSLA-III gives 34.84% reduction in power and 56.91% improvement in delay compared to conventional CSLA adder and also improves the energy at the rate of 86.77% and 71.92% compared to the conventional RCA and a CSLA adder respectively.