Cache Coherence Control Research Articles

Cellular Automata Based Test Design for Coherence Verification in 3D Caches

To provide high vertical interconnection density between device tiers, Through Silicon Via (TSV) offers a promising solution in 3D caches. It reduces the length of global interconnection and ensures high speed cache memory access. Maintaining coherency of shared data in such caches is, however, very crucial and, therefore, demands that the reliability and accuracy of TSVs as well as the cache coherence controller (CC) are to be ensured. In the current work, we propose an elegant test solution for at-speed detection of stuck-at-faults in TSVs (offline test) as well as verification for the functioning of CC (online test). The proposed test structure is designed around the modular and cascadable structure of Cellular Automata (CA) to achieve a cost-effective realization of test and coherence verification in 3D caches with high degree of scalability. It ensures correct decisions in more than 71% cases even if the test hardware is subjected to single stuck-at-fault.

M7: Oracle's Next-Generation Sparc Processor

The Oracle Sparc M7 processor more than triples the throughput of the Sparc M6 processor, while increasing per-thread performance, power efficiency, and I/O bandwidth. M7 contains 32 8-thread, dual-issue, out-of-order Sparc cores. To minimize L3 cache hit latency, M7 features a partitioned L3 cache, with a novel on-chip network for communication between the cache partitions, coherence control, and memory. Memory bandwidth is more than 3 times that of the Oracle Sparc M6 processor. On-chip accelerators providing query filtering and decompression can provide another order of magnitude performance increase for these tasks. M7 keeps power consumption at a minimum through multiple power-saving techniques. M7 scales to 32-processor shared memory multiprocessing systems (SMPs). Coherent shared memory is also supported between SMPs in a cluster. Such a cluster is robust against both communication and SMP failure. Application data integrity guards against pointer-related software vulnerabilities without slowing the processor. Fine-grained memory migration supports concurrent garbage collection.

Design and Implementation of Metadata Cache Management Strategy for the Distributed File System

Caching strategies and the resulting cache coherence control technique have become the key techniques for the system development. Based on the study of the cache technology of the home and abroad distributed file systems, and combined with the design requirements and characteristics for our multi-user parallel file system Cappella, this paper proposes a new meta-data cache management strategy. And this strategy not only improves the performance of metadata services, reducing the user access latency, but also controls metadata cache consistency very well.

VBON: Toward efficient on-chip networks via hierarchical virtual bus

The need for scalable and efficient on-chip communication in future many-core architecture has resulted in the network-on-chip (NoC) design emerging as a popular solution. It is a common belief that packet-based NoC can provide high efficiency, high throughput, and low latency for future applications instead of conventional transaction-based bus. However, these superior features of NoCs are only applied to unicast (one-to-one) latency non-critical traffic. Their multi-hop feature and inefficient multicast (one-to-many) or broadcast (one-to-all) support have made it awkward when performing some kinds of communications including cache coherence protocol, global timing and control signals, and some latency critical communications. This paper presents VBON, a new architecture of incorporating buses into NoCs in order to take advantage of both NOCs and buses in a hierarchical way. The point-to-point links of conventional NoC designs can be used as bus transaction link dynamically for bus request. This can achieve low latency while sustain high throughput for both unicast and multicast communications at low cost. To reduce the latency of physical layout for the bus organization, the hierarchical redundant buses are used. Detailed network latency simulation and hardware characterization demonstrate that VBON can provide the ideal interconnect for a broad spectrum of unicast and multicast scenarios and achieve these benefits with inexpensive extensions to current NoC router.

A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips

Broadcast and synchronization techniques are used for cache coherence control in conventional larger scale snoop-based SMP systems. The penalty for synchronization is directly proportional to system size. Meanwhile, advances in LSI technology now enable placing a memory controller on a CPU die. The latency to access directly linked memory is drastically reduced by an on-die controller. Developing an enterprise server system with these CPUs allows us an opportunity to achieve higher performance. Though the penalty of synchronization is counted whenever a cache miss occurs, it is necessary to improve the coherence method to receive the full benefit of this effect. In this paper, we demonstrate a coherence directory organization that fits into DSM enterprise server systems. Originally, a directory-based method was adopted in high performance computing systems because of its huge scalability in comparison with snoop-based method. Though directory capacity miss and long directory access latency are the major problems of this method, the relaxed scalability requirement of enterprise servers is advantageous to us to solve these problems along with an advanced LSI technology. Our proposed directory solves both problems by implementing a full bit vector level map of the coherence directory on an LSI chip. Our experimental results validate that a system controlled by our proposed directory can surpass a snoop-based system in performance even without applying data localization optimization to an online transaction processing (OLTP) workload.

A New Semantic Cache Management Method in Mobile Databases

In mobile database systems, caching is a crucial way to improve the performance because a new query can be partially answered locally when the client is continuously moving around. Semantic caching has been paid much attention in traditional database systems. However, the methods of semantic cache management proposed in those systems are not suitable for mobile computing environment. Moreover, although many improved semantic caching strategies for mobile computing application have been proposed in recent years, few papers discussed semantic cache coherence control, which is very important in mobile computing environment. In this paper, we propose some new semantic cache model and management algorithms, which can significantly reduce the unnecessary uplink requests and downlink broadcasts compared to previous schemes. Simulation experiments are carried out to evaluate the proposed strategy.

A Multi-Protocol Cache Controller

Bus-based shared memory multiprocessors with per-processor caches use either invalidation or update protocols to maintain cache coherence. This paper suggests mixing protocols for different data objects within a single application, depending on whatever protocol is more efficient for an access pattern to a given object. The model of a twoprotocol cache coherence controller has been created in CSP-based Transim language. Each cache line is tagged not only with the state, but also with the protocol type. Two most frequent 4-state, write-back protocols are implemented: MESI (invalidation) and Dragon (update) protocol. The model will be used for experimental evaluation of the proposed controller.

Protocol considerations for a prefix-caching proxy for multimedia streams

The increasing popularity of multimedia streaming applications introduces new challenges in content distribution. Web-initiated multimedia streams typically experience high start-up delay, due to large protocol overheads and the poor delay, throughput, and loss properties of the Internet. Internet service providers can improve performance by caching the initial segment (the prefix) of popular streams at proxies near the requesting clients. The proxy can initiate transmission to the client while simultaneously requesting the remainder of the stream from the server. This paper analyzes the challenges of realizing a prefix-caching service in the context of the IETF's Real-Time Streaming Protocol (RTSP), a multimedia streaming protocol that derives from HTTP. We describe how to exploit existing RTSP features, such as the Range header, and how to avoid several round-trip delays by caching protocol information at the proxy. Based on our experiences, we propose extensions to RTSP that would ease the development of new multimedia proxy services. In addition, we discuss how caching the partial contents of multimedia streams introduces new challenges in cache coherency and feedback control. Then, we briefly present our preliminary implementation of prefix caching on a Linux-based PC, and describe how the proxy interoperates with the RealNetworks server and client.

Exploiting the benefits of multiple-path network in DSM systems: architectural alternatives and performance evaluation

Modern high-performance networks being used for scalable distributed shared-memory (DSM) systems support multiple paths to increase bandwidth and/or reduce contention. Such networks violate the constraint of pairwise in-order message delivery implicitly required by many existing directory-based cache coherence protocols. To solve this problem, two alternative strategies are currently used by computer architects. The first strategy, used in the SGI Origin series, is to employ an intelligent cache coherence protocol which detects and resolves all race conditions caused by out-of-order (OoO) events. The second strategy, used in the HAL Mercury series, is to use a sophisticated network interface (NI) which detects and remedies every OoO event before the messages are fed to the cache coherence controllers. Both strategies involve complicated hardware logic, either at the cache coherence controller level or at the NI level. In this paper, we propose a new strategy that uses block correlated FIFO channels. This new strategy detects all potential race conditions and prevents them from occurring. It allows the use of a simple cache coherence protocol and an inexpensive NI. We also present an efficient implementation of this strategy based on current technology. Detailed simulations are performed using benchmark applications to evaluate the performance of our new strategy. The results indicate that, compared to the existing strategies, our new strategy always provides either the best or close to the best overall performance. This study also provides valuable insights into the design trade-offs in incorporating modern networks into DSM systems.

Comparisons between mesh and hierarchical ring networks for shared-memory multiprocessors

Communication performance comparisons, in terms of message latency, between mesh and hierarchical ring interconnection networks for shared-memory multiprocessors are developed. Traffic in the networks is assumed to consist of the short, fixed-length messages needed for remote-memory read/write operations and cache coherency control. Square-mesh networks with bidirectional links and no end-around connections are compared to two- and three-level hierarchical rings. Wormhole routing is used in the meshes, with messages consisting of / flits, with each flit containing b bits. In the ring networks, each ring segment can contain a complete message of f × b bits. Meshes and three-level rings provide comparable delays for system sizes of up to 200 or 300 processor clusters. The delay comparisons are valid only for the lightly loaded traffic case in which contention and blocking are low. This is the situation in practical shared-memory multiprocessor systems with a low cache miss rate and a high physical locality of reference in the global address space.

Cluster architectures and S/390 Parallel Sysplex scalability

Supporting high transaction rates and high availability for on-line transaction processing and emerging applications requires systems consisting of multiple computing nodes. We outline various cluster architectures and describe the factors that motivate the S/390® Parallel Sysplex™ architecture and its resulting advantages. We quantify the scalability of the S/390 Parallel Sysplex and show that the transaction rate supported is close to linear as nodes are added to the system. The key facet of the S/390 Parallel Sysplex architecture is the coupling facility. The coupling facility provides for very efficient intertransaction concurrency control, buffer cache coherency control, and shared buffer management, among other functions, that lead to the excellent scalability achieved. It also provides for effective dynamic load balancing, high data buffer hit ratios, and load balancing after a failure.