VBON: Toward efficient on-chip networks via hierarchical virtual bus

Abstract

The need for scalable and efficient on-chip communication in future many-core architecture has resulted in the network-on-chip (NoC) design emerging as a popular solution. It is a common belief that packet-based NoC can provide high efficiency, high throughput, and low latency for future applications instead of conventional transaction-based bus. However, these superior features of NoCs are only applied to unicast (one-to-one) latency non-critical traffic. Their multi-hop feature and inefficient multicast (one-to-many) or broadcast (one-to-all) support have made it awkward when performing some kinds of communications including cache coherence protocol, global timing and control signals, and some latency critical communications. This paper presents VBON, a new architecture of incorporating buses into NoCs in order to take advantage of both NOCs and buses in a hierarchical way. The point-to-point links of conventional NoC designs can be used as bus transaction link dynamically for bus request. This can achieve low latency while sustain high throughput for both unicast and multicast communications at low cost. To reduce the latency of physical layout for the bus organization, the hierarchical redundant buses are used. Detailed network latency simulation and hardware characterization demonstrate that VBON can provide the ideal interconnect for a broad spectrum of unicast and multicast scenarios and achieve these benefits with inexpensive extensions to current NoC router.