Abstract
The Oracle Sparc M7 processor more than triples the throughput of the Sparc M6 processor, while increasing per-thread performance, power efficiency, and I/O bandwidth. M7 contains 32 8-thread, dual-issue, out-of-order Sparc cores. To minimize L3 cache hit latency, M7 features a partitioned L3 cache, with a novel on-chip network for communication between the cache partitions, coherence control, and memory. Memory bandwidth is more than 3 times that of the Oracle Sparc M6 processor. On-chip accelerators providing query filtering and decompression can provide another order of magnitude performance increase for these tasks. M7 keeps power consumption at a minimum through multiple power-saving techniques. M7 scales to 32-processor shared memory multiprocessing systems (SMPs). Coherent shared memory is also supported between SMPs in a cluster. Such a cluster is robust against both communication and SMP failure. Application data integrity guards against pointer-related software vulnerabilities without slowing the processor. Fine-grained memory migration supports concurrent garbage collection.
Published Version
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