On the Cache Behavior of SPLASH-2 Benchmarks on ARM and ALPHA Processors in Gem5 Full System Simulator

Abstract

Today cache size and hierarchy level of caches play an important role in improving computer performance. By using full system simulations of gem5, the variation in memory bandwidth, system bus throughput, L1 and L2 cache size misses are measured by running SPLASH-2 Benchmarks on ARM and ALPHA Processors. In this work we calculate cache misses, memory bandwidth and system bus throughput by running SPLASH2 benchmarks on gem5 Full System Mode. Our results show that L1 cache misses decrease as L1 cache size is varied from 16KB to 64KB. L1 cache misses are independent of L2 cache size after the program data resides in L2 cache. The memory bandwidth and system bus throughput decreases as L1 and L2 cache size increases.