Cache Access Research Articles

Real-time map rendering and interaction: a stylized hierarchical symbol model

ABSTRACT Digital maps, serving as pivotal instruments in the realm of geographic information services, adeptly encapsulate spatial data through refined graphics and symbols. Widely used across various domains such as smart devices, in-vehicle navigation systems, unmanned aerial vehicles (UAV), electronic gaming, and virtual reality, these maps face the ongoing challenge of delivering real-time, precise, and efficacious map rendering and interaction experiences. In response to this challenge, this study introduces a Stylized Hierarchical Symbol structure (SHS) and a Geographic Feature Color-weighted Rendering technique (GFCR). The approach is further complemented by incorporating Adaptive Hierarchy-Weighted caching (AHie), Catalan Number-based Caching access (CatNCa), and Grid-based Dynamic caching loading (GriD). Experimental results demonstrate the method's effectiveness in addressing issues related to timeliness, accuracy, and logical correctness in mobile map environments, enhancing the real-time interaction experience of mobile digital maps. Notably, this method imposes modest hardware and storage requirements, making it applicable to a wide range of scenarios including natural resource planning, intricate road landscapes, route navigation challenges, and emerging fields such as autonomous driving, virtual reality, and the metaverse.

Designing a Deep Neural Network engine for LLC block reuse prediction to mitigate Soft Error in Multicore

Last level cache (LLC), a major contender of chip area, exhibits the highest sensitivity to soft error. Block reuse prediction is used to exhibit selective protection of LLC blocks. However, traditional reuse predictors fail to accurately understand the cache access pattern. This work explores machine learning for block reuse prediction that realizes the features that affect reuse likelihood and therefore, better predicts the reusable blocks. To off-load the reuse calculation from the processing cores, a dedicated reuse predictor engine is designed. This engine implements a deep neural network with unsupervised learning and calculates reuse probabilities offline without affecting the execution path. Priority blocks with high reuse likelihood are protected using replications in shared LLC. Low priority blocks are invalidated to reduce their vulnerable time. A replication aware replacement policy is also developed to protect the replicated/reserved blocks from eviction. The scheme is evaluated in Multi2Sim 5.0 simulation framework with SPEC-CPU benchmarks considering bulk-CMOS, FDSOI and FinFET technologies. The results indicate 41.29% and 43.14% reductions in miss rate, 92.29% and 89.56% reductions in vulnerability, 5.73% and 6.31% increase in write-back rate, 17.55% and 16.27% reductions in average memory access time, 2.17% and 1.54% increase in Instructions-per-cycle (IPC) and 1.31% and 0.77% reductions in normalized-execution-cycle over the baseline (with SECDED protection) for integer and floating point benchmarks respectively. Marginal increase in power consumption by 1.33% and dynamic energy by 0.43% are observed at 6.32% area overhead.

RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks

Cache timing channel attacks exploit the inherent properties of cache memories: hit and miss time along with the shared nature of the cache to leak secret information. The side channel and covert channel are the two well-known cache timing channel attacks. In this article, we propose Restricted Static Pseudo-Partitioning (RSPP), an effective partition-based mitigation mechanism that restricts the cache access of only the adversaries involved in the attack. It has an insignificant impact of only 1% in performance, as the benign processes have access to the full cache and restrictions are limited only to the suspicious processes and cache sets. It can be implemented with a maximum storage overhead of 1.45% of the total Last-Level Cache (LLC) size. This article presents three variations of the proposed attack mitigation mechanism: RSPP, simplified-RSPP (S-RSPP) and corewise-RSPP (C-RSPP) with different hardware overheads. A full system simulator is used for evaluating the performance impact of RSPP. A detailed experimental analysis with different LLC and attack parameters is also discussed. RSPP is also compared with the existing defense mechanisms effective against cross-core covert channel attacks.

LAG-based schedulability analysis for preemptive global EDF scheduling with dynamic cache allocation

In recent years, the maturation of modern multicore processor technology and its increasing adoption in critical industrial domains have posed significant challenges for real-time systems, primarily due to contention for shared cache resources and the resulting uncertainty. To address this issue, contemporary processors employ cache partitioning techniques, enhancing temporal predictability by isolating cache access among processor cores. However, this isolation technique may lead to real-time tasks missing their deadlines due to an insufficient number of cache partitions. Consequently, this paper investigates the schedulability of preemptive global Earliest Deadline First (EDF) real-time scheduling algorithms that support dynamic cache allocation. We propose an innovative LAG-based schedulability analysis method for these algorithms and present a utilization-based schedulability condition that reduces analysis time complexity while improving analysis accuracy. Building upon this foundation, and incorporating task characteristics into our analysis, this paper further introduces an optimization technique aimed at minimizing the pessimism inherent in the schedulability test. Lastly, the performance and efficiency of the proposed schedulability determination method are validated through simulation experiments with randomly generated tasks.

Multi-User PIR with Cyclic Wraparound Multi-Access Caches.

We consider the problem of multi-access cache-aided multi-user Private Information Retrieval (MACAMuPIR) with cyclic wraparound cache access. In MACAMuPIR, several files are replicated across multiple servers. There are multiple users and multiple cache nodes. When the network is not congested, servers fill these cache nodes with the content of the files. During peak network traffic, each user accesses several cache nodes. Every user wants to retrieve one file from the servers but does not want the servers to know their demands. This paper proposes a private retrieval scheme for MACAMuPIR and characterizes the transmission cost for multi-access systems with cyclic wraparound cache access. We formalize privacy and correctness constraints and analyze transmission costs. The scheme outperforms the previously known dedicated cache setup, offering efficient and private retrieval. Results demonstrate the effectiveness of the multi-access approach. Our research contributes an efficient, privacy-preserving solution for multi-user PIR, advancing secure data retrieval from distributed servers.

Novel Edge Caching Approach Based on Multi-Agent Deep Reinforcement Learning for Internet of Vehicles

Along with the development of Internet of Vehicles (IoV) and wireless technology, the usage of applications that require low latency, such as autonomous driving and intelligent navigation, is increasing rapidly, and the demand for content is increasing greatly. This paper proposes an edge caching approach for the IoV based on multi-agent deep reinforcement learning (ECSMADRL) so as to resolve the problem of excessive response delay due to the large increase of data traffic in the IoV. The approach jointly considers content distribution and caching in dynamic environments. In other words, each moving vehicle in the IoV can be seen as an agent, and it can make decisions about content caching and content access adaptively according to the changing environment to minimize the delay in the process of content distribution. It is proved by experiments that compared with other methods, the proposed edge caching (EC) approach has better performance in reducing content distribution delay, improving content hit rate and success rate.

Extending the classical side-channel analysis framework to access-driven cache attacks

Cryptographic devices are vulnerable to side-channel attacks, which have attracted broad attention in the hardware security field. The side-channel analysis framework proposed at Eurocrypt 2009 has been widely adopted in academia, containing key elements such as points of interest, leakage models, distinguishers, and security metrics. This classical framework, however, is not intuitively compatible with recent micro-architectural attacks such as cache attacks, therefore, few attempts have been made to link them. In this paper, we extend the classical side-channel analysis framework and migrate its ideas to access-driven cache attacks. We find that cache attacks can be effectively incorporated into this framework. Specifically, we propose a leakage model called cache access pattern vector according to the cache timing leakage characteristics. Furthermore, we propose data preprocessing schemes such as noise reduction, dimensionality reduction, and vector expansion to implement efficient attacks. Subsequently, we proposed seven distinguishers in three categories: difference of means-based analysis, vector distance-based analysis, and mutual information-based analysis. Moreover, we attacked the last round of the AES fast software implementation algorithm based on the Chipyard platform. According to the experimental results, all proposed methods can successfully extract the key, and five of them are comparable to mainstream cache analysis in attack efficiency. Finally, we evaluate the five efficient distinguishers under three different cache micro-architectures using guessing entropy. Based on the experimental environment of this paper, vector distance-based distinguishers have the best attack efficiency, and the difference of mean-based analysis has the worst. Surprisingly, the most general mutual information-based attacks can achieve excellent medium results in a few attack rounds without the help of static analysis tools. Meanwhile, the experimental results demonstrate that cache micro-architecture directly impacts the attack effect, in which the smaller cache line size benefits the attacks, while the random replacement policy increases the noise and difficulty of the attacks.

Architecting the Autocuckoo Filter to Defend Against Cross-Core Cache Attacks

Cross-core cache timing side-channel attacks, which observe cache access behavior of victims running on different physical cores to infer sensitive information, have become a significant threat. Although the attacks are covert, they cause the attacked cachelines to frequently migrate among cache hierarchies, rendering abnormal traffic. Based on this observation, the proposed scheme PiPoMonitor records cache-memory access traffic and prefetch suspicious lines under attack to interfere with adversaries’ probes. In pursuit of security and performance, PiPoMonitor exploits a Cuckoo filter as the recording structure and introduces two features to it: 1) autonomic deletion and 2) relocation accelerating. The former exponentially increases the uncertainty of record eviction against reverse engineering attacks, while the latter leverages a pipelined architecture to alleviate the impact of intensive filter queries on the memory critical path. PiPoMonitor is not only able to effectively mitigate cross-core cache attacks and defeat sophisticated defense-aware attackers but also induces a negligible performance penalty and acceptable hardware overhead.

A method of defense against cache timing attack in non-volatile memory

Attackers of modern computer architecture found that cache access latency difference between cache hit and cache miss is a point where secure data are overlooked. To prevent such data leakage, cache partitioning technique is utilized for defenders via cache hit isolation. Although this approach is effective in increasing resistance against cache timing attack, it is not suitable for emerging memory system, which is based on non-volatile memories, because it overlooks the weaknesses of the write operations. This paper proposes a secure-aware partitioning guide architecture to improve performance and write endurance by removing the necessity of cache flushing. During changing cache partitioning status, the write counts are considered for the new status and no cache lines are evicted in the proposal. As a result, the lifetime is extended by 1.77 times and the penalty of cache flushing is saved by 7.8%.

Energy and Latency Efficient Caching in Mobile Edge Networks: Survey, Solutions, and Challenges

Future wireless networks provide research challenges with many fold increase of smart devices and the exponential growth in mobile data traffic. The advent of highly computational and real-time applications cause huge expansion in traffic volume. The emerging need to bring data closer to users and minimizing the traffic off the macrocell base station introduces the use of caches at the edge of the networks. Storing most popular files at the edge of mobile edge networks (MENs) in user terminals (UTs) and small base stations caches is a promising approach to the challenges that face data-rich wireless networks. Caching at the mobile UT allows to obtain requested contents directly from its nearby UTs caches through the device-to-device (D2D) communication. In this survey article, solutions for mobile edge computing and caching challenges in terms of energy and latency are presented. Caching in MENs and comparisons between different caching techniques in MENs are presented. An illustration of the research in cache development for wireless networks that apply intelligent and learning techniques in a specific domain in their design is presented. We summarize the challenges that face the design of caching system in MENs. Finally, some future research directions are discussed for the development of cache placement and cache access and delivery in MENs.

Efficient thread‐to‐core mapping alternatives for application‐level redundant multithreading

SummaryRedundant multithreading (RMT) is an effective thread‐level replication method to improve the reliability requirements of applications. Although it significantly improves the robustness of applications, it comes with additional performance overhead since the redundant threads might share the same core resources. In our previous study [Efficient selective replication of critical code regions for SDC mitigation leveraging redundant multithreading.J Supercomput2021;77:14130‐14160], we presented an efficient software‐level RMT approach, where we execute the most critical code regions with three threads to correct errors. In this study, we focus on further improving the performance of our software‐level RMT method by presenting a set of different thread‐to‐core mapping alternatives. We provide different static mapping methods, which require preliminary information about the applications, such as execution time, instruction‐per‐cycle (IPC), or cache usage patterns, and a set of dynamic mapping methods, which map threads to cores dynamically at runtime without requiring any additional information. The dynamic mapping methods decide which threads are mapped to which cores at each scheduling point based on the IPC, cache miss rate, or cache access values of each thread as well as each core. Experimental results show that the dynamic mapping method, which maps threads to cores based on IPC values, outperforms all other static and dynamic methods. It also outperforms our baseline model, where the operating system handles the thread‐to‐core mappings by 8%, 7%, and 20% based on average speedup, harmonic speedup, and mean slowdown metrics.

A Novel Strategic Caching and Availability Optimization for Wireless Unmanned Aerial Vehicle Communication Networks

The rowing complexity in the 5G technology has created a necessity for UAV(Unmanned Aerial Vehicle)-assisted cellular networks as base stations. This is helpful for a wider coverage with higher transmission rates as it addresses three critical issues, i.e. location, performance and bandwidth. Besides, the integration of caching into conventional UAV infrastructure has received significant attentions since it can bring contents and memory storage closer to a mobile device. In a dynamic resource caching for wireless mobile networks, drone’s settings contain important options for supporting a wide variety of applications and services, including the network access fee, quality of service (QoS) , number of cached contents, cache access fee and beaconing duration. A theoretic model based on game theory is developed to study the effect of competition among UAVs that have caching and sharing revenue model. Note that an optimal usage of UAV capabilities would thus lead to a cost-effective strategy for energy consumption and QoS requirements.

CoDi$: Randomized Caches Through Confusion and Diffusion

Cloud providers are increasingly exposed to malicious actors through transient attacks, such as Spectre and Meltdown. The cache hierarchy is the main target to build the required side-channels to leak data. Randomized caches can be employed to provide security but often rely on cryptographic primitives to deter side-channel attacks. These increase the access latency and deteriorates the system performance. This paper shows that randomized caches do not have to increase the cache access latency, and that their security does not have to rely on a cryptographic hash function or block-cipher. Herein, CoDi$ is proposed, a randomized last level cache that achieves security by tying the local and global states. Security is achieved through a higher miss energy consumption and occupied area, instead of penalizing performance. CoDi$ is able to evict any cached address by allowing addresses to be displaced in two levels of freedom, through hopscotch (local state) and cuckoo hashing (global state), without increasing the hit latency. Through these displacements, paths can be built to the eviction address. The security of CoDi$ relies on the hardness to control all possible displacement paths when a miss occurs, which requires control over the local and global states of the cache simultaneously. Confusion is generated when evicting an address, as there are many possible cache states that could result from this eviction. Also, for each executed eviction, multiple addresses in the cache are non-deterministically displaced, providing diffusion. Moreover, experimental analysis for a 48-bit secure CoDi$, using SPEC, NPB, and Polybench benchmarks, shows improvements in the number of instructions per cycle and up to 5% in misses, when compared to two state-of-the-art randomized caches.

BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network

Nowadays, system-on-chip (SoC) integrates more processing cores and IPs with network-on-chip (NoC) for satisfying today's demands, including low power consumption and high performance, without affecting the elasticity and scalability. When the on-chip processing elements (PEs) are increased, burst traffic will be generated from memory and cache accesses. As a result, the packet transmission latency is increased, reducing the system's speed performance. This paper proposes a new hybrid Base delta Neighbourhood Indexing Sequence (BΔ-NIS) based compression method for compressing the network traffic. The previous solutions for data compression often contain incompressible packets for certain data patterns. The proposed method uses Neighbourhood Indexing Sequence (NIS) algorithm to determine the optimal codeword for uncompressible chunks of delta compression approach using zeros and ones based traversals. Because of the dynamic nature of BΔ-NIS, it is highly effective and compresses all chunks in the packets efficiently. Moreover, the concept of dynamic header flit extension is introduced in the proposed compression method, which provide unlimited scalability. The proposed BΔ-NIS algorithm is robust to packet losses and leads to significant power saving. The simulation results show that the proposed BΔ-NIS reduces the hardware overhead and overtakes the existing data compression techniques by attaining a mean compression ratio of 0.73. In addition, BΔ-NIS accomplishes 51% latency reduction compared to the baseline router (without any compression). It also minimizes the power consumption of the de/compression modules by 70.14% and 20.8% as compared to the NoΔ and FlitZip respectively.

Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory

Magnetic tunnel junction (MTJ)-based memory devices have larger switching delay and energy consumption, compared to cache or dynamic random access memory. In order to broaden the applications of the magnetoresistive random access memory, reducing the switching time and energy consumption of the MTJ is required. Here, a novel lateral double MTJ with an orthogonal polarizer is proposed. The proposed device consists of three ferromagnetic regions: the first pinned region (PR1) with perpendicular magnetic anisotropy (PMA), a free region (FR) with PMA, and the second pinned region (PR2) with in-plane magnetic anisotropy (IMA). PR1 and PR2 are placed on top of the oxide barrier, which separates them from the FR, comprising a lateral double MTJ structure. The current pulse through PR2 helps to perturb the magnetization of the FR. Since the angle between PR2 and FR is 90°, the initial torque increases significantly, decreasing switching delay by 4.02 times and energy-delay product by 7.23 times. It is also shown, that the area of the access transistor can be reduced by approximately 10%, while maintaining the same energy-delay product and reducing gate RC delay.

Detection of Cache Pollution Attack Based on Federated Learning in Ultra-Dense Network

Ultra-Dense Network (UDN) as one of the key technologies of 5G aims to increase the capacity per area of the current 4G network by 1,000-fold through the deployment of dense Small Base Stations (SBSs). To reduce the traffic on backhaul links, Content-Centric Networking (CCN) as a promising network architecture has been applied to UDN recently. However, its in-network caching mechanism is subject to Cache Pollution Attack (CPA), where attackers aim to occupy limited caching space with unpopular contents. Existing studies focusing on the static networks cannot be directly used in dynamic UDN scenarios. In this paper, we propose a detection and defense scheme of CPA based on federated learning, where CPA is determined by the cooperation of multiple SBSs. First, each SBS can build or join a cluster based on the metrics of distance similarity and load similarity. Then, each cluster head as the working node trains the local classifier to detect CPA based on the statistics within the cluster. The macro base station aggregates all the local models to generate an improved global classifier for all the SBSs. In our scheme, federated learning as a special case of distributed machine learning allows each cluster head to independently train the local data even when it is non-i.i.d. or unbalanced. Simulation results show that our scheme outperforms in terms of detection ratio, cache hit ratio, access delay, and false alarm ratio compared with other state-of-the-art schemes.

LOSC: A locality-optimized subgraph construction scheme for out-of-core graph processing

Big data applications increasingly rely on the analysis of large graphs. In recent years, a number of out-of-core graph processing systems have been proposed to process graphs with billions of edges on just one commodity computer, by efficiently using the secondary storage (e.g., hard disk, SSD). Unfortunately, these graph processing systems continue to suffer from poor performance, despite of many solutions proposed to address the disk I/O bottleneck problem, a commonly recognized root cause. However, our experimental results show that another root cause of the poor performance is the subgraph construction phase of graph processing, which induces a large number of random memory accesses that substantially weaken cache access locality and thus greatly degrade the performance. In this paper, we propose an efficient out-of-core graph processing system, LOSC, to substantially reduce the overheads of subgraph construction. LOSC proposes a locality-optimized subgraph construction scheme that significantly improves the in-memory data access locality of the subgraph construction phase. Furthermore, LOSC adopts a compact edge storage format and a lightweight replication of vertices to reduce I/O traffic and improve computation efficiency. Extensive evaluation results show that LOSC is respectively 9.4× and 5.1× faster than GraphChi and GridGraph, two representative out-of-core systems. In addition, LOSC outperforms other state-of-art out-of-core graph processing systems including FlashGraph, GraphZ, G-Store and NXGraph. For example, LOSC can be up to 6.9× faster than FlashGraph.

Understanding I/O Direct Cache Access Performance for End Host Networking

Direct Cache Access (DCA) enables a network interface card (NIC) to load and store data directly on the processor cache, as conventional Direct Memory Access (DMA) is no longer suitable as the bridge between NIC and CPU in the era of 100 Gigabit Ethernet. As numerous I/O devices and cores compete for scarce cache resources, making the most of DCA for networking applications with varied objectives and constraints is a challenge, especially given the increasing complexity of modern cache hardware and I/O stacks. In this paper, we reverse engineer details of one commercial implementation of DCA, Intel's Data Direct I/O (DDIO), to explicate the importance of hardware-level investigation into DCA. Based on the learned knowledge of DCA and network I/O stacks, we (1) develop an analytical framework to predict the effectiveness of DCA (i.e., its hit rate) under certain hardware specifications, system configurations, and application properties; (2) measure penalties of the ineffective use of DCA (i.e., its miss penalty) to characterize its benefits; and (3) show that our reverse engineering, measurement, and model contribute to a deeper understanding of DCA, which in turn helps diagnose, optimize, and design end-host networking.

An End-to-End Automatic Cache Replacement Policy Using Deep Reinforcement Learning

In the past few decades, much research has been conducted on the design of cache replacement policies. Prior work frequently relies on manually-engineered heuristics to capture the most common cache access patterns, or predict the reuse distance and try to identify the blocks that are either cache-friendly or cache-averse. Researchers are now applying recent advances in machine learning to guide cache replacement policy, augmenting or replacing traditional heuristics and data structures. However, most existing approaches depend on the certain environment which restricted their application, e.g, most of the approaches only consider the on-chip cache consisting of program counters (PCs). Moreover, those approaches with attractive hit rates are usually unable to deal with modern irregular workloads, due to the limited feature used. In contrast, we propose a pervasive cache replacement framework to automatically learn the relationship between the probability distribution of different replacement policies and workload distribution by using deep reinforcement learning. We train an end-to-end cache replacement policy only on the past requested address through two simple and stable cache replacement policies. Furthermore, the overall framework can be easily plugged into any scenario that requires cache. Our simulation results on 8 production storage traces run against 3 different cache configurations confirm that the proposed cache replacement policy is effective and outperforms several state-of-the-art approaches.

Security Model for Randomization-based Protected Caches

Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention.This vulnerability has been shown to lead to several microarchitectural attacks. As a promising solution, recent work proposes Randomization-based Protected Caches (RPCs). RPCs randomize cache addresses, changing keys periodically so as to avoid long-term leakage. Unfortunately, recent attacks have called the security of state-of-the-art RPCs into question.In this work, we tackle the problem of formally defining and analyzing the security properties of RPCs. We first give security definitions against access-based cache sidechannel attacks that capture security against known attacks such as Prime+Probe and Evict+Probe. Then, using these definitions, we obtain results that allow to guarantee security by adequately choosing the rekeying period, the key generation algorithm and the cache randomizer, thus providing security proofs for RPCs under certain assumptions.