BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network

Abstract

Nowadays, system-on-chip (SoC) integrates more processing cores and IPs with network-on-chip (NoC) for satisfying today's demands, including low power consumption and high performance, without affecting the elasticity and scalability. When the on-chip processing elements (PEs) are increased, burst traffic will be generated from memory and cache accesses. As a result, the packet transmission latency is increased, reducing the system's speed performance. This paper proposes a new hybrid Base delta Neighbourhood Indexing Sequence (BΔ-NIS) based compression method for compressing the network traffic. The previous solutions for data compression often contain incompressible packets for certain data patterns. The proposed method uses Neighbourhood Indexing Sequence (NIS) algorithm to determine the optimal codeword for uncompressible chunks of delta compression approach using zeros and ones based traversals. Because of the dynamic nature of BΔ-NIS, it is highly effective and compresses all chunks in the packets efficiently. Moreover, the concept of dynamic header flit extension is introduced in the proposed compression method, which provide unlimited scalability. The proposed BΔ-NIS algorithm is robust to packet losses and leads to significant power saving. The simulation results show that the proposed BΔ-NIS reduces the hardware overhead and overtakes the existing data compression techniques by attaining a mean compression ratio of 0.73. In addition, BΔ-NIS accomplishes 51% latency reduction compared to the baseline router (without any compression). It also minimizes the power consumption of the de/compression modules by 70.14% and 20.8% as compared to the NoΔ and FlitZip respectively.