A new traffic compression method for end-to-end memory accesses in 3D chip-multiprocessors

Abstract

As the number of cores increases, power consumption becomes the main concern in Network on Chip (NoC) and Last Level Cache (LLC). In on-chip interconnection networks, bursty-based traffics between components such as cache and memory banks have a big contribution of total traffic in NoC-based many-core systems. In this context, these types of traffics have an impressive impact on NoC energy consumption. Moreover, non-volatile memories (NVMs) are among the newest solutions to replace SRAM in LLC. However, NVMs suffer the limited number of write operations and long write operation latency and high energy. In this paper, we present a novel compression method to reduce the data traffic between processor cores and non-volatile memories in a 3D system. It can also reduce the number of write operations in a LLC to reduce the total energy consumption. In this paper, we propose a novel compression method called Zero-Duplicate Compression (ZDC) to compress network traffic and to improve energy efficiency in NVMs as a LLC. Our experiments show that our proposed compression method provides significant compression ratio with trivial hardware overhead in compared to two other state-of-the-art compression methods.