C-mode Scanning Acoustic Microscopy Research Articles

(Invited) Al-Al Waferbonding Process Development for Heterogeneous Integration

3D heterogeneous integration provides the possibility to combine dissimilar semiconductor technologies and add new components to obtain a higher performance and increase the functionality. Aligned Wafer level bonding, where the chips are vertically interconnected is known as one of the key technologies needed for 3D integration. Here, Aluminum to aluminum bonding is very attractive due to its easy compatibility to complementary metal-oxide-semiconductor (CMOS) processes. Furthermore Al-Al bonding provides not only the mechanical attachment between different wafers but also enables a good electrical and thermal conductivity. One of the main challenges for Al-Al thermocompression bonding is the formation of aluminum oxide which inhibits uniform and reliable Al-Al bonding at low temperatures with minimum bond forces. To overcome this limitation, this work presents a surface activated bonding process carried out in an EVG® ComBond® 200 mm automated high vacuum wafer bonding system. Here, the surface oxide is first removed with an argon plasma treatment. Without breaking vacuum to avoid a reoxidation, the wafers are optically aligned to each other and then bonded by applying force and temperature.This paper shows an integration concept for patterned 200 mm Al-Al bonded wafers and focusses on different factors influencing the quality of the Al-Al bonding. The bond quality is evaluated with various characterization methods. For electrical characterization single contacts with sizes down to 10 µm x 10 µm are analyzed. To characterize the bond interface C-mode scanning acoustic microscopy (C-SAM), scanning electron microscopy (SEM) and transmission electron microscopy (TEM) are used. To calculate the bond strength, shear force measurements are carried out. The alignment accuracy is evaluated with an infrared microscope measuring the overlay of specific alignment marks at different dice across the wafer.A great factor influencing the bonding quality are the process parameters during the actual bonding process. Here, we vary the duration of the argon plasma activation from 1.5 to 5 min. Additionally, the impact of the bonding temperature in the range of 200 to 300 °C and the influence of the bonding force between 20 and 60 kN is investigated. Furthermore the bonding time is varied from 15 to 60 min. The best results with contact resistances in the mΩ-Range and a bonding yield >95% are achieved for wafers bonded for 1 h at 300 °C with 60 kN and an activation time of 5 min.Besides the bonding parameters, also the wafer fabrication prior to the bonding process has a significant influence on the Al-Al bond quality. In this context, the local and global topography of the wafers play an important role. An improved wafer flatness increases the contact area during bonding and can thus contribute to a better bonding result. In order to reduce the surface roughness of the Al bonding pads, we vary the parameters for the aluminum deposition and analyze the impact of different adhesion/barrier layers below the aluminum bonding film. The paper shows that also the tungsten plugs under the Al bonding pads affect their topography and thus the bond quality. In addition, we modify an etch-mask influencing the condition of the Al bonding pads and directly correlate it to the bonding yield and electrical resistance. Moreover, the impact of the wafer bow on the bond strength is studied.Even the processes that follow the Al-Al bonding can still negatively affect the final result. After bonding a backside grinding process is used, which causes silicon dust on the wafer surface and requires an additional cleaning step. This study shows the effect of an ultrasonic clean on the measured bond strength.In summary we present a surface activated, low temperature Al-Al bonding process of patterned 200 mm wafers with a high bonding yield, low contact resistances and an alignment accuracy close to 1 µm. Our work presents an integration concept for Al-Al bonded wafers and highlights different factors that influence the bonding result.

Experimental assessment of barely visible impact damage carbon fiber reinforced epoxy composite using ultrasound method

Background Carbon fiber reinforced epoxy (CFRP) is susceptible to impact damage which could resulted in reduction of the mechanical properties. This paper studies the architecture of barely visible impact damage (BVID) to comprehend the extent of damage on quasi-isotropic CFRP laminates of varying thickness (i.e. 16, 24 and 32-ply laminates of 3, 4 and 5 mm respectively). Methods Quasi-static indentation is chosen to produce BVID on CFRP laminates, followed by using non-destruction evaluation method, namely conventional contact-type ultrasonic testing (UT) and C-mode scanning acoustic microscopy (C-SAM) method. Results The findings revealed (1) the size and shapes of the BVID on CFRP laminates, (2) no damage was found at the center of the impact point, and (3) the bridging between the point of impact to the outer damaged diameter due to the consequence of diverse orientation of carbon fiber strips which exhibit excellent mechanical properties before structural failure. Conclusions The results concluded that the UT and C-SAM method can identify both the pristine region and the internal damaged structures in CFRP laminates.

Experimental assessment of barely visible impact damage carbon fibre reinforced epoxy composite using ultrasound method

Background: Carbon fibre reinforced epoxy (CFRP) is susceptible to impact damage which could resulted in reduction of the mechanical properties. This paper studies the architecture of barely visible impact damage (BVID) to comprehend the extent of damage on quasi-isotropic CFRP laminates of varying thickness (i.e. 16, 24 and 32-ply laminates of 3, 4 and 5 mm respectively). Methods: Quasi-static indentation is chosen to produce BVID on CFRP laminates, followed by using non-destruction evaluation method, namely conventional contact-type ultrasonic testing (UT) and C-mode scanning acoustic microscopy (C-SAM) method. Results: The findings revealed (1) the size and shapes of the BVID on CFRP laminates, (2) no damage found at the point of damage, and (3) the bridging between the point of impact to the outer damaged diameter due to the consequence of diverse orientation of carbon fibre strips which exhibit excellent mechanical properties before structural failure. Conclusions: The results concluded that the UT and C-SAM method can identify both the pristine region and the internal damaged structures in CFRP laminates.

Modeling of flip-chip underfill delamination and cracking with five input manufacturing variables

The chip corner geometry and the mismatch of the coefficient of thermal expansion cause a local stress concentration in the underfill near the chip corner area. Delamination at the chip-underfill interface and cracks in the underfill often originate from the chip corner and might develop throughout the assembly. This paper presents a modeling approach that allows the estimation of the initial moment of delamination, the growth of delamination and the cracking profiles in flip-chip packages. The reliability model in this work includes five input variables: kerf width, dicing type, laser outrigger presence, sealband material and sealband shape. Thirteen test cells of flip-chip experimental samples were first prepared according to these input variables and were subjected to deep thermal cycling (DTC). C-mode scanning acoustic microscopy (C-SAM), infrared microscopy (IR) and cross-sectioning were used to estimate the underfill failure moments, delamination areas and crack profiles as a reference for subsequent numerical modeling. An artificial neural network (ANN) model was trained to estimate the number of cycles to delamination for cells in the test dataset. The predicted numbers of cycles for all 6 cells in the test dataset were consistent with experimental observations. A finite element model was built to describe the growth of delamination. When the model reached the same delamination area as measured by C-SAM, the difference between the predicted number of cycles and the C-SAM inspection moment were smaller than the inspection interval (250 cycles) for 5 out of 6 cells in validation; the delamination growth model was thus consistent with the experimental observations. The extended finite element method (XFEM) was used to model the underfill cracks without predefined paths. One of the cracks propagated along the diagonal direction, and the other two cracks were along the edges of the die. The directions of edge cracks were in good agreement with the experimental observations, with an error of less than 2.5° for the edge cracks. Overall, with five input manufacturing variables, this modeling approach is able to provide reasonable predictions of the number of cycles to chip-underfill delamination initiation, area of delamination and underfill crack paths in flip-chip packages.

Low Temperature Hydrophilic SiC Wafer Level Direct Bonding for Ultrahigh-Voltage Device Applications.

SiC direct bonding using O2 plasma activation is investigated in this work. SiC substrate and n− SiC epitaxy growth layer are activated with an optimized duration of 60s and power of the oxygen ion beam source at 20 W. After O2 plasma activation, both the SiC substrate and n− SiC epitaxy growth layer present a sufficient hydrophilic surface for bonding. The two 4-inch wafers are prebonded at room temperature followed by an annealing process in an atmospheric N2 ambient for 3 h at 300 °C. The scanning results obtained by C-mode scanning acoustic microscopy (C-SAM) shows a high bonding uniformity. The bonding strength of 1473 mJ/m2 is achieved. The bonding mechanisms are investigated through interface analysis by transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDX). Oxygen is found between the two interfaces, which indicates Si–O and C–O are formed at the bonding interface. However, a C-rich area is also detected at the bonding interface, which reveals the formation of C-C bonds in the activated SiC surface layer. These results show the potential of low cost and efficient surface activation method for SiC direct bonding for ultrahigh-voltage devices applications.

Analysis of the effect of structural defects on the fatigue strength of RFSSW joints using C‐scan scanning acoustic microscopy and SEM

AbstractSolid‐state refill friction stir spot welding (RFSSW) technology offers significant benefits in the fabrication of aluminium structures in the transport and aerospace industries. In this paper, the joining of 1.6‐mm‐thick Alclad 7075‐T6 aluminium alloy sheets is investigated. High‐cycle fatigue strength tests of single‐lap welded joints were carried out on an Instron E10000 testing machine with a limited number of cycles equal to 2 × 106. The welding of overlap fatigue specimens was conducted using an RPS100 spot welder by Harms & Wende GmbH & Co KG. C‐mode scanning acoustic microscopy (C‐SAM) and scanning electron microscopy (SEM) were utilised to evaluate the joint quality and characterise the microstructure. The paper discusses the effect of the maximum load force and defects (voids, hook, kissing bond, bonding ligament, etc) associated with the material flow in the weld on the failure mechanism. Insufficient plasticisation of sheet material and mixing of the material in the weld area are crucial defects that influence the number of destructive cycles. The weld defects in the joint structure are a source of a decrease in the fatigue life compared with the fatigue life of defect‐free welds. It was also found that RFSSW joint defects can be effectively detected by the nondestructive C‐SAM method.

Interlayer Dielectric Bonding for 300mm Wafers

Nowadays, the large-scale integration process using 300 mm Si wafers is the main stream in the manufacturing process for commercial devices. Furthermore, wafer-level hybrid bonding technology is the key issue for the 3D high-density integration devices. For hybrid interface with metal and interlayer dielectric, both materials are required for the reliable connection. In particular, the interlayer dielectric layers have various materials and conditions in order to apply for each device such as SiO2 by thermal oxide, tetraethyl orthosilicate, or silane; SiN, quartz, and so on. The direct bonding technology has been investigated for several decades, and several bonding methods are applicable for the wafer-level bonding. In particular, surface activated bonding (SAB) method with Ar fast atom bombardment (Ar-FAB) or plasma activated bonding (PAB) are the essential technology for wafer-level hybrid bonding. In this research, several interlayer dielectric substrates were prepared on 300 mm Si wafers; SiO2 by thermal oxide, tetraethyl orthosilicate, or silane; SiCN, and the several process parameters including pre-process for the bonding has been investigated and evaluated their bonding quality. In this abstract paper, partial results are described: Thermal oxide SiO2 (100 nm thickness) wafers were bonded by PAB process. Bonded wafers were evaluated by C-mode scanning acoustic microscopy (C-SAM) for voids confirmation and blade strength measurement. (Fig.1) Also, the bonded interface has been observed by the cross-sectional transmission electron microscopy (TEM) observation. (Fig.2) At the interface of among the bonded wafers, there is only one void due to a particle intervening interface during bonding process. The peripheral unbonded area seems to correspond to the touched area by the transferring process. Furthermore, the cross-sectional TEM image shows the stable bonded interface without voids. In the conference program, we would like to present the each optimized bonding process for each ILD material cyclopaedically. Figure 1

A new hermetic sealing method for ceramic package using nanosilver sintering technology

High reliable packaging materials are needed for electronics when they work at harsh environments. Among which, the nanosilver material has been widely studied and applied in power electronics due to its low processing temperature and high reliability. This paper investigates the bonding properties of nanosilver sintered hermetic cavity. There are two kinds of lids used in this study, including copper lid and silicon lid. The X-ray and C-Mode Scanning Acoustic Microscopy (C-SAM) results revealed that delamination tended to happen in Cu lid sintered cavity as the recovery of deformed Cu lid was hindered by sintered dense Ag layer. However, no delamination or cracks were found in Si lid sintered cavity. Finite element analysis (FEA) method was used to investigate the effects of lid materials on the stress distribution of lid. The results indicated that the Cu lid sintered cavity showed a much higher stress than the Si lid sintered cavity under the sintering parameters of 250°C and 10MPa. There is no obvious change in the stress distribution areas on Cu lid with the increasing of pressures from 5 to 30MPa. However, the distribution area of stress on Si lid expanded obviously only when the sintering pressure increased to 30MPa. With the increase of sintering pressures from 5 to 30MPa, the maximum stresses on Cu lid are almost the same, while increasing trend was found on Si lid.

Surface pretreated low-temperature aluminum\u2013aluminum wafer bonding

Aluminum–aluminum wafer bonding is becoming increasingly important in the production of CMOS microelectromechanical systems. So far, successful bonding has required extreme processing temperatures of 450 °C or more, because the chemically highly stable oxide layer acts as a diffusion barrier between the two aluminum metallization layers. By using the ComBond® system, in which a surface treatment and subsequent wafer bonding are both performed in a high vacuum cluster, for the first time successful Al–Al wafer bonding was possible at a temperature of 150 °C. The bonded interfaces were characterized using C-mode scanning acoustic microscopy and transmission electron microscopy, and featured areas of oxide-free, atomic contact.

Wafer-Scale Dies-Transfer Bonding Technology for Hybrid III/V-on-Silicon Photonic Integrated Circuit Application

In this paper, we review a variety of hybrid III/V-on-silicon integration platforms with focus on the optical coupling between III/V and silicon waveguides. Numerical simulations with regard to the coupling efficiency are conducted for various mode-overlapped and adiabatic-coupled structures for future design guideline. As a highlight, we show a novel wafer-scale dies-transfer bonding technology that features the merits of high bonding efficiency and process scalability for potential manufacturability of hybrid III/V-on-silicon photonic integrated circuit. Exemplary demonstration of up to 100 dies bonding to an 8-in processed silicon wafer is shown with ∼80% bonding yield, according to the C-mode scanning acoustic microscope characterization. As a proof-of-concept, hybrid silicon mode-locked lasers using the bonded wafer are demonstrated.

Thin Layer Transfer Using Room Temperature Wafer-Level Bonding Process

Direct wafer bonding has already been demonstrated as an efficient solution to create a linkage between two different surfaces. One of the main limitation is the temperature required to stabilize the bonding interface and the strength. For example, to completely stabilize a Si/Si bonding realized at room pressure, an annealing step done at 1000°C or above is required. In the past, alternative low temperature processes, using plasma activation of the surfaces before contact between them, were developed for SiO2 to Si and SiO2 to SiO2 bondings, lowering the annealing temperature at 300°C and enabling enough bond strength for many applications [1]. Another possible option to realize a room temperature Si/Si bonding is to use a covalent bonding process [2]. The EVG®580 ComBond® was developed with this aim by bringing the wafers in contact in an ultra-high vacuum environment, after activation in vacuum of both surfaces in the ComBond® Activation Module (CAM®) [3,4]. This paper aims to present observations made after the transfer of a thin layer using this novel direct covalent Si/Si bonding process. The bonding process was realized in an EVG®580 ComBond® equipment installed at CEA-Leti. At first, the equipment and the process window were qualified in terms of metal and particle contaminations. Measurements of particles with a threshold at 90nm were performed, and detection of metals contamination demonstrated that the whole bonding process was metal free with a specification of 1.1010 at/cm² for all metallic elements. The activation process, performed in the CAM®, was also characterized, especially in terms of etching rate, roughness and amorphous thickness measurement done by ellipsometry. Then, an appropriate bonding process, demonstrating a high bond strength (>5 J/m²) was developed for Si/Si 200 mm wafers. Using this process, the bonding of a SOI (Si 100nm - SiO2 200nm) with a Si wafer was performed, in order to transfer the SOI Si layer onto a new substrate and to characterize both the bonding and the transfer qualities. In this study, bonding quality is assessed using C-mode Scanning Acoustic Microscopy (C-SAM) which is performed just after bonding, as shown on figure 1a, where no defects have been observed. More generally, in order to control the bonding and the layer transfer processes, particle contamination measurements deserve to be performed on the SOI surface before bonding and after layer transfer. It may be done using a SurfScan equipment (SP2) from KLA-Tencor with a detection threshold value of 90 nm for instance. If large particles are deposited at the bonding interface during activation process, they lead to non-transferred areas (i.e. holes) visible after layer transfer. As we can see from figure 1b, no holes or additional defects are detected after such a layer transfer. Thus, perfect quality of transferred layers on 200 mm full wafers is shown. Additional measurements may be performed in order to characterize the bonding interface. Ellipsometry is used to measure the thickness of the amorphous area created during the surface activation step. TEM observations, made before and after recrystallization, allow to confirm the thickness of the amorphous layer, as well as to study the temperature at which the Si interface is fully recrystallized. Finally, SIMS measurements is used to characterize the other species than Si which could be found at the bonding interface like oxygen, carbon, and metallic elements for instance. The successful transfer of a thin Si layer onto a new substrate shown in this work demonstrates that such a bonding process would deserve to be applied to many other thin layer transfer techniques. REFERENCE [1] T. Plach, K. Hingerl, S. Tollabimazraehno, G. Hesser, V. Dragoi and M. Wimplinger, J. Appl. Phys., 113, 094905 (2013) [2] H. Takagi, K. Kikuchi, R. Maeda, T. R. Chung and T. Suga, "Surface Activated Bonding of Silicon Wafers at Room Temperature", Appl. Phys. Lett. Vol. 68, No.16 (1996), pp. 2222-2224. [3] C. Flötgen, N. Razek, V. Dragoi, M. Wimplinger, “Novel Surface Preparation Methods for Covalent and Conductive Bonded Interfaces Fabrication”, ECS Trans. 64(5), The Electrochemical Society, pp. 103-110, 2014 [4] C. Flötgen, N. Razek, V. Dragoi, “Functional Interfaces Fabrication Through Room Temperature Wafer-Level Bonding”, Proc. of WaferBond Conference, 2015, pp. 55-56 EVG®580 is a Trade Mark of EVGroup ComBond® is a Trade Mark of EVGroup CAM® is a Trade Mark of EVGroup Figure 1

Low-Temperature Aluminum-Aluminum Wafer Bonding

Thermo-compression wafer bonding is a key technology for the wafer-level production of hermetically sealed cavities, which are essential for the functioning of many microelectromechanical systems (MEMS). Aluminum, with its low material price, high thermal and electrical conductivities and its complementary metal oxide semiconductor (CMOS) compatibility, is a promising candidate for the fabrication of CMOS-MEMS, in which the sensor/actuator part is bonded to the electrical circuit. The chemically highly stable oxide layer on the Al surface cannot be removed by conventional methods. It acts as a thin diffusion barrier layer between the two aluminum metallization layers, and therefore inhibits successful low temperature Al-Al wafer bonding. So far, effective Al-Al wafer bonding has required extreme processing temperatures of >300°C and high contact pressures. Typically, 450°C-550°C led to bonded Al-Al wafers with incorporated alumina (Al2O2) precipitates and reasonable bonding quality. By using the EVG®580 ComBond®system, in which the aluminum oxide is first removed physically, followed by bonding of the two metallization layers – both performed in a high vacuum cluster – for the first time successful Al-Al wafer bonding was feasible at a temperature of 100°C. In the present work, the microstructure of structured and unstructured aluminum films on silicon substrates was characterized by atomic force microscopy (AFM) and transmission electron microscopy (TEM). C-mode scanning acoustic microscopy (C-SAM), TEM and energy dispersive x-ray spectroscopy (EDXS) interface studies of Al-Al wafer pairs bonded with this novel method revealed oxide-free, atomic contact and grain growth across the original interface. Further, the bond strength was characterized based on dicing yield and pull tests.

Low-Temperature Aluminum-Aluminum Wafer Bonding

Aluminum-aluminum thermo-compression wafer bonding is becoming increasingly important in the production of microelectromechanical systems (MEMS) devices. As the chemically highly stable aluminum oxide layer acts as a diffusion barrier between the two aluminum metallization layers, up to now the process has required bonding temperatures of 300°C or more. By using the EVG®580 ComBond® system, in which a surface treatment and subsequent wafer bonding are both performed in a high vacuum cluster, for the first time successful Al-Al wafer bonding was possible at a temperature of 100°C. The bonded interfaces of blank Al wafers and Al wafers with patterned frames were characterized using C-mode scanning acoustic microscopy (C-SAM) and transmission electron microscopy (TEM) as well as dicing yield and pull tests representative for the bonding strength. The investigations revealed areas of oxide-free, atomic contact at the Al-Al bonded interface.

Detection and formation mechanism of micro-defects in ultrafine pitch Cu—Cu direct bonding*Project supported by the National Natural Science Foundation of China (Grant No. 61274111) and the National Basic Research Program of China (Grant No. 2015CB057205).

In this paper, Cu–Cu interconnects with ultrafine pad pitches of 6 μm, 8 μm, and 15 μm are implemented on the 12 inch wafers by a direct bonding process. Defects are not found by traditional non-destructive (NDT) c-mode scanning acoustic microscopy (c-SAM). However, cross sectional observation of bonding interfaces reveals that micro-defects such as micro seams are located at SiO2 bonding interfaces. In order to examine the micro-defects in the ultra-fine pitch direct bonding process by the NDT technology, a novel “defect-enlarged approach” is proposed. The bonded dies are first annealed in an N2 oven at 300 °C for a few hours and then cooled quickly in air. The c-SAM scanning images show large defects at the place where nothing can be detected by c-SAM before this treatment. Cross sectional observation of the bonding interfaces indicates that these defects consist of large size micro seams at the SiO2 bonding interface, especially near Cu pads with an ultrafine pitch of 6 μm. However, these large defects disappear after several hours at room temperature, observed by c-SAM. It is inferred that the disappearance of these defects inspected by the “defect-enlarged approach” results from the combination of intrinsic micro seams and “weak” bonds in the silicon oxide layer. Then the underlying physical mechanism of these micro-defects is proposed, which is influenced by Cu pad surface topology and bonding models.

Stencil Printing of Underfill for Flip Chips on Organic-Panel and Si-Wafer Substrates

A high-throughput method of post assembly underfill is presented in this paper. Emphasis is placed on the proposal of a specially designed stencil to print the underfill material for flip chips on large organic-panel and Si-wafer assemblies. After printing, the organic-panel or Si-wafer assemblies are placed on a hot plate for the underfill to totally fill the space between the chips, solder joints, and substrates by capillary action, and then cured. The cured assemblies are characterized by the C-mode scanning acoustic microscopy, X-ray, shear test, cross sectioning, and scanning electron microscopy. The effects of the viscosity, thermal enhancement, and multiple prints of underfills are examined. It is found that stencil printing of underfill for flip chips on organic-panel and Si-wafer substrates is a very high-throughput, simple, and low-cost process.

Evaluation of CSAM for Plastic-Encapsulated Microcircuit Dormant Storage Testing

Rigorous environmental testing, with C-mode scanning acoustic microscopy (CSAM) inspection, was imposed on a sizeable set of exemplary commercial off-the-shelf plastic encapsulated microcircuits (PEMs) to demonstrate their suitability for dormant storage over extensive periods of time. After qualification testing of over 4800 samples of 39 standard manufacturer (mfr) part numbers from 18 world-class mfrs in 25 widely different PEM package types, indications of product discrepancies by CSAM were largely discounted based upon device reliability testing, including physical cross sectioning.

A Case Study of the Reliability of Copper Bond Wires In Plastic Encapsulated Integrated Circuits

Sixteen plastic encapsulated integrated circuits were initially received as part of a root-cause failure investigation, twelve of which contained copper bond wires and the other four containing gold bond wires. It was reported that eight of the integrated circuits had failed in the field with intermittent or complete malfunction of the components. Electrical testing confirmed the reported failure and found temperature sensitive, intermittent open circuits on various pins coinciding with the sample history. C-Mode scanning acoustic microscopy (CSAM) was performed on the devices, with each sample exhibiting varying degrees of delamination between the lead-frame and the plastic encapsulant. The backside of the package was polished into the underside of the lead-frame to preclude the introduction of any contamination due to chemical decapsulation. This allowed the mechanical removal of the leads from the package and inspection of the stitch bonds. Scanning electron microscope (SEM) inspection revealed that the copper stitch bonds had corroded to some extent (ranging from mild corrosion to complete consumption of the stitch bond) in each of the examined bonds, whereas the gold stitch bonds were unaffected. Overall inspection of the leads identified chlorine contamination along the delaminated interface.

Optimization of Low Temperature Cu-Cu Wafer Bonding Using Advanced Analytical Methods

Metal thermo-compression wafer bonding is a promising candidate for three-dimensional integration of Integrated Circuits (3D ICs). 3D ICs are very interesting as they allow for higher performance due to shorter interconnect paths fabricated in a wafer-level integration approach, even for wafers processed in different technologies. For example, Complementary Metal Oxide Semiconductors (CMOS) and Micro- Electro- Mechanical Systems (MEMS) may be integrated this way. Due to its high electrical and thermal conductivity, low cost, and current availability in numerous IC fabrication facilities Cu is a very attractive bonding material for 3D integration. During the past decade processes were developed for Cu-Cu thermo-compression bonding using about 1 h at 400°C under high contact pressure. A substantial bonding temperature reduction is required in order to optimize post-bond wafer-to-wafer alignment accuracy, to minimize thermo-mechanical stresses, to prevent device degradation (as it is the case for Dynamic Random Access Memories - DRAMs), and to increase the throughput of the bonding process.The aim of this work was to study the physical mechanisms of Cu-Cu bonding, develop a deep knowledge of the effects of these mechanisms, and then apply this knowledge to optimize the bonding process for low temperatures. This was achieved by preparing 150 mm silicon sample wafers by two alternative methods (Cu sputtering and electroplating) either with or without Chemical Mechanical Polishing (CMP), running a set of experiments covering combinations of wet chemical ex-situ and dry in-situ oxide reducing pre-treatments and then evaluating the results using analytical techniques, such as Atomic Force Microscopy (AFM), Electron Back- Scatter Diffraction (EBSD), Transmission Electron Microscopy (TEM), C-mode Scanning Acoustic Microscopy (C-SAM), several elemental analysis techniques and a qualitative version of the Maszara crack test. Here the used wet chemistry was diluted citric acid (1wt%) and the reducing gas was forming gas (96% Ar + 4% H2). Subsequent to the wafer bonding process, the post-bond annealing was performed in order to increase the bond strength while keeping the retention time in the wafer bonding system as short as possible.It was determined that for successful low temperature Cu-Cu thermo-compression wafer bonding the following classes of variables have to be considered (i) the contact of the two Cu surfaces, even at atomic scale, (ii) the cleanliness of the Cu surfaces, (iii) the diffusion properties of the two Cu layers and (iv) process conditions. In this paper the measured experimental results are compared with current knowledge and theory. In addition, key variables for establishing a successful bonding process were discussed. Using the fundamental information learned in these experiments it was possible to perform Cu-Cu thermo-compression wafer bonding at and below 200°C (see Figure 1); even room temperature direct bonding is achievable.

Thermal Fatigue Characteristics of Die Attach Materials for Packaged High-Brightness LEDs

With the increase of driving current and power density, the thermal fatigue characteristics of die attach materials have become an important issue impacting the long-term reliability of high-brightness light-emitting diodes (HB LEDs). In this paper, an accelerated power cycling method is used to predict the thermal fatigue life of die attach materials for packaged HB LEDs. The thermal fatigue life of Au80Sn20 eutectic and silver paste is investigated at driving currents of 650, 675, and 700 mA. Changes in the thermal resistance of die attach materials are monitored by the noninvasive structure function method based on the measurement of transient temperature response curves through power cycling experiments. Results of C-mode scanning acoustic microscopy and cross-sectional scanning electron microscopy indicate that delamination is the main failure mechanism of the die attach materials under thermal fatigue stress. Furthermore, the thermal fatigue life of die attach materials can be derived from the relationship between lifetime and temperature difference according to the Coffin-Manson relationship. The results suggest that Au80Sn20 eutectic possesses a longer thermal fatigue life than silver paste at the same temperature difference of thermal fatigue stress.

Effect of Prebonding Anneal on the Microstructure Evolution and Cu–Cu Diffusion Bonding Quality for Three-Dimensional Integration

Electroplated copper (Cu) films are often annealed during back-end processes to stabilize grain growth in order to improve their electrical properties. The effect of prebonding anneal and hence the effective initial grain size of the Cu films on the final bond quality are studied using a 300-nm-thick Cu film that was deposited on a 200-mm silicon (Si) wafer and bonded at 300°C. As compared with the control wafer pair with a prebonding anneal at 300°C for 1 h in N2, the wafer pair without a prebonding anneal showed greater improvement in void density based on c-mode scanning acoustic microscopy (c-SAM). Dicing yield and shear strength were also enhanced when a prebonding anneal was not applied. This improvement is due to substantial grain growth of smaller Cu grains during the bonding process, which leads to a stronger Cu–Cu bond. Our work has identified a Cu–Cu bonding process with a lower total thermal budget, which is seen as a favorable option for future three-dimensional (3D) integrated circuit (IC) technology.