Burst-mode Clock And Data Recovery Research Articles

Experimental Demonstration of a Photonic Frame Based Packet-Switched Optical Network for Data Centers

This article reports on the design and the experimental realization of packet-switched optical network (PSON) for a data center network. In PSON, an optical interconnect consists of a combination of a fast tunable laser (FTL), an arrayed waveguide grating router, and a burst mode receiver (BMR). The conventional FTL transmitters can only accommodate short fixed-size photonic frame (PF) of tens of microseconds rather than variable-size PF due to the short-term wavelength stability. By using the FTL with a thermal compensation method, the PSON can support variable-size PFs with extended size to minimize the switching overhead in the optical switch domain. Our PSON system can achieve up to 96% throughput of 10 GbE service as the end-to-end optical switching time is reduced to 1.94 $\mu$ s that requires only 3 $\mu$ s guard-time in a 45 $\mu$ s time-slot. Total switching time includes wavelength conversion time of FTL, response time of BMR and burst mode-clock and data recovery (BM-CDR). Our PSON will achieve near non-blocking scheduling by use of a centralized scheduler running a grant-aware (GA) scheduling algorithm, which can be further improved to be non-blocking scheduling with a novel algorithm called C-RRP. The C-RRP scheduling algorithm is designed especially for the non-uniform distribution. Simulation results show that C-RRP improves the throughput and latency performance in hot-spot conditions.

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS

A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\bf mm}^{2}$</tex></formula> and 60 mW.

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI pp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps rms . The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm 2 only. It dissipates 12.4 mW from 1 V supply.

10-Gb/s BM-CDR Circuit With Synchronous Data Output for Optical Networks

This letter presents a 10-Gb/s burst-mode clock and data recovery (BM-CDR) circuit based on an analog phase-picking method. The experiment demonstrates that the proposed BM-CDR circuit is able to align the BM data to a local clock with a phase alignment accuracy of ±π/4, a 25-ns latency and zero bit loss. The circuit further resamples the aligned data using the local clock for jitter reduction. The experiment shows error-free operation of the BM-CDR circuit for burst-mode data packets with various phase delays.

20-GSample/s (10 GHz $\times$ 2 Clocks) Burst-Mode CDR Based on Injection Locking and Space Sampling for Multiaccess Networks

In this paper, we demonstrate a novel 20-GSample/s burst-mode clock and data recovery (BM-CDR) technique for optical multiaccess networks. The BM-CDR incorporates an injection-locking method for clock recovery and a clock phase aligner employing space sampling with two multiphase clocks at 10 GHz and a phase-picking algorithm for automatic clock phase acquisition. The design provides low latency and fast response without requiring a reset signal from the network layer. The BM-CDR achieves a bit error rate <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> while featuring instantaneous (0-bit) phase acquisition for any phase step (±2π rad) between successive bursts. We also compare the data with probabilistic theoretical predictions to validate the experimental results.

10.3-Gb/s Burst-Mode 3R Receiver Incorporating Full AGC Optical Receiver and 82.5-GS/s Over-Sampling CDR for 10G-EPON Systems

In this letter, we developed, for the first time, 10.3-Gb/s burst-mode 3R receiver incorporating a full automatic gain control optical receiver and 82.5-GS/s over-sampling clock and data recovery (CDR) for 10G-EPON. Burst-mode preamplifier, limiting amplifier, and CDR were newly fabricated on 0.13-?m SiGe bipolar complementary metal-oxide-semiconductor process to completely meet the IEEE802.3av 10G-EPON standards. The 10.3-Gb/s burst-mode 3R receiver successfully achieves the burst receiver sensitivity of -30.1 dBm (at bit error rate (BER) =1 ×10-3) and the dynamic rage more than 24.1 dB (at BER=1 ×10-3) with the assistance of FEC RS(255, 223).

Burst-Mode CDR Performance in Long-Reach High-Split Passive Optical Networks

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper compares two burst-mode clock and data recovery (BM-CDR) techniques suitable for bursty upstream data transmission, namely a gated voltage controlled oscillator (GVCO) and an oversampling clock phase alignment (CPA). Numeric models were deduced with timing jitter and duty cycle distortion (DCD) present in the received data. The performance of the two techniques are analyzed and compared especially in an optically amplified long-reach high-split PON (LR-PON) system. It is shown that an oversampling CPA exhibits a large DCD tolerance and better jitter rejection than a GVCO without line coding, resulting in high network efficiency while keeping fast bit synchronisation. This makes the oversampling CPA technique the best option for the proposed network. </para>

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect levelvarying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-μm CMOS process. It successfully operates at a data rate of 10.3125Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2ns with AC-coupling without a reset signal. The IC also demonstrates 1001bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation

In this letter, a 1.25-Gb/s 0.18-μm CMOS half-rate burstmode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4×1.4 mm2, and power consumption is 32 mW under a 1.8-V supply voltage. key words: burst-mode CDR, clock recovery, phase-locked loop, realigned oscillation

A multibitrate burst-mode CDR circuit with bit-rate discrimination function from 52 to 1244 Mb/s

We fabricate and assess a clock and data recovery (CDR) circuit with a bit-rate discrimination (BRD) function that can receive burst-mode signals containing packets of different bit rates. The clock recovery circuit in the CDR circuit consists of gated oscillators (GOs) for handling the burst-mode signals, whose bit rates vary with each packet. Moreover, we improve the performance of the clock recovery circuit based on GOs against the bit rate unevenness around each bit rate. By combining an agile clock recovery circuit and a digital BRD circuit, the CDR circuit can handle multiplexed bit rates. Tests show that the circuit offers excellent performance for the multiplexed bit rates of nonreturn-to-zero 52, 155, 622, and 1244 Mb/s.