Thickness Of Buried Oxide Layer Research Articles

Back Gate Bias Influence on BESOI ISFET Sensitivity

The application of Field Effect Transistors (FETs) to sensors and biosensors allows a mass production, low cost, small size, fast response and, also, the possibility of integrating the device and conditioning signal circuit in the same integrated circuit (IC). The Ion Sensitive Field Effect Transistor (ISFET), invented in 1970 by Piet Bergveld (1), is a device similar to the conventional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), except that the metal gate is replaced by an inert electrode/pseudo electrode and a sample solution, in order to expose the gate oxide layer to ions present in the solution. The solution charges change the electrical potential in the gate oxide surface and, consequently, the device threshold voltage changes as a function of the ion concentration in the sample solution, being used as a pH sensor. Thus, the ISFET is a very promising device to Point-of-Care (POC) monitoring, such as COVID-19 control (2) and for continuous in vivo monitoring ion activity in biological processes (3)-(6).The BESOI (Back Enhanced Silicon-On-Insulator) MOSFET is a device patented in 2015 by João Antonio Martino and Ricardo Cardoso Rangel (7). This device is easy to fabricate and low cost. In the last years, the research using this device as a sensor/biosensor has been done (8)-(14). This paper presents, for the first time, the BESOI MOSFET working as an Ion Sensitive Field Effect Transistor (ISFET): the BESOI ISFET. Therefore, the focus of this work is to study the device electrical behavior influenced for pH standard solutions.The BESOI ISFET was fabricated at Integrated System Laboratory (LSI) from University of Sao Paulo (USP), Brazil. It is a planar device made on a SOI (Silicon-On-Insulator) wafer with three conventional photolithography steps, in an analogous way to previous work (15) and one more photolithography step to create microchannel and microreservoirs with SU-8 (16) layer to contain the sample solution. The wafer has no doping process (there is only the natural wafer doping of 1015 cm-3). The silicon channel layer and the gate oxide (SiO2) thicknesses are 10 nm and 25 nm, respectively. The buried oxide layer thickness is 200 nm. The drain and source contacts are fabricated with nickel and the contact pads using aluminum. The Figure 1 presents the final device layout and the Figure 2 shows the device schematic drawn.Differently from a conventional ISFET, where the drain current flows at the front interface, in the BESOI ISFET the drain current flows at the back interface. As the BESOI ISFET is a non-intentionally doped device, the free conduction charge layer is formed by biasing the Back Gate electrode (VGB). When a positive enough VGB is applied, electrons are attracted and accumulated at the back interface, and therefore, current flows from source to drain when VDS (Drain bias) is applied. A Platinum (Pt) pseudo-electrode is used to apply front-gate voltage (VGF) to the sample solution.The experimental drain current (IDS) as a function of the front-gate voltage (VGF), for 25 V applied at the back-gate (VGB), is presented in Figure 3.A, which is possible to observe that the neutral pH (pH7) curve stayed between the acid pH (pH4) curve, in the left, and alkaline pH (pH10) curve, in the right. This result shows that the threshold voltage (VTH) is lower for acid pH and higher for alkaline pH, what is compatible with the conventional ISFET results present in the literature (17). To corroborate the experimental measurement result, the device simulation was made with TCAD-Sentaurus (18), based in the paper (19). Figure 3.B shows the same trend for the simulated device with pH solution for any VGB value.In Figure 4, the threshold voltage was analyzed as a function of the pH for different VGB values. The VTH increases (becomes more positive) for alkaline pH values, regardless of the VGB applied. However, the VTH variation in the pH range, between pH4 and pH10, is different for different VGB values. With higher VGB applied, higher is the VTH variation. In Figure 5 Is possible to see clearly that the sensitivity (ΔVTH /ΔpH) increases with the VGB increase probably due to the small influence of the series resistance. In another hand, the acquired sensitivity values for VGB higher than 15 V in this work (about 25-33 mV/pH, approximately), is compatible with results present in the literature for conventional ISFETs with silicon dioxide (SiO2) for gate insulator (20). Figure 1

Radiation-Induced Degradation Mechanism of X-Ray SOI Pixel Sensors With Pinned Depleted Diode Structure

The X-ray Silicon-On-Insulator (SOI) pixel sensor named XRPIX has been developed for the future X-ray astronomical satellite FORCE. XRPIX is capable of a wide-band X-ray imaging spectroscopy from below 1 keV to a few tens of keV with a good timing resolution of a few tens of μs. However, it had a major issue with its radiation tolerance to the total ionizing dose (TID) effect because of its thick buried oxide layer due to the SOI structure. Although new device structures introducing pinned depleted diodes dramatically improved radiation tolerance, it remained unknown how radiation effects degrade the sensor performance. Thus, this paper reports the results of a study of the degradation mechanism of XRPIX due to radiation using device simulations. In particular, mechanisms of increases in dark current and readout noise are investigated by simulation, taking into account the positive charge accumulation in the oxide layer and the increase in the surface recombination velocity at the interface between the sensor layer and the oxide layer. As a result, it is found that the depletion of the buried p-well at the interface increases the dark current, and that the increase in the sense-node capacitance increases the readout noise.

(Invited, Digital Presentation) Approach to Neuromorphic Computing with Ferroelectric Schottky Barrier FETs

Neuromorphic computing inspired by neural network systems of the human brain enables energy efficient computing as a solution of the von Neumann bottleneck. A neural network consists of thousands or even millions of neurons which communicate with each other through connected synapses. Synapses can memorize and process the information simultaneously. The plasticity of a synapse to strengthen or weaken its activity over time make it be capable of learning and computing. Thus, artificial synapses which can emulate functionalities and the plasticity of bio-synapses form the backbone of a neuromorphic computing system.Non-volatile memories with two-terminals, like resistive random-access memory (ReRAM), phase change memory (PCM), are attractive candidates for artificial synapses. However, signal processing and learning cannot be performed simultaneously in these two-terminal synapses. FeFET, similar to a MOSFET structure using CMOS compatible HfO2 based ferroelectrics as gate oxide forms three-terminal synapses offering high endurance, good performance and high energy efficiency. In contrast to two-terminal devices, three terminal FeFET based synapses can perform processing and learning at the same time. In order to maintain the ferroelectric properties of an HfO2 based ferroelectric film, high temperature annealing should be avoided after the ferroelectric layer deposition. In this paper, we present ferroelectric NiSi2 source/drain Schottky barrier (SB) MOSFET (FE-SBFET) structure (Fig.1a), which requires neither ion implantation nor thermal activation of source/drain contacts at high temperatures.FE-SBFETs were fabricated on SOI substrates with a boron-doped (1016 B/cm-3), 55 nm thick top Si layer and a 145 nm thick buried oxide (BOX) layer. Very thin (9 nm) single crystalline NiSi2 layers which offer superior properties of uniform and stable SB contacts on Si are used at source/drain regions. A gate stack consisting of 10 nm thick Hf0.5Zr0.5O2 (HZO) layer and a 40 nm thick TiN layer are deposited by ALD and sputtering, respectively. A rapid thermal annealing at 500 °C is performed to crystallize the HZO into a ferroelectric phase before the gate patterning. The fabricated device has a channel length of 10 µm and a gate width of 10 µm. The overlap between the top gate and NiSi2 is 6 µm along the channel and 10 µm wide on each side. The ferroelectric polarization modulates both the SB at the source/drain contacts as well as the potential in the channel, thus changing the carrier injection through the SB. The Id-Vg transfer characteristics of a p-type FE-SBFET shows a clockwise hysteresis which is caused by the ferroelectric polarization switch.The excitatory post-synaptic current (EPSC), one of the typical short-term synaptic plasticity features for biologic synapses, is characterized by measuring the transient drain currents for a voltage pulse on the gate of a FE-SBFET (Fig.1b). The amplitude of the pulse VAM changes from -0.2 to -1.2 V with a fixed pulse width tpw=1 μs. We found that the EPSC peak value increases linearly with VAM. It shows a very low energy/spike consumption of 2fJ/spike at VAM=-0.2 V, demonstrating a very high energy efficiency. From the EPSC measurements with repeated gate voltage pulses paired-pulse facilitation/depression (PPF/PPD) are characterized showing an exponential decay, similar to biological synapses.The long-term synaptic plasticity of FE-SBFET synapses is characterized by a series repeated identical or non-identical pulses. The later can improve the long-term potentiation/depression (LTP/LTD) symmetry and linearity. The measurements show a large Gmax/Gmin ratio, very high endurance and small cycle-to-cycle (CTC) variation (1.06%) due to the perfect contact of NiSi2 (Fig.1c). The biological neuron-like spike-timing-dependent plasticity (STDP) is characterized for the FE-SBFET synapse. The results show an asymmetric anti-Hebbian STDP, which is one of the biological STDP functionalities (Fig.1d).In conclusion, the fabricated FE-SBFET synapse exhibits multiple synaptic functions with high endurance and small variations. The ultra-low energy/spike consumption indicates a high potential for low power neuromorphic computing applications. Acknowledgement: This work was supported by the Federal Ministry of Education and Research (BMBF, Germany) in the project NEUROTEC (16ME0398K). Figure 1

Lateral-Zigzag PN Junction Enabled High-Efficiency Silicon Micro-Ring Modulator Working at 100Gb/s

We propose and demonstrate a novel lateral-zigzag PN junction for silicon modulator working in C and O bands. The designed PN junction exhibits characteristics of large bandwidth, high modulation efficiency, and easy fabrication. For demonstration, it is embedded in a 220 nm silicon rib waveguide on a 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> thick buried oxide layer to form a micro-ring modulator. The measured 3 dB electro-optic bandwidth of the fabricated modulator is 42 GHz while the resistor-capacitor (RC) bandwidth is measured and calculated to be 174 GHz. Clear and open eye diagrams are obtained for 50 Gb/s non-return zero (NRZ) and 100 Gb/s four-level pulse amplitude modulation (PAM4) signals. The modulation power consumption is only 14 fj/bit.

Power enhancement of MEMS vibrational electrostatic energy harvester by stray capacitance reduction

We report a design method to enhance the output power of vibrational microelectromechanical system (MEMS) electrostatic energy harvesters by reducing the reactive power that does not contribute to the net output. The mechanism of enhancing the active current while reducing the reactive current is analytically studied using an equivalent circuit model of electret-based velocity-damped resonant-generator. Reduction of the internal parasitic capacitance associated to the contact pads and electrical interconnections significantly improves the power factor and increases the deliverable power. The design strategy is applied to an actual device that produces 1.3 mW from the vibrations of 0.65 G (1 G = 9.8 m s−2) at 158 Hz, suggesting a 2.9-fold enhancement of output power by increasing the buried oxide layer thickness from 1 µm to 3 µm.

Epitaxial Ge-Gd[formula omitted]O[formula omitted] on Si(111) substrate by sputtering for germanium-on-insulator applications

Germanium-on-insulator (GeOI) technology is a potential-alternative to the bulk-silicon based devices for radio-frequency (RF), and complementary metal oxide semiconductor applications at advanced technology nodes. A thin germanium channel is the key enabler of high mobility transistors and group-IV photonic devices. A prohibitive cost of GeOI wafers may discourage high volume manufacturing (HVM) despite promising performance. Here, we demonstrate epitaxial Gd2O3-Ge-Gd2O3 thin film growth on Si(111) substrate in an HVM platform - RF magnetron sputter system, where, the first Gd2O3 layer acts as buried-oxide (BOX) in the GeOI wafer. The second Gd2O3 layer is used as a cap-layer to be removed later using wet etching. Both the Gd2O3 layer is grown epitaxially at 750∘C, while the germanium layer is grown at room temperature and crystallised later by solid phase epitaxy (SPE) technique. The entire growth is performed without vacuum-break, to enable high throughput and excellent interface control. To compare the quality of the heterostructure, this sputter based SPE is performed on: (1) in-situ sputter grown, versus (2) ex-situ molecular-beam-epitaxy (MBE) grown epitaxial Gd2O3 BOX layer. The x-ray diffraction analysis confirms the formation of twin-free epitaxial Ge layer in the case of in-situ sputtered Gd2O3 while twinned Ge layer is observed in the case of ex-situ MBE grown Gd2O3. The twinning of the Ge layer in the ex-situ process is further supported by transmission electron microscopy analysis. Finally, we have performed an experiment to study the impact of Gd2O3 BOX layer thickness on the crystal quality of Ge layer and show that the Ge layer crystal quality remains intact irrespective of BOX layer thickness. Therefore, we have achieved twin free Ge epitaxy in RF magnetron sputter system, equivalent to in-situ All-MBE SPE process. Such a process enables low-cost GeOI wafer manufacturing for cost-effective RF transistors.

Applications of Direct-Current Current–Voltage Method to Total Ionizing Dose Radiation Characterization in SOI NMOSFETs with Different Process Conditions

As a promising candidate in space radiation hardened applications, silicon-on-insulator (SOI) devices face the severe problem of total ionizing dose (TID) radiation because of the thick buried oxide (BOX) layer. The direct-current current–voltage (DCIV) method was applied for studying TID radiation of SOI metal–oxide–semiconductor field–effect transistors (MOSFETs) with different manufacture processes. It is found that the peak of high-voltage well (PX) devices shows a larger left-shift and a slower multitude increase along with radiation dose, compared with that of low-voltage well (PV) devices. It is illustrated that the high P-type impurity concentration near back interface makes it more difficult to break up silicon hydrogen bonds, which gives the PX devices superiority in resisting the build-up of interface traps. The study results indicate that increasing doping concentration of the body region near the back-gate interface might be an alternative radiation hardening technique of SOI MOSFET devices to avoid the parasitic back transistors’ leakage.

Room-temperature bonded silicon on insulator wafers with a dense buried oxide layer formed by annealing a deposited silicon oxidation layer and surface-activated bonding

We propose a fabrication process for a silicon on insulator (SOI) wafer with an extremely thick buried oxide (BOX) layer for custom micro-electro mechanical systems (MEMS) devices. A BOX layer is generally formed by thermal oxidation above 800 °C. It is limited for this method to form an extremely thick layer of more than 10 μm. Thus, we attempted to deposit the BOX layer by chemical vapor deposition at 300 °C for a short time, followed by annealing at above 300 °C to make it denser. In addition, a silicon layer was bonded to the BOX layer at room temperature by surface activated bonding not to receive thermal stress. As a result, the bonding interface had no voids. The breakdown electric field of the BOX layer in the accidental B mode was improved by annealing. Therefore, SOI wafers fabricated by our method will be beneficial to next-generation MEMS device fabrication.

High resolution, high channel count mid-infrared arrayed waveguide gratings in silicon.

Arrayed waveguide gratings (AWGs) working in the 4.7 µm wavelength range are reported on silicon-on-insulator waveguides with 1500 nm thick silicon and 2 µm thick buried oxide layers. For eight channel devices, three different channel spacings (200 GHz, 100 GHz, and 50 GHz) with cross talk levels of -32.31dB, -31.87dB, and -27.28dB and insertion loss levels of -1.43dB, -4.2dB, and -2.3dB, respectively, are demonstrated. Fourteen channel AWGs with 170 GHz channel spacing and 16 channel AWGs with 87 GHz channel spacing are shown to have a cross talk value of -21.67dB and -24.30dB and insertion loss value of -4.2dB and -3.8dB, respectively. Two AWGs with 10 nm difference in channel peak are designed, and the measurements show a 9.3 nm difference. The transmission spectrum shift as a function of temperature is found to be 0.22 nm/°C.

Silicon nitride optical phased array based on a grating antenna enabling wavelength-tuned beam steering.

An optical phased array (OPA) in silicon nitride (SiN) is conspicuously highlighted as a vital alternative to its counterpart in silicon. However, a limited number of studies have been conducted on this array in terms of wavelength-tuned beam steering. A SiN OPA has been proposed and implemented with a grating antenna that incorporated an array of shallow-etched waveguides, rendering wavelength-tuned beam steering along the longitudinal direction. To accomplish a superior directionality on a wavelength-tuned beam steering, the spectral beam emission characteristics of the antenna have been explored from the viewpoint of a planar structure that entails a buried oxide (BOX), a SiN waveguide core, and an upper cladding. Two OPA devices having substantially different thicknesses of the resonant cavities, established by combining the BOX and SiN core, were considered theoretically and experimentally to scrutinize the spectral emission characteristics of the antenna on beam steering. Both of the fabricated OPA devices steered light by an angle of 7.4° along the longitudinal direction for a wavelength ranging from 1530 to 1630 nm, while they maintained a divergence angle of 0.2°×0.6° in the longitudinal and lateral directions. Meanwhile, the OPA fabricated on a substantially thick BOX layer featured a limited steering performance to attain a stabilized response over a broad spectral region. We examined the influence of the cavity thickness on the spectral response of the antenna in terms of optical thickness. Based on the two antenna characteristics, it was confirmed that the grating antenna emitted the beam with a higher efficiency when the optical thickness of the cavity corresponded to odd integer multiples of the quarter wavelength. This work is a considerable strategy for designing a stabilized SiN OPA over a desired spectral region.

Analytical model of LDMOS with a single step buried oxide layer

In this paper, a two-dimensional analytical model is established for the Single-Step Buried Oxide SOI structure proposed by the authors. Based on the two-dimensional Poisson equation, the analytic expression of the surface electric field and potential distributions for the device is achieved. In the SBOSOI (Single-Step Buried Oxide Silicon On Insulator) structure, the buried oxide layer thickness changes stepwise along the drift region, and the electric field in the oxide layer also varies with the different buried oxide layer thickness. These variations will modulate the surface electric field distribution through the electric field modulation effects, which makes the surface electric field distribution more uniform. As a result, the breakdown voltage of the device is improved by 60% compared with the conventional SOI structure.To verify the accuracy of the analytical model, the device simulation software ISE TCAD is utilized, the analytical values are in good agreement with the simulation results by the simulation software. The results verified the established two-dimensional analytical model for SBOSOI structure is valid, and it also illustrates the breakdown voltage enhancement by the electric field modulation effect sufficiently.The established analytical models will provide the physical and mathematical basis for further analysis of the new power devices with the patterned buried oxide layer.

Analytical model of LDMOS with a double step buried oxide layer

In this paper, a two-dimensional analytical model is established for the Buried Oxide Double Step Silicon On Insulator structure proposed by the authors. Based on the two-dimensional Poisson equation, the analytic expressions of the surface electric field and potential distributions for the device are achieved. In the BODS (Buried Oxide Double Step Silicon On Insulator) structure, the buried oxide layer thickness changes stepwise along the drift region, and the positive charge in the drift region can be accumulated at the corner of the step. These accumulated charge function as the space charge in the depleted drift region. At the same time, the electric field in the oxide layer also varies with the different drift region thickness. These variations especially the accumulated charge will modulate the surface electric field distribution through the electric field modulation effects, which makes the surface electric field distribution more uniform. As a result, the breakdown voltage of the device is improved by 30% compared with the conventional SOI structure.To verify the accuracy of the analytical model, the device simulation software ISE TCAD is utilized, the analytical values are in good agreement with the simulation results by the simulation software. That means the established two-dimensional analytical model for BODS structure is valid, and it also illustrates the breakdown voltage enhancement by the electric field modulation effect sufficiently.The established analytical models will provide the physical and mathematical basis for further analysis of the new power devices with the patterned buried oxide layer.

Analysis and reduction of leakage current of 2 kV monolithic isolator with wide trench spiral isolation structure

In this work, the origin of the leakage current of a highly area-efficient silicon-on-insulator (SOI) monolithic isolator using a spiral trench isolation structure is clarified by experimental and simulation analyses and its reduction method is proposed. It was found that parasitic MOSFET inversion and accumulation channels formed at the SOI and buried oxide (BOX) interface are the origins of leakage current. To reduce the leakage current, adequate SOI spiral length and width and BOX layer thickness are proposed for various voltage usages and show the possibility of 4 kV voltage tolerance and 500 MΩ isolation resistivity.

Investigation of Electrostatic Integrity of Nanoscale Dual Material Gate Dielectric Pocket Silicon-on-Void (DMGDPSOV) MOSFET for Improved Device Scalability

This paper presents a 2-D temperature-dependent analytical drain current model, which is valid for six different device architectures (by slightly modifying the used parameters), i.e., dual material gate dielectric pocket silicon-on-void, dual material gate silicon-on-void, dual material gate silicon-on-insulator, dielectric pocket silicon-on-void, silicon-on-void, and silicon-on-insulator MOSFETs. The results thus obtained, i.e., drain current, transconductance, $g_{m}$/$I_{\rm ds}$ ratio, threshold voltage, subthreshold slope, and $I_{\rm on}$ /$I_{\rm off}$ ratio have been verified with the simulated results obtained using ATLAS 3-D device simulator for channel length down to 30 nm. The analytical model is also used to investigate the impact of temperature variation on the characteristics of N-MOS inverter based on different architectures. In addition, impact of process and parameters variation (i.e., variation in shallow extension depth $(X_{e})$, side pillar thickness $(T_{\rm st})$, thickness of buried oxide layer $(t_{3})$ along with the variation in temperature) on the subthreshold performance of different devices has also been studied through exhaustive device simulation.

Quantitative Extraction of Electric Flux in the Buried-Oxide Layer and Investigation of Its Effects on MOSFET Characteristics

Silicon-on-insulator (SOI) MOSFETs have advantages over conventional bulk MOSFETs in terms of their electrical characteristics, but also have inherent disadvantages due to the presence of their buried-oxide (BOX) layers. In this paper, focus was placed on drain electric flux passing via the BOX layer to the body region as an influence that induces disadvantages such as drain-induced barrier lowering in SOI MOSFETs. The electric flux in the BOX layer was visualized using stream functions, and was quantitatively evaluated for the first time ever. The results showed the dependence of electric flux on relative permittivity and the BOX layer thickness. These outcomes confirmed that the subthreshold slope (SS) in short-channel SOI MOSFETs is affected strongly by electric flux detouring via the BOX layer, and the compact model of the enhancement of SSs due to the flux is proposed.

Ultra-compact optical 90° hybrid based on a wedge-shaped 2 × 4 MMI coupler and a 2 × 2 MMI coupler in silicon-on-insulator

We propose an ultra-compact optical 90° hybrid with the smallest length of 107μm, consisting of a wedge-shaped 2 × 4 MMI coupler connected with a 2 × 2 MMI coupler using silicon nanowaveguide technology. Neither cascaded phase shifters nor waveguide crossings are attached to the proposed 90° hybrid in coherent receiving system. The proposed device is demonstrated on silicon-on-insulator (SOI) with 220nm thick top-silicon layer and 2μm thick buried oxide layer. A high performance of the proposed 90° hybrid is exhibited experimentally with a high extinction ratio larger than 20dB, an excess loss mostly less than 0.5dB, a common mode rejection ratio better than -20dB and phase deviation within the range of 5° over C-band spectral range.

Residual stresses at cavity corners in silicon-on-insulator bonded wafers

Uncontrolled residual stresses in both integrated circuit and micro-electro-mechanical system applications may affect device performance and reliability, making microscale experimental analysis of the residual stresses an essential part of process and quality control. This work studies the residual stresses generated from different processing parameters common in the manufacture of silicon-on-insulator wafers with buried cavities (cavity-SOI). The buried cavities can concentrate the residual stresses and generate localized mechanical failures. Infrared photoelasticity and optical profilometry are used here to analyze the stress state in wafers after each of several critical processing steps, each with different process parameters. It is found that the residual stresses associated with cavities in the bonded wafers may significantly increase depending upon the oxidation/etching steps and that the stress magnitude is dependent upon the particular etched cavity geometry. Process-dependent stress states and their generation mechanisms are explained for each processing step. The oxide layer grown on cavity sidewalls is found to significantly impact the residual stress at the cavity corners, with a strong dependence on buried oxide layer thickness. By selecting appropriate processing steps and parameters, the magnitude and orientation of the residual stress in the cavity-SOI wafers can be controlled to enhance reliability.

Silicon nitride CMOS-compatible platform for integrated photonics applications at visible wavelengths

Silicon nitride is demonstrated as a high performance and cost-effective solution for dense integrated photonic circuits in the visible spectrum. Experimental results for nanophotonic waveguides fabricated in a standard CMOS pilot line with losses below 0.71dB/cm in an aqueous environment and 0.51dB/cm with silicon dioxide cladding are reported. Design and characterization of waveguide bends, grating couplers and multimode interference couplers (MMI) at a wavelength of 660 nm are presented. The index contrast of this technology enables high integration densities with insertion losses below 0.05 dB per 90° bend for radii as small as 35 µm. By a proper design of the buried oxide layer thickness, grating couplers with efficiencies above 38% for the TE polarization have been obtained.

Passive Photonics in an Unmodified CMOS Technology With No Post-Processing Required

Passive photonic components consisting of sub-micrometer waveguides, grating couplers, and ring resonators are demonstrated in an unmodified commercial complementary metal-oxide-semiconductor (CMOS) process. Waveguides demonstrate propagation losses of approximately 1 dB/mm at 1.3-μm wavelengths. Grating couplers achieve better than -5.8-dB coupling efficiencies. Ring resonators exhibit Qs greater than 5000 with extinction ratios of more than 20 dB. Furthermore, due to the utilization of front-end-of-the-line design layers for creating the waveguide cores coupled with a relatively thick buried-oxide layer standard within the process, no post-processing is required at the chip or wafer level to achieve the reported device performance. Hence, for the first time, designers without processing capabilities may design custom CMOS photonic circuits for a broad range of applications. One such application which may appropriately leverage the low-cost platform could be disposable bio-photonic sensor arrays.

A New Slope SOI-LDMOS High-Voltage Power Device

A slope SOI-LDMOS power device is proposed for high-voltage. When a positive bais is applied to the drain electrode, holes are induced and astricted by the slope buried oxide layer. So a high density positive charge layer is formed on the buried oxide layer. The electrical field in the buried oxide is improved as well as vertical breakdown voltage by the layer. Because the thickness of the drift region linearly increases from the source to the drain, the surface electric field is optimized, resulting in increase of lateral breakdown voltage. In this paper, the electric characteristics of the new device are simulated by Medici softerware. The result is shown that above 600 V breakdown voltage is obtained at 1μm thick buried oxide layer. The breakdown voltage is higher by three times than that of conventional SOI LDMOS.