Buried-channel Transistors Research Articles

Total dose radiation effects of hybrid bulk/SOI CMOS active pixel with buried channel SOI source follower

A CMOS active pixel with pinned photodiode which used in-pixel buried-channel (BC) transistor has been reported, and the characteristic of CMOS image sensor with in-pixel buried-channel transistor was carried out. In this paper, we have a research on a hybrid bulk/silicon-on-insulator (SOI) CMOS active pixel with pinned photodiode which use buried channel SOI NMOS Source Flower (SF) by simulation. We study the basic characteristics of buried-channel SOI NMOS and the characteristics of CMOS active pixel optimized by using in-pixel buried-channel SOI transistor under radiation. The results show that, compared to the conventional active pixel with the standard surface-channel (SC) SOI NMOS SF, the dark random noise of the pixel which uses in-pixel buried channel SOI NMOS SF can be reduced under the radiation and the output swing is improved.

Performance of Deep-Depletion Buried-Channel $n$-MOSFETs for CMOS Image Sensors

Buried-channel (BC) MOSFETs are known to have better noise performance than their surface-channel (SC) counterparts when used as a source follower in modern charge-coupled devices (CCDs). CMOS image sensors are finding increasing applications and compete with CCDs in high-performance imaging, but BC transistors are rarely used in CMOS. As a part of the development of charge storage using CCDs in CMOS, we designed and manufactured deep-depletion BC n-type MOSFETs in 0.18- μm CMOS image sensor process. The BC transistors are designed in a way similar to the source followers in a typical BC CCD, and feature deep n-channel implant and threshold voltage exceeding -2.5 V. In this paper, we report the results from their characterization and compare them with normal enhancement mode and “zero-threshold” SC devices. In addition to the detailed current-voltage and noise measurements, 2-D semiconductor device simulation results are presented to illustrate and understand the different conditions affecting the channel conduction and the noise performance of the BC transistors. We show that under optimal bias conditions the noise performance of the BC transistors can be superior despite their lower gain as in-pixel source followers.

A Statistical Evaluation of Random Telegraph Noise of In-Pixel Source Follower Equivalent Surface and Buried Channel Transistors

Using a large-scale array test circuit, both static characteristics and random telegraph noise (RTN) of in-pixel source follower equivalent transistors of a CMOS image sensor with buried and surface channel transistor structures were statistically evaluated under various current and body bias conditions. The distribution of noise intensities at various operational bias conditions, correlations between RTN amplitude and static characteristics were analyzed. It was found that the RTN amplitude has a positive correlation between the subthreshold swing for both types of transistors.

Reverse short and narrow channel effects in n and p transistors: quantification of the enhanced diffusion and the gate oxide thickness increase

The threshold voltage (VT) of CMOS 6 IBM technology n and p transistors function of their length L was investigated. A reverse short channel effect (RSCE) was observed simultaneously on the n inverted and p buried channel transistors, i.e. a VT n( L) increase and a correlated VT p( L) decrease when L was decreased. The same effect was observed for narrower channels. After correction of the standard short channel effect, the correlation between VT n( L) and VT p( L) was explained by two components: first a boron oxidation enhanced diffusion in the channel during the sidewall polysilicon gate oxidation; second, an increase of the gate oxide electrical thickness inversely proportional to the gate conductor width. This thickness increase was interpreted as due to a contaminant diffusion from the gate stack sidewall during the sidewall oxidation, either oxygen producing a physical thickness increase, or fluorine reducing the oxide dielectric constant.

Characteristics of inversion-channel and buried-channel MOS devices in 6H-SiC

Inversion-channel and buried-channel gate-controlled diodes and MOSFET's are investigated in the wide bandgap semiconductor 6H-SiC. These devices are fabricated using thermal oxidation and ion implantation. The gate-controlled diodes allow room temperature measurement of surface states, which is difficult with MOS capacitors due to the 3 eV bandgap of 6H-SiC. An effective electron mobility of 20 cm/sup 2//Vs is measured for the inversion-channel devices and a bulk electron mobility of 180 cm/sup 2//Vs is found in the channel of the buried-channel MOSFET. The buried-channel transistor is the first ion-implanted channel device in SIC and the first buried-channel MOSFET in the 6H-SiC polytype. >

Ionizing radiation hardening of a CCD technology

A three-level polysilicon, buried channel charge coupled device (CCD) technology has been tested for Co/sup 60/ ionizing radiation damage up to a total dose of 90 krad(Si). For this purpose CCD image sensors have been irradiated together with their associated test structures. These include different types of MOSFETs, natural transistors, buried channel transistors, field transistors, and diodes. The devices have been fully characterized during irradiation and afterwards, as a function of time. The standard technology has been assessed, leading to the implementation of process and design modifications. The modified technology has been further tested according to the same procedure and significant improvement in the sensors' behavior under irradiation and during annealing has been observed. The radiation hardness of the CCDs has been correlated with the results of the test structures, allowing a better understanding of the degradation phenomena and of the countermeasures needed for a radiation-hardened technology. >

A general gate-current p-MOS lifetime prediction method applicable to different channel structures

A recently developed surface-channel p-MOS lifetime prediction technique based on injection gate charge is extended to buried-channel devices. It is shown that a more general form of the equation governing the degradation accurately describes the degradation behavior of both surface-channel and buried-channel transistors, indicating that the method has general applicability for p-channel transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Suppression of hot-carrier effects in submicrometer surface-channel PMOSFETs

Hot-carrier-induced degradation in surface-channel (p-type polysilicon gate) PMOSFETs is investigated. Hot-electron-induced punchthrough is found to limit the lifetime of these devices. Although these surface-channel devices are observed to be more reliable than conventional buried-channel transistors, a lightly doped drain design is found to be necessary to provide adequate suppression of hot-carrier generation in 0.8- mu m-gate-length (L/sub eff/=0.5 mu m) transistors operated at 5 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Channel potential and channel width in narrow buried-channel MOSFET's

A new method is described for determining the effective width over which incremental charge spreads in a narrow buried-channel transistor. The method is based on the transconductance in the buried-channel mode. Experimental results for effective widths and channel potential shifts are presented for MOSFET's with effective channel widths from 2 to 10 µm. Two-dimensional numerical calculations verify the experimental results.

A survey of high-density dynamic RAM cell concepts

The performance capabilities of a variety of dynamic RAM cell concepts proposed in recent years are compared to the industry standard one-transistor cell. The new concepts are divided into three categories. The lateral charge sensing cells such as the Charge-Coupled cell, Hi-C cell, Merged-Charge cell, and Stacked-Capacitor cell. Vertical cells such as VMOS, the Punchthrough Isolated, and the Buried-Bit-Line cell which make use of the third dimension to achieve higher density. The Stratified-Charge cell and Taper-Isolated cell use current sensing of a dynamic change in the threshold voltage of a buried-channel transistor. The various cells were fabricated and compared on the basis of signal size, leakage rates, packing density, and fabrication and operational complexity. An overall figure of merit for a dRAM cell is suggested which combines all three considerations. Based on the cell concepts reported to date and this figure of merit, the Stacked-Capacitor, VMOS, and Punchthrough-Isolated cells ate the most promising charge storage cells. The Taper-Isolated cell, however, is shown to have significant overall advantage compared to the charge storage cells.

Extraction of implantation profiles from the differential body effect of ion-implanted m.o.s. transistors

A simple d.c. method is presented for the extraction of very shallow doping profiles in the depth range 0–200 nm in buried-channel transistors or c.c.d.s. The evaluation is free from complex corrections. Profile position and concentrations are determined with ± 5% accuracy.