A survey of high-density dynamic RAM cell concepts

Abstract

The performance capabilities of a variety of dynamic RAM cell concepts proposed in recent years are compared to the industry standard one-transistor cell. The new concepts are divided into three categories. The lateral charge sensing cells such as the Charge-Coupled cell, Hi-C cell, Merged-Charge cell, and Stacked-Capacitor cell. Vertical cells such as VMOS, the Punchthrough Isolated, and the Buried-Bit-Line cell which make use of the third dimension to achieve higher density. The Stratified-Charge cell and Taper-Isolated cell use current sensing of a dynamic change in the threshold voltage of a buried-channel transistor. The various cells were fabricated and compared on the basis of signal size, leakage rates, packing density, and fabrication and operational complexity. An overall figure of merit for a dRAM cell is suggested which combines all three considerations. Based on the cell concepts reported to date and this figure of merit, the Stacked-Capacitor, VMOS, and Punchthrough-Isolated cells ate the most promising charge storage cells. The Taper-Isolated cell, however, is shown to have significant overall advantage compared to the charge storage cells.