Bump Metallization Research Articles

Evaluation of Static and Dynamic Characteristics of Bump Metal Mesh Foil Bearing

Evaluation of Static and Dynamic Characteristics of Bump Metal Mesh Foil Bearing

Pre-applied underfill Technique for Fine-pitch Cu Pillar 3D Die Stacking to Enable 2.5/3D Advanced Packaging

Increased performance and smaller form factor have driven demand for next generation architectures for integrated circuit 3D (IC) chip packaging. Advanced chip packaging technologies, such as 2.5D and 3D, offer greater chip compatibility and lower power consumption. Given these advantages, the adoption of advanced packaging is inevitable. One key driver is the copper pillar interconnect technology which offers several benefits such as improved electromigration resistance, improved electrical and thermal conductivity, simplified under bump metallization (UBM), and higher input/output (I/O) density. The fine pitches that copper pillars are capable of helps the technology to supersede solder bump technology, which reaches its lowest pitch around 40 microns. Finer pitches allow for a higher I/O count, which enhances performance. One of the major innovations has been 2.5/3D integration, a technique of vertically stacking multiple dies. However, traditional encapsulation techniques become challenging because traditional capillary underfill methods become restrictive as enlarged surface area is required in order to provide underfill protection on multiple surfaces. Here, we discuss a novel approach of vertically stacking dies with an integrated underfill process that minimizes the required area for underfilling in fine-pitch IC chip packages by creating a technique to apply underfill during thermo-compression bonding. This process offers a reliable method for vertical stacking of multiple chips and eliminates post-processing need for underfill application. Additionally, the process provides precise temperature control to both the substrate and die by using a mechanism of dual heat application. This is used in combination with a controlled variable application of compressive force on the package. Through fine-tuning of the force and temperature applied to the IC components, the bonding process can be tailored to simultaneously provide the ideal underfill curing conditions while forming solder joints. In this work, we used dies with 80µm pitch Cu pillar flip chip copper pillars with tin/silver caps bonded to Electroless Nickel and Immersion Gold (ENIG) pads in conjunction with commercially available pre-applied underfill material. The interconnect strength was determined though destructive shear testing and cross-sectional analysis to evaluate for the bonding quality and strength. A scanning electron microscope was used to visually examine joint properties, and X-ray analysis was conducted to review for underfill voiding. Finally, completed assemblies were thermal-cycled to evaluate for the degradation of joint strength and voiding of underfill under induced stress.

A DFT Characterization of Structural, Mechanical, and Thermodynamic Properties of Ag9In4 Binary Intermetallic Compound

The intermetallic compounds (IMCs) at the interface between the solder joint and metal bond pad/under bump metallization (UBM) exert a significant impact on the thermal–mechanical behavior of microelectronic packages because of their unique physical properties. In this study, a theoretical investigation of the physical properties, namely structural, mechanical, and thermodynamic properties, of the Ag9In4 IMC was conducted using ab initio density functional theory (DFT) calculations. The calculated equilibrium lattice constants were in good agreement with the literature experimental data. Furthermore, with the calculated elastic constants, we can derive the ductility and brittleness nature, elastic anisotropy, and direction-dependent elastic properties of Ag9In4 through several elastic indices, three-dimensional surface representation, and two-dimensional projections of elastic properties. The calculations inferred that the cubic Ag9In4 IMC confers structural and mechanical stability, ductility, relative low stiffness and hardness, and elastic anisotropy. Finally, the thermodynamic properties, i.e., Debye temperature, heat capacity, and minimum thermal conductivity, were also investigated. Evidently, the low-temperature heat capacity conforms to the Debye heat capacity theory and the high-temperature one complies with the classical Dulong–Petit law.

(Digital Presentation) Electrochemical Deposition of Sn-Cu Alloys for Applications in 3D Stacking in Microelectronics Industry

The use of eutectic Sn-Cu alloys in packaging applications in microelectronics industry is not something entirely new. However, this alloy was mostly used in large features and fabricated using metal powders and metallurgical deposition techniques. The diameter of an individual grain of the eutectic Sn-Cu powder is typically similar in size to the diameter of pillars or bumps currently used in 3D stacking, and if we were to check its usefulness as a solder on this scale, an alternative manufacturing technique had to be used.We have electrochemically deposited Sn-Cu alloys having up to 10 wt.% Cu and explored its possible benefits when used as a solder in combination with different Under bump metallization (UBM) materials. Sn-Cu alloys were deposited on blanket and patterned coupons, and promising experiments then transferred to a wafer-scale, i.e. Sn-Cu alloys were deposited on 300 mm wafers in an industrial-type plating tool. A typical sample/wafer had a Cu seed with a diffusion barrier (e.g. TiW) underneath and patterned features defined with a photoresist mask. Characteristic dimensions of the patterned features were on the order of mm and cm (lines), (diameter)D50µm × (height)H60 µm (pillars), and D8µm × H15 µm (bumps). Cu, Ni, or Co were used as UBM layers.Chemical composition of deposited alloys has been examined by using X-ray fluorescence (XRF), Micro X-ray fluorescence (Micro-XRF), Inductively coupled plasma mass spectrometry (ICP-MS), and Electron probe microanalysis (EPMA). Surface morphology and the shape of deposited features have been examined using Scanning electron microscopy (SEM) and Laser scanning microscopy (LSM), while thermodynamic properties have been studied using Differential scanning calorimetry (DSC). Within-wafer (WIW) and within-die (WID) height uniformity of the pillars has been analyzed using Falcon 630 Plus tool (Camtek Ltd), capable of capturing heights of all the structures on the wafer simultaneously. The kinetics of Intermetallic compound (IMC) formation have been studied in the number of selected samples by combining ex-situ Focused ion beam (FIB) and in-situ measurements of resistance change of the features during anneal/thermal ageing [1].We will discuss possible benefits and drawbacks for use of electrochemically deposited Sn-Cu alloy solders in combination with different UBM layers based on these results.

Effect of Grain Structure and Ni/Au-UBM Layer on Electromigration-Induced Failure Mechanism in Sn-3.0Ag-0.5Cu Solder Joints

The development of advanced electronic devices leads to highly miniaturized interconnect circuits (ICs), which significantly increases the electromigration (EM) phenomenon of solder and circuits due to higher current density. The electromigration of solder joints under high current density has become a severe reliability concern in terms of microelectronic product reliability. The microstructure of the solder plays an important role in the electromigration induced degradation. In this study, Sn-3.0Ag-0.5Cu solder bumps with Ni/Au under bump metallization (UBM) layer were fabricated and electromigration acceleration tests were conducted under current density of 1.4 × 104 A/cm2 and 120 °C to investigate the effect of grain structure and Ni/Au-UBM layer on EM-induced failure. Grain structures of solder bumps were determined by utilizing the Electron Backscatter Diffraction (EBSD) technique, and single-crystal solder, single-crystal dominated solder, and polycrystalline solder are observed in different test samples. According to the Scanning Electron Microscope (SEM) images, it is observed that the Ni/Au-UBM layer of the Cu pad can inhibit atom diffusion between solder bump and Cu pad, which reduces the consumption of Cu pad but causes a large void and crack at the interface. The EM lifetime of single crystal solder bumps is lower than that of polycrystalline solder bumps when the c-axis of single crystal solder bumps is perpendicular to the electron flow direction. Additionally, the single crystal structure will increase the brittleness of the solder bump, and cracks are easily generated and expanded under the stress caused by the mismatch of thermal expansion coefficients between the solder bump and Ni/Au-UBM layer near Cu pad. Polycrystalline solder bumps with a higher misorientation angle (15–55°) have a higher atom diffusion rate, which will result in the acceleration of the EM-induced failure.

Electrochemical deposition of indium from chloride bath for low-temperature microbump bonding

Indium chloride bath was characterized towards the application of low-temperature thermal compression bonding. The electrochemical behavior of the indium chloride bath was analyzed using the cyclic voltammetry method. Electrochemical deposition of indium was carried out at various deposition factors on different materials such as copper, nickel, and cobalt. Based on the results of indium deposition obtained from the blanket films, indium bumps were electrochemically fabricated inside a through-resist hole pattern at various current densities. In addition, stacked indium bumps with various metals (Cu/In, Cu/Ni/In, Cu/Co/In) were formed for a practical application of micro bump bonding. Moreover, the formation of the intermetallic compounds between indium and under bump metallization was investigated.

Mechanism on preferred orientation roof-type Cu6Sn5 grain formation in micro-bump with (111) nanotwinned copper UBM

The (111) nanotwinned copper films used as a novel under bump metallization (UBM) were applied in micro-bump solder technology for 3D packaging. The orientation and morphology of interfacial Cu 6 Sn 5 grains on (111) nanotwinned copper UBMs were investigated by soldering at different temperatures (250 °C and 300 °C). The (11−20) preferred orientation roof-type Cu 6 Sn 5 intermetallic compound (IMC) formed on Sn/(111) nanotwinned copper interface at a higher soldering temperature of 300 °C; while random orientation scallop-type Cu 6 Sn 5 grains formed on Sn/(111) nanotwinned copper interface at lower soldering temperature of 250 °C. The preferred orientation relationships between and interfacial roof-type Cu 6 Sn 5 grains and (111) nanotwinned copper UBMs are {11−20} Cu6Sn5 ||{111} copper in 〈0001〉 Cu6Sn5 ||〈011〉 copper and {11–20} Cu6Sn5 ||{111} copper in 〈10−10〉 Cu6Sn5 ||〈112〉 copper . Moreover, the average shear strength of the (111) nanotwinned copper/Sn/(111) nanotwinned copper solder interconnects soldered at 300 °C (40.19 MPa) is 30% higher than that soldered at 250 °C (31.09 MPa). This study provides an insight in controlling the morphology and orientation of interfacial Cu 6 Sn 5 grains on the (111) nanotwinned copper used as UBMs for the 3D packaging application. • Random intersecting angles of roof-type Cu 6 Sn 5 grains formed on (111) nt-Cu UBM. • ORs: {11–20} η ||{111} Cu in <0001> η ||<011 > Cu , {11–20} η ||{111} Cu in<10–10 > η||<112 > Cu . • Average shear strength of the solder interconnects soldered at 300 °C is 40.19 MPa.

Effect of Intermetallic Compound Bridging on the Cracking Resistance of Sn2.3Ag Microbumps with Different UBM Structures under Thermal Cycling

In this study, the effect of intermetallic compound (IMC) bridging on the cracking resistance of microbumps with two different under bump metallization (UBM) systems, Cu/solder/Cu and Cu/solder/Ni, under a thermal cycling test (TCT) is investigated. The height of the Sn2.3Ag solders was ~10 µm, which resembles that of the most commonly used microbumps. We adjusted the reflow time to control the IMC bridging level. The samples with different bridging levels were tested under a TCT (−55–125 °C). After 1000 and 2000 TCT cycles (30 min/cycle), the samples were then polished and characterized using a scanning electron microscope (SEM). Before IMC bridging, various cracks in both systems were observed at the IMC/solder interfaces after the 1000-cycle tests. The cracks propagated as cyclic shapes from the sides to the center and became more severe as the thermal cycle was increased. With IMC bridging, we could not observe any further failure in all the samples even when the thermal cycle was up to 2000. We discovered that IMC bridging effectively suppressed crack formation in microbumps under TCTs.

Theoretical and experimental investigations on mechanical properties of (Fe,Ni)Sn2 intermetallic compounds formed in SnAgCu/Fe-Ni solder joints

The effect of Ni element on mechanical properties of FeSn2 phase was investigated by means of nano-indentation measurements and first-principles calculations. The Ni content within (Fe,Ni)Sn2 interfacial intermetallic compounds (IMCs) were controlled by using different FeNi under bump metallizations (UBMs) within SnAgCu(SAC)/Fe-Ni solder joints. For SAC/Fe-45Ni (45 wt% Ni) solder joint, (Fe,Ni)Sn2 phase has coarser grains with an average amount of 1.5 at.% Ni as confirmed by scanning electron microscopy (SEM) observation and energy disperse spectroscopy (EDS). Its average Young's modulus and hardness are 134.1 GPa and 6.0 GPa respectively as measured by nano-indentation test. While for SAC/Fe-73Ni solder joints, (Fe,Ni)Sn2 phase has smaller grain size with 4.2 at.% Ni solid solution. The corresponding Young's modulus and hardness are 143.2 GPa and 6.1 GPa respectively. As further confirmed by transmission electron microscopy (TEM) and selected area electron diffraction (SAED), the (Fe,Ni)Sn2 phase possesses a crystalline of I4/mcm space group. The mechanical properties of pure FeSn2, Fe23NiSn48(about 1.5 at. % Ni) and Fe7NiSn16(about 4.2 at. % Ni) are also calculated using first principle calculation. The calculated results showed that Young's modulus increased from 134.8GPa to 139.9GPa as the Ni concentrations increased from 0 at.% to 4.2 at.%. Combining theoretical and experimental methods, we can safely conclude that the introduction of Ni element improves the Young's modulus of FeSn2 phase. However, ductility of FeSn2-based phase was the worst among the common IMCs deducing from the B/G value. And the brittleness was also confirmed by the fracture surface according to SEM observation. The brittleness of (Fe,Ni)Sn2 phase might be a risk of the reliability of SAC/Fe-Ni solder joints.

Interfacial Reactions of Sn-3.0Ag-0.5Cu Solder with Sputter Cu-Ti Alloy Film UBM

Herein, the influence of Ti additive on the formation of intermetallic compounds (IMC) in a SAC/Cu-Ti soldered joint and corresponding mechanical properties are systematically investigated. The Ti-to-Cu ratio under bump metallization (UBM) is adjusted by tuning the target current during magnetron sputtering. Interestingly, the needle-like IMC, which is different from the traditional scallop-like IMC, is formed in the SAC/Cu-Ti soldered joint after reflow. The growth of Cu3Sn and Kirkendall voids is significantly inhibited after thermal aging in the SAC/Cu-Ti soldered joint. Overall, the segregation of Ti at grain boundaries forms a titanium-rich layer. Also, the Ti-rich layer acts as a diffusion barrier layer and hinders the diffusion of Cu into IMC. The shear strength test results show that SAC/Cu-Ti has much stronger strength than SAC/Cu both before and after thermal aging. These results confirm that Cu-Ti UBM is beneficial to the improvement of welding reliability.

Formation and nanomechanical properties of intermetallic compounds in electrodeposited Cu–Sn–Co multilayers

The properties of the intermetallic compounds (IMCs) formed at the interface between the solder and the Under Bump Metallization (UBM) are crucial for the reliability of solder joints. Cobalt (Co) is a potential candidate for UBM since it can act as a diffusion barrier and hence can improve the performance of tin-based solder joints. Growth kinetics, mechanism of formation, and properties of IMC in the copper-tin-cobalt (Cu–Sn–Co) system that is encountered with Co UBM are presented in this paper. Cu–Sn–Co systems were prepared by electrodeposition of Cu, Sn and Co multilayers on Cu substrates followed by reflow at 250 °C for varying durations (1–30 min). Microscopic observation revealed the formation of defect-free (Co,Cu)Sn3, crack-containing (Cu,Co)6Sn5 and thin irregular Cu3Sn IMCs after 1 min reflow. As reflow duration increased, (Co,Cu)Sn3 and Cu3Sn grew at the expense of (Cu, Co)6Sn5. The consumption of the entire Sn layer after 1 min and the calculated effective interdiffusion coefficient of (Co,Cu)Sn3 suggested that the growth of (Co,Cu)Sn3 after 1 min is controlled by solid-state diffusion of Sn. The average Young’s Modulus values of (Co,Cu)Sn3, (Cu,Co)6Sn5 and Cu3Sn are 99.5 ± 3.2 GPa, 110.8 ± 7.3 GPa and 109.4 ± 0.3 GPa, respectively, while the nanohardness values are 4.15 ± 0.34 GPa, 6.74 ± 0.62 GPa and 4.96 ± 1.09 GPa, respectively. Increasing the reflow duration in the Cu–Sn–Co system is expected to improve the performance of the solder joint, through the replacement of the crack-containing (Cu,Co)6Sn5 by the defect-free (Co,Cu)Sn3.

Improvement of thermomigration resistance in lead-free Sn3.5Ag alloys by Ag interlayer

A significant improvement of thermomigration (TM) resistance in Pb-free Sn3.5Ag alloys was achieved by a Ag interlayer. Ag interlayer was used to form Ag3Sn intermetallic compound (IMC) during reflowing process, which can serve as a barrier to suppress thermomigration-induced Cu flux under a temperature gradient. Two different kinds of sandwich samples were designed and compared, Cu/Ag/Sn3.5Ag/Cu and Cu/Sn3.5Ag/Cu. A heat sink and a heat source were employed to establish a temperature gradient of 7000 °C/cm. The growth rate of IMCs at cold end in Cu/Ag/Sn3.5Ag/Cu was slower than that in Cu/Sn3.5Ag/Cu. Thermomigration-induced Cu fluxes were also effectively inhibited in Cu/Ag/Sn3.5Ag/Cu specimens, and the calculated value of JCu,TM was about one-third times as that in Cu/Sn3.5Ag/Cu specimen. In addition, the dissolution of IMCs and under bump metallization (UBM) at hot end was barely observed in Cu/Ag/Sn3.5Ag/Cu specimen. These results suggest that Ag3Sn layer can be a diffusion barrier to effectively inhibit the Cu flux from hot end to cold end under a temperature gradient. Furthermore, crystallographic orientation of Sn grains was affected by the Ag interlayer, and it leads to the c-axis of Sn grain being more vertical to the direction of JCu,TM for the samples with Ag interlayer deposited, which further enhances the effect of suppression on JCu,TM.

A study on wettability and formation of intermetallic phase between Co–Cr–Mo alloy and Sn-Solder used as a potential under bump metallization for flip-chip packages

The wettability and formation of intermetallic compounds (IMCs) formed between a Co–Cr–Mo-based alloy and Sn-solder metal were investigated using the reflow soldering method. Soldering was conducted in an electric furnace in separate experiments at temperatures of 533, 553, 573, 623, and 673 K for 600 s. The morphology of the intermetallic layer formed at the Co–Cr–Mo-based/Sn-solder interface was characterized by scanning electron microscopy (SEM). The chemical composition and phase of the formed intermetallic layer were analyzed by electron probe microscopic analysis (EPMA) and X-ray diffraction analysis. Wettability analysis indicated that the soldering temperature influenced the wettability. With increasing soldering temperatures, the spreading factor increased, whereas the contact angle decreased. The intermetallic layers were found in triples in the intermediate zone between the solidified Sn-solder and the Co–Cr–Mo-based substrate. The thickness of the intermetallic layers increased in proportion with increasing soldering temperature. The EPMA analysis indicated only two IMCs formed at the interface of the joint at all of the investigated soldering temperatures, although three interfacial layers were observed by SEM analysis. The Sn-richer phase, Co(Cr,Mo)Sn2, formed adjacent to the Sn-solder matrix, whereas the Co(Cr,Mo)Sn was found near the Co–Cr–Mo-based substrate. The nanoindentation measurement revealed that the formed Co(Cr,Mo)Sn2 and Co(Cr,Mo)Sn IMCs possessed lower hardness values compared to the Sn–Cu intermetallic systems.

Synthesis, composition, morphology, and wettability of electroless Ni-Fe-P coatings with varying microstructures

Thermal stability and wettability are important properties for under bump metalization (UBM) in electronic devices. This study aims at preparing the Ni-Fe-P coatings with varying microstructures and investigating the effects of microstructures on their properties including surface morphology, roughness, chemical bonding and wettability. The microstructure of the Ni-Fe-P coatings was mainly controlled by their Fe content. The crystallinity of these coatings continuously increased to 100% when the Fe content reached 12 wt.%, while they exhibited amorphous structure with a Fe content of below 9 wt.%. The wettability order of these coatings are amorphous, crystalline and mixed structure from the best to the worst, which is mainly due to their surface roughness. Moreover, the Fe addition in the Ni-P coatings can promote their thermal stability, showing a good potential as UBMs at elevated temperature. In a temperature range of 340°C – 480°C, the amorphous Ni-Fe-P coatings gradually transformed into Ni3P, FeNi3 and slight Ni phases.

Electrochemical Deposition of Sn-Cu Alloys for Applications in 3D Stacking in Microelectronics Industry

The use of eutectic Sn-Cu alloys in packaging applications in microelectronics industry is not something entirely new. However, this alloy was mostly used in large features and fabricated using metal powders and metallurgical deposition techniques. The diameter of an individual grain of the eutectic Sn-Cu powder is typically similar in size to the diameter of pillars or bumps currently used in 3D stacking, and if we were to check its usefulness as a solder on this scale, an alternative manufacturing technique had to be used.We have electrochemically deposited Sn-Cu alloys having up to 10 wt.% Cu and explored its possible benefits when used as a solder in combination with different Under bump metallization (UBM) materials. Sn-Cu alloys were deposited on blanket and patterned coupons, and promising experiments then transferred to a wafer-scale, i.e. Sn-Cu alloys were deposited on 300 mm wafers in an industrial-type plating tool. A typical sample/wafer had a Cu seed with a diffusion barrier (e.g. TiW) underneath and patterned features defined with a photoresist mask. Characteristic dimensions of the patterned features were on the order of mm and cm (lines), (diameter, d)50µm × (height, H)60µm (pillars), and (d)8µm × (H)15µm (bumps). Cu, Ni, or Co were used as UBM layers.Chemical composition of deposited alloys has been examined by using X-ray fluorescence (XRF), Micro X-ray fluorescence (Micro-XRF), Inductively coupled plasma mass spectrometry (ICP-MS), and Electron probe microanalysis (EPMA). Surface morphology and the shape of deposited features have been examined using Scanning electron microscopy (SEM) and Laser scanning microscopy (LSM), while thermodynamic properties have been studied using Differential scanning calorimetry (DSC). Within-wafer (WIW) and within-die (WID) height uniformity of the pillars has been analyzed using Falcon 630 Plus tool (Camtek Ltd), capable of capturing heights of all the structures on the wafer simultaneously. The kinetics of Intermetallic compound (IMC) formation have been studied in the number of selected samples by combining ex-situ Focused ion beam (FIB) and in-situ measurements of resistance change of the features during anneal/thermal ageing [1].We will discuss possible benefits and drawbacks for use of electrochemically deposited Sn-Cu alloy solders in combination with different UBM layers based on these results.

Evaluation of creep properties for aged Pb-free solder joints/(Ni-P/Au) UBM with small addition Cu using shear punch creep testing method

The creep mechanical and physical properties of solder joints play an important role to ensure the service life of electronics products. In this paper, we investigated the creep properties of Pb-free Sn-4Ag and Sn-4Ag-0.5Cu (small additions Cu) solder joints on Ni-P/Au under bump metallization (UBM) using the shear punch creep test (SPCT) method at 30 °C. These results have been compared with the Pb-based Sn-37Pb solder joint after isothermal aging (150 °C) according to different times. In order to analyze the result of SPCT, the specific methods (i.e., Power-law relationship, Larson-Miller law and Monkman-Grant correlation) were used. Through the Power-law relationships, the stress exponents (n) of the Pb-free solder were higher than the Pb-based solder and generally, (n) value decreased with increasing aging time. Also, according to Larson-Miller law, the Pb-free solder joints revealed superior mechanical properties. The Monkman-Grant exponent (m) value of three solder joints which analyze by Monkman-Grant correlation is proximately 1. Furthermore, the failure fracture surface behavior of solder was investigated using scanning electron microscopy (SEM). Elongated dimple-like structures were detected on the fracture surfaces of all as-soldered (aging time 0 h) samples, but these gradually decreased with increasing aging time. The results indicated that the creep properties of Pb-free solder were better than Pb-based solders, and the Sn-4Ag-0.5Cu solder joint showed the best creep mechanical properties.

A Novel Intermetallic Compound Insertion Bonding to Improve Throughput for Sequential 3-D Stacking

This article provides a novel 3-D die-to-wafer (D2W) bonding method using intermetallic compound (IMC) layer insertion into a soft Sn bump to generate mechanical connection of two dies, called insertion bonding. A 50% decrease in stacking time can be obtained. Using this process close to a 100% electrical yield of daisy chains containing 800 fine pitch bumps (20 $\mu \text{m}$ ) is achieved. Various challenges for insertion bonding, such as material selection, surface properties of microbumps, bonding optimization, and compatibility with underfill materials, are discussed in this article. In addition, the potential application of IMC insertion bonding to prevent oxide formation for Co-based under bump metallization and as protection layer is explored.

Highly solderability of FeP film in contact with SnAgCu solder

New under bump metallization (UBM) is required for future microelectronics to minimize reliability concerns with solder interconnects. In this study, electroless FeP film was prepared as UBM. Solderability of electroless NiP, electrodeposite Fe and electroless FeP films with eutectic SnAgCu solder was investigated by static wetting tests and wetting balance measurements. Results revealed that the solderability of NiP film has almost no change with thermal aged for the film in air atmosphere increasing. The contact angles for FeP and Fe films with SnAgCu solder increased and the maximum wetting force decreased with heating time increasing from 0 h, 48 h, 89 h–160 h at 180 °C. But the solderability of FeP film was found to be better than those of NiP and Fe whether the films in base or thermal aged at 180 °C for 89 h. Even after thermal aged in air atmosphere at 180 °C for 160 h, the FeP also performed the smallest contace angle compared with the NiP and the Fe. Oxide layer on the surface of FeP was much easier to be removed by rosin mildly activated flux during reflow process because loose structure. It was proved to be the key for the highly solderability of electroless FeP.

Characterization of Electroless Nickel Plated Materials During High Temperature Solder Processing

Electroless nickel immersion gold (ENIG) has emerged as a leading surface finish for under bump metallization (UBM). An ENIG surface typically exhibits excellent planarity, good electrical characteristics, wettability for solder, and wire bond-ability. Reliability and performance of ENIG systems have been extensively reported at temperatures below 250°C; however, information is not readily available about its reliability at higher temperatures. In this paper, thermal behavior of electroless Ni/Au, Ni/Pd and Ni/Pd/Au during solder reflow processing at temperatures of up to 350°C is characterized. Wafer level evaluations were completed using optical microscopy and FIB cross-sectional SEMs, while packaged devices were subjected to standard reliability tests. Electroless Ni began to exhibit signs of cracking when exposed to temperatures of 350°C under certain conditions. Based on these findings, we propose electroless Ni material structures and maximum processing temperatures to minimize stress cracking at high reflow temperatures. This paper builds on our previous work by expanding the tested material structures to a gold-free process of Ni/Pd as well as 5um Ni/Pd/Au. Power devices manufactured with electroless Ni metallization can be capable of passing JEDEC qualification when implemented with these design parameters.

(Invited) Application of Three Dimensional Chip Stacking Technology for Fully Depleted Silicon-on-Insulator Quantum Beam Imager

Requirements of a quantum beam imager such as a vertex detector in high energy physics experiment are intelligent functions which are realized by embedding memories of quantum beam hit-position, hit-charge, and hit-timing in a pixel with keeping small pixel size to achieve high spatial resolution. To satisfy the requirements, circuit layer stacking on a sensor, i.e., three dimensional (3D) technology, has been widely studied and proposed. The Silicon-on-Insulator (SOI) sensor is one of the 3D sensors because the circuits in the top silicon layer is on the sensors of the bottom silicon substrate. The circuits and sensors are electrically connected by submicron W filled vias through the buried oxide (BOX), which are called as through BOX vias (TBV). Thus, the SOI sensor has extremely higher fill factor than the bulk-CMOS sensor. In order to achieve more intelligent functions in the pixel, however, the pixel size by using the simple SOI technology is large to get the required spatial resolution. Therefore, multiple circuit layer formation by chip stacking technology is adopted. In this chip stacking, a fine pitch micro-bump technology with two-tile face-to-face stacking is employed because of the simplest 3D structure. The target of micro bump diameter and spacing are 2.5 μm and 5 μm, respectively. The SOI 3D chip stacking process is starting with the base chips which are fabricated by an 8 inch 0.2 μm fully depleted SOI pixel sensor process with five metal layers. After the metal 5 etching, an oxide film is deposited and planarized by chemical mechanical polishing (CMP). W-filled vias to a under bump metal is formed at bump formation areas. After the under bump metal deposition and patterning, metal bumps are formed. Then, two chips which are lower and upper chips are aligned and bonded face-to-face at 200℃ followed by adhesive injection. To make bonding pads on the upper chip, the upper chip handle silicon is etched until exposing the BOX and TBV by wet solution. TBV can easily connect between circuits in the upper chip and the bonding pad metal without any through silicon via (TSV) process. This is the most superior point to use the FD-SOI pixel sensor in 3D structure. The TBV size is around 0.3 μm which is much smaller than a conventional TSV whose size is around 5 μm by using the most advanced technology. In addition, this TBV can be used as interconnections between multiple chips without any TSV. Finally, bonding pad and passivation formation are done. For micro bump formation, a gold bump was utilized because the gold is oxidation-resistant metal. The micro gold bump was fabricated by two methods. One is a cone shaped gold bump manufactured by a gold nanoparticle deposition with a photoresist lift-off technique [1]. The cone shaped gold bump with 2.5 μm in diameter and 2.5 μm in height are successfully formed on the under bump metal layer. Because of the nanoparticle deposition, the gold bump is easier to deform by the bonding. Thus, the collapsibility allows low stress to the die and high reliable junctions. It is also confirmed that the bump resistance is approximately 0.25 Ω/bump from daisy chain measurement. The other is a gold cylindrical bump using a combination of inverse-tapered photoresist and low incident angle sputtering [2]. Because of narrowing at the top, lower pressure to collapse between the bumps is required than the gold cone bumps. This may also improve bump yield and reliability. 0.37 Ω/bump of the bump resistance is obtained by the gold cylindrical bumps. Using the FD-SOI 3D chip stacking technology with the cylindrical bump, the pixel sensor designed for the International Linear Collider (ILC) vertex detector called SOFIST was fabricated and the chip photo is shown in the figure. In SOFIST, hit-position, hit-charge, and hit-time memories are embedded in each pixel by the 3D micro bump bonding with 20 mm pixel size. Owing to the removal of the handle silicon of the upper chip, the patterns of the lower chip can be seen through the upper chip oxide. The green patterns close to bonding pads are backsides of silicon layer in the upper chip. As shown in the figure, our 3D process technology is successfully introduced in FD-SOI quantum beam imager.