Bump Joints Research Articles

Electrical behavior of Au–Ge eutectic solder under aging for solder bump application in high temperature Electronics

As deep earth oil exploration transits into deeper earth, it faces challenges in producing reliable microelectronics devices and sensors that will not degrade at high temperature, especially those related to packaging materials and assembly of the devices. It has been reported that the mechanical performance of a high temperature Au–Ge eutectic solder is able to fulfill the minimum interconnection properties specified by the oil and gas exploration industry. However, the impact of thermal aging to Au–Ge eutectic solder’s electrical property is not clear. In this work, it is observed that the bulk Au–Ge electrical resistivity decreased initially with thermal aging and then saturated. This effect is mainly contributed by the grain growth of Au, which results in a reduction in grain boundaries, as well as coarsening of the Ge phases. On the other hand, study on the microstructure and electrical resistance of Au–Ge solder bump joint after aging shows that the electrical resistance increased. The increase in resistance is contributed mainly by the NiGe and Ni5Ge3 intermetallic compounds growth, which also led to a degradation in the Ni(P) barrier layer.

플렉시블 전자기기 응용을 위한 미세 솔더 범프 접합부에 관한 연구

In electronic industry, the trend of future electronics will be flexible, bendable, wearable electronics. Until now, there is few study on bonding technology and reliability of bonding joint between chip with micro solder bump and flexible substrate. In this study, we investigated joint properties of Si chip with eutectic Sn-58Bi solder bump on Cu pillar bump bonded on flexible substrate finished with ENIG by flip chip process. After flip chip bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test, thermal shock test, and bending test. After thermal shock test, we observed that crack initiated between <TEX>$Cu_6Sn_5IMC$</TEX> and Sn-Bi solder and then propagated within Sn-Bi solder and/or interface between IMC and solder. On the other hands, We observed that fracture propated at interface between Ni3Sn4 IMC and solder and/or in solder matrix after bending test.

Damage of lead-free solder joints in flip chip assemblies subjected to high-temperature thermal cycling

The damage mechanism of lead-free ball grid array (BGA) solder joints is studied whilst the magnitude of the damage was quantitatively evaluated to determine the impact of the thickness of inter-metallic compound (IMC) layer on the reliability of the joints. Five virtual test vehicle assemblies of flip chip (FC) which have 4–12μm thickness of IMC layer were subjected to the same accelerated high-temperature cycles utilising, in parts, the IEC standard 60749-25. The visco-plastic responses of the assemblies’ solder bump joints to the induced thermal load were simulated using Anand’s plasticity model. The results demonstrate that very thin and thick thickness of IMC layer impact the reliability of the FC solder joints. It was found that strain range at steady state joint damage is approximately 0.07–0.12. This finding indicates that strain controlled studies on bulk solder which are not up to these limits are inadequate to characterise damage behaviour and model damage evolution in the FC BGA solder bump joints. Further results show that the magnitude of the average accumulated visco-plastic energy density per cycle (wacc) depends on the volume percentage of solder and IMC in the joints. This dependency explains why the existing life prediction models based on wacc are not satisfactory in estimating the damage in solder joints. The authors propose the development of new prediction models which will be specific on the volume percentage of solder and IMC in the joints.

Estimation and visualization of the fatigue life of Pb-free SAC solder bump joints under thermal cycling

A method for estimating the fatigue life of Pb-free solder (Sn–3.0Ag–0.5Cu) bump joints under thermal cycling is described. The test specimens were 4, 6 and 8mm chip size packages mounted on printed circuit boards. To develop a semi-analytical model for estimating the thermal fatigue life, thermal cycle tests were carried out on the test specimens and the thermal fatigue life obtained experimentally was compared with the corresponding result from nonlinear, elastic–plastic finite element analysis. It was found that the chip size affected the thermal fatigue life and the strain accumulated in the solder bumps during thermal cycling. This was due to the difference in mechanical boundary conditions around the Si chip. Based on the Coffin–Manson law, an equation for estimating the thermal fatigue life was derived and the predicted fatigue life for various chip sizes and under different rises in temperature were found to be in good agreement with the experimental results. Moreover, a measurable parameter that correlates with the accumulated strain in the solder bumps was introduced for estimating the thermal fatigue life of the test specimens.

Effect of Bump Shape on Current Density and Temperature Distributions in Solder Bump Joints under Electromigration

Three dimensional thermo-electrical finite element analysis was employed to simulate the current density and temperature distributions for solder bump joints with different bump shapes. Mean-time-to-failure (MTTF) of electromigration was discussed. It was found that as the bump volume increased from hourglass bump to barrel bump, the maximum current density increased but the maximum temperature decreased. Hourglass bump with waist radius of 240 μm has the longest MTTF.

Effect of Interfacial Reaction Layer Thickness on Fracture Morphology and Impact Resistance of Sn-Ag-Cu Solder Bump Joint

Effect of Interfacial Reaction Layer Thickness on Fracture Morphology and Impact Resistance of Sn-Ag-Cu Solder Bump Joint

Use of Modified Accumulated Damage Model to Predict Fatigue Failure Lives of Sn-Ag-Cu-based Solder Joints in Ball-Grid-Array-Type Packages

We have developed a modified accumulated damage model that can be used to predict fatigue failure lives of solder joints in electronic devices. Our model calculates the fatigue failure life of solder on the basis of the damage that accumulates during crack propagation by using a finite element method and corrects for the dependence of element size on the calculated life by using the Hutchinson-Rice-Rosengren singularity theory. We predicted the fatigue lives of conventional and copper-core solder bump joints in ball-grid-array packages in thermal cycling tests. The good agreement between these predictions and experimental results indicates that our model can effectively predict fatigue failure life in solder joints.

Advanced Bump Structure for Improving the Board Level Characteristics of WLCSP

In this study, to increase solder joint reliability, we developed the epoxy reinforced bump structure surrounding the solder bump joint. The thermal-mechanical reliability of the epoxy reinforced solder bumped wafer level package was carried out during the thermal cycle and drop shock test of the package. The reliability of solder bump joint was evaluated by means of the thermal cycle in the range -40° to 125°. The experimental results revealed that the thermo-mechanical fatigue properties of the epoxy reinforced bump structure was better than that of the conventional solder bump structure. Epoxy reinforced bump structures improved the WLP characteristic life by at least 2 times. Also, the drop shock reliability of epoxy reinforced bump structure was enhanced 3 times better drop characteristic life than that of conventional single bump structure. The life time of epoxy reinforced solder bump joint was longer than that of the conventional WLCSP solder joint.

Residual Strain Measurement of Thin-Layer Cured Adhesives and Their Effects on Warpage in Electronic Packaging

Residual strains (stresses) of thin-layer adhesives are important and need be determined and further analyzed for better reliability design of the joints or bump joints in electronic or optoelectronic packaging. The purposes of this paper are to quantify residual strains of two adhesives: A (paste type) and B (film type) due to chemical shrinkage, stress relaxation, and thermal-loadings and moisture-loadings, and to investigate their effects on the warpage of die attachment assembly. At the beginning, the mechanical properties of the two adhesives in terms of temperatures are measured by dynamic mechanical analyzer (DMA) and thermomechanical analyzer (TMA). The residual strains are documented by testing fully cured adhesive/silicon bi-material plates under thermal and moisture loading using Twyman-Green (T/G) interferometry system associated with Timoshenko's bi-material theory and finite element method (FEM). Furthermore, the warpage of silicon/adhesive/Cu tri-material plates (similar to die attachment assembly) with both adhesives under thermal and moisture loading are also investigated by T/G experiments and confirmed by Suhir's solution and FEM results. For adhesive-A, the results of the bi-material plate suggest that the residual strains are only induced by mismatch of the coefficients of thermal expansion during thermal loading, rather than other factors, right after the fully cured adhesive cooling down to room temperature. On the other hand, for adhesive-B, it was found that the additional residual strain of this film adhesive caused by chemical shrinkage plus stress relaxation, is about 2.26 ? 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , which accounts for 85% of thermal-residual strains in the bi-material plate from curing temperature cooling down to room temperature. Experimental results also indicated that moisture-absorption expansion of the both adhesives is the major cause of decreasing warpage for the bi-material plates at 29?C/55% RH, other than stress relaxation. In contrast to the results of the bi-material plate, the warpages of the tri-material plates are found to be insensitive to the moisture-absorption, chemical, and thermal strains of adhesives, but not to elastic moduli of adhesives, due to their relatively thin-layer and compliant nature. This paper has successfully laid down an approach for determining residual strain of thin-layer adhesive and provided information about their effect on warpage of die attachment assembly.

Solder joint reliability in flip chip package with surface treatment of ENIG under thermal shock test

This study investigated the microstructural evolution and evaluated the thermo-mechanical reliability of a Sn-3.0Ag-0.5Cu (in wt.%) flip chip package during a thermal shock test. The reliability of the flip chip bonded packages was evaluated by means of the thermal shock in the temperature range of 233 K to 398 K. After 250 thermal shock cycles, cracks finally occurred at the corner solder bump joint on the chip side interfacial regions. In that, the crack initiated at the solder region near the intermetallic compound (IMC) layers. For the interpretation of the failure mechanism of the package, finite element analyses were conducted. From the finite element analysis or computational simulation result, the distribution of the plastic work in the corner solder bump was found to be most considerable. This means that the corner solder bump has the highest potential for first crack initiation and growth, because the thermo-mechanical failure of the solder joints is mainly caused by the accumulation of the plastic work. This matched well with the experimental results.

Effect of the Formation of the Intermetallic Compounds between a Tin Bump and an Electroplated Copper Thin Film on both the Mechanical and Electrical Properties of the Jointed Structures

The mechanical and electrical reliabilities of fine bumps with diameters and heights on the order of scores of microns were studied, considering the growth of the intermetallic compound (IMC) at the interface between a tin bump and a copper thin-film interconnection. It was found that an increase in the thickness of the IMC changed the stress and strain fields around the interface significantly, and thus, changed the fracture mode from a fatigue crack of the solder to a fatigue crack of the copper interconnection or to delamination between the IMC and the copper interconnection. This is because the mechanical properties of the grown IMC differ from those of copper and tin and that a large number of Kirkendall voids appeared around the interface. In addition, the resistance of the bumps increased dramatically with the increment of the IMC layer because of the growth of the Kirkendall voids. Therefore, it is very important to minimize the growth of the IMC in order to assure the reliability of the bump joint structures.

エリアアレイ型フリップチップ実装構造 : バンプ接続部状態の非破壊検査システム(&lt;小特集&gt;電子機器の熱・機械信頼性と機械工学)

エリアアレイ型フリップチップ実装構造 : バンプ接続部状態の非破壊検査システム(&lt;小特集&gt;電子機器の熱・機械信頼性と機械工学)

Effect of Copper-Tin Intermetallic Compound on Reliability of Fine Bump Joint Structures

Mechanical and electrical reliability of fine bumps with diameter and height of tens of μm was studied considering the growth of the intermetallic compound (IMC) at the interface between a bump and a copper thin-film interconnection. It was found that the increase of the thickness of the IMC change the stress and strain field around the interface significantly, and thus, the fracture mode from the fatigue crack of solder to fatigue crack of the copper interconnection or delamination between the IMC and the copper interconnection. This is because that the mechanical properties of the grown IMC differ from those of copper and tin and that a large amount of Kirkendall voids appeared around the interface. In addition, the resistance of the bumps increased drastically with the increment of the thickness of the IMC layer because of the growth of Kirkendall voids. Therefore, it is very important to minimize the growth of the IMC to assure the reliability of the bump joint structures.

Transient Stress Distributions in NCF-Bonded COG Packages due to Moisture Diffusion

The nonconductive film (NCF) adhesives have potentials to replace the anisotropic conductive film (ACF) adhesive in the chip-on-glass (COG) or other packages in liquid crystal displays (LCDs) due to their feasible features of finer bump pitch and cost reduction. Prior to applying the NCF to the COG packages, reliability issues, such as interfacial delamination and increase of bump contact resistance under thermal and moisture loads, have to be overcome. The objective of this paper is to investigate the effect of moisture ingression on stress field of the COG packages with NCF bonding. The coefficients of moisture diffusion and the hygro-strains of the NCF adhesive have been determined by an innovative approach of measuring the out-of-plane deformation of the bimaterial specimens during moisture absorption at the condition of 30degC/85%RH using Twyman-Green interferometry, associated with a finite element analysis and bimaterial theory. In this study, the results show that the average of the moisture diffusion coefficients and saturated hygro-strains of the NCF under 30degC/85%RH are 1.09 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /s and 1.51 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , respectively. After being validated by the diffusion theory, the moisture- transient finite element analysis reveals that the moisture absorption of the COG package under 30degC/85%RH is nearly saturated after 1000 h. It is also found that there are large tensile stresses at pad corner and mediate ones across bump joint, and these tensile stresses gradually increase with moisture absorption and up to the maximum at the state of moisture saturation. Through the parametric study by the validated finite element model, the results show that the tensile bump-joint and interfacial stresses increase nonlinearly with the NCF elastic modulus and linearly with the saturated moisture-induced strain (SMIS) of the NCFs. Furthermore, the COG package with polyimide bumps is found to have lower moisture-induced tensile stresses than that with gold bumps. It is further shown that the tensile stresses from the longitudinal-section and transverse-section models are similar only with a few percent difference in values. It can be concluded that the stress states of the NCF-bonded COG packages induced by transient moisture ingression have been fully addressed through experimental, theoretical and numerical approaches in this study.

Interfacial Reaction of Electroless Ni-P Plating with Sn-3.5Ag (-Co) Solder

The reaction between Sn-Ag (-Co) solder and electroless Ni-P plating was investigated in order to clarify the effect of the addition of Co to Sn-Ag solder on the formation of intermetallic compound (IMC) at the interface and the joint strength at the interface. Sn-Ag-Co solder was specially prepared. The results show that there is little effect of the addition of Co to the Sn-Ag solder on the IMC formation and the thickness of the IMC at the interface. For the pull strength of the solder bump joint, the addition of Co to the solder didn’t strongly affect the pull strength of the solder joints, but it affected the fracture mode of the solder joints.

1204 めっき錫バンプと銅薄膜配線間金属間化合物の機械特性(S05-1 ナノ・マイクロ材料の強度・信頼性(1)銅薄膜の強度物性,21世紀地球環境革命の機械工学:人・マイクロナノ・エネルギー・環境)

Residual stress in the bump joint structures that consist of copper thin films and lead-free solder bumps with intermetallic compounds(IMC) between them was analyzed by using a finite element method as a function of the thickness of the IMC. It was found that the stress and strain fields around the bump/interconnection changed dramatically depending on the thickness of the intermetallic compound.

Bump Formation and Flip Chip Processes for RF System-on-Packages

For flip-chip process of RF system-on-packages(SOP), double bump bonding processes were investigated. Sn-Ag and Sn solder joints were formed by the reflowed double bumping process, and Sn/In/Sn bump joints were fabricated by the non-reflowed double bump bonding process. The height-to-size ratios of 0.78 and 0.65 were obtained for the reflowed double bumping and the non-reflowed bumping, respectively. Average contact resistance of the reflowed Sn-Ag and Sn solder joints was about 13m/ which was much lower than 24~33m/ of the non-reflowed Sn/In/Sn bump joints. The reflowed solder double bumping method is more suitable for flip-chip process of RF-SOP than the non-reflowed double bump bonding.

Electrical Characteristics of the Three-Dimensional Interconnection Structure for the Chip Stack Package with Cu through Vias

A chip stack specimen of a three-dimensional (3-D) interconnection structure with Cu vias of 75-μm diameter, 90-μm height, and 150-μm pitch was successfully fabricated using via hole formation with deep reactive ion etching (RIE), Cu via filling with pulse-reverse pulse electroplating, Si thinning, Cu/Sn bump formation, and flip-chip bonding. The contact resistance of a Cu/Sn bump joint and Cu via resistance could be determined from the slope of the daisy chain resistance versus the number of bump joints of the flip-chip specimen containing Cu vias. When the flip chip was bonded at 270°C for 2 min, the contact resistance of a Cu/Sn bump joint of 100-μm diameter was 6.74 mΩ, and the resistance of a Cu via of 75-μm diameter and 90-μm height was 2.31 mΩ. As the power transmission characteristics of the Cu through via, the S21 parameter was measured up to 20 GHz.

Fabrication and Evaluation of 3D Packages with Through Hole Via

ABSTRACTSystem in package (SiP) is a superb candidate to enhance the area efficiency and performance of electronic packaging. Here, recent work on stacked chip type 3D SiP with vertically interconnected through hole vias are reported. The process includes; formation of 50um-diameter via holes, conformal deposition of SiO2 dielectric layer, deposition of Ta and Cu barrier layers, via filling by Cu electroplating, Cu/Sn bump formation for multi-chip stacking, and finally chip-to-PCB bonding using Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3D SiP stacked up to 10 layers was successfully fabricated.A high frequency electrical model of the through hole via was proposed and the model parameters were extracted from measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. Contact resistances of Cu via and bump joint were presented.

Aging treatment characteristics of solder bump joint for high reliability optical module

The joint strength and fracture surfaces of Sn–37 mass% Pb and Au stud bumps for photo diode packages after isothermal aging testing were studied experimentally. Al/Au stud bumps and Cu/Sn–37 mass% Pb solders were adopted, and aged for up to 900 h to analyze the effect of intermetallic compound (IMC). The joint strength decreased with aging time. The diffraction patterns of Cu 6Sn 5, scallop-shaped IMCs, and planar-shaped Cu 3Sn were characterized using transmission electron microscopy (TEM). The formation of Kirkendall voids and the growth of IMCs at the solder were found to be a possible mechanism for joint strength reduction.