Electrical Characteristics of the Three-Dimensional Interconnection Structure for the Chip Stack Package with Cu through Vias

Abstract

A chip stack specimen of a three-dimensional (3-D) interconnection structure with Cu vias of 75-μm diameter, 90-μm height, and 150-μm pitch was successfully fabricated using via hole formation with deep reactive ion etching (RIE), Cu via filling with pulse-reverse pulse electroplating, Si thinning, Cu/Sn bump formation, and flip-chip bonding. The contact resistance of a Cu/Sn bump joint and Cu via resistance could be determined from the slope of the daisy chain resistance versus the number of bump joints of the flip-chip specimen containing Cu vias. When the flip chip was bonded at 270°C for 2 min, the contact resistance of a Cu/Sn bump joint of 100-μm diameter was 6.74 mΩ, and the resistance of a Cu via of 75-μm diameter and 90-μm height was 2.31 mΩ. As the power transmission characteristics of the Cu through via, the S21 parameter was measured up to 20 GHz.