Bulk Trap Density Research Articles

Temperature Dependence of Trap Density Distribution in Poly(3-hexylthiophene) and 1-(3-Methoxycarbonyl)-propyl-1-phenyl-(6,6)C61 Based Blending Films under Illumination

Measurements of the current density–voltage (J–V) characteristics of a poly(3-hexylthiophene) (P3HT) and 1-(3-methoxycarbonyl)-propyl-1-phenyl-(6,6)C61 (PCBM)-based electron-dominated device as functions of temperature were carried out. A transport transition from three-dimensional variable range hopping (VRH) to space-charge-limited current (SCLC) with an exponential distribution of traps (filled and unfilled) was observed. The bulk trap density, about 1018 cm-3, of the P3HT:PCBM blend film was evaluated by the differential method. A shift to the lowest unoccupied molecular orbital (LUMO) state of PCBM for trap density distribution was observed owing to the temperature dependence of the Fermi level of PCBM materials. It is supposed that the Fermi level of PCBM materials is strongly temperature-dependent similarly to that of amorphous silicon semiconductors.

Temperature Dependence of Trap Density Distribution in Poly(3-hexylthiophene) and 1-(3-Methoxycarbonyl)-propyl-1-phenyl-(6,6)C61 Based Blending Films under Illumination

Measurements of the current density–voltage (J–V) characteristics of a poly(3-hexylthiophene) (P3HT) and 1-(3-methoxycarbonyl)-propyl-1-phenyl-(6,6)C61 (PCBM)-based electron-dominated device as functions of temperature were carried out. A transport transition from three-dimensional variable range hopping (VRH) to space-charge-limited current (SCLC) with an exponential distribution of traps (filled and unfilled) was observed. The bulk trap density, about 1018 cm-3, of the P3HT:PCBM blend film was evaluated by the differential method. A shift to the lowest unoccupied molecular orbital (LUMO) state of PCBM for trap density distribution was observed owing to the temperature dependence of the Fermi level of PCBM materials. It is supposed that the Fermi level of PCBM materials is strongly temperature-dependent similarly to that of amorphous silicon semiconductors.

Annealing temperature dependence on the positive bias stability of IGZO thin-film transistors

The threshold voltage shift (Δ V th) under positive-voltage bias stress (PBS) of InGaZnO (IGZO) thin-film transistors (TFTs) annealed at different temperatures in air was investigated. The dramatic degradation of the electrical performance was observed at the sample that was annealed at 700°C. The degradation of the saturation mobility (μsat) resulted from the diffusion of indium atoms into the interface of the IGZO/gate insulator after crystallization, and the degradation of the subthreshold slope (S-factor) was due to the increase in the interfacial and bulk trap density. In spite of the degradation of the electrical performance of the sample that was annealed at 700°C, it showed a smaller Δ V th under PBS conditions for 104 s than the samples that were annealed at 500°C, which is attributed to the nanocrystal-embedded structure. The sample that was annealed at 600°C showed the best performance and the smallest Δ V th among the fabricated samples with a μsat of 9.38 cm2/V s, an S-factor of 0.46 V/decade, and a Δ V th of 0.009 V, which is due to the passivation of the defects by high thermal annealing without structural change.

Interface Trap Characterization of a 5.8-$\hbox{\rm{ \AA}}$ EOT p-MOSFET Using High-Frequency On-Chip Ring Oscillator Charge Pumping Technique

Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.

Paraffin wax passivation layer improvements in electrical characteristics of bottom gate amorphous indium–gallium–zinc oxide thin-film transistors

In this research, paraffin wax is employed as the passivation layer of the bottom gate amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs), and it is formed by sol–gel process in the atmosphere. The high yield and low cost passivation layer of sol–gel process technology has attracted much attention for current flat-panel-display manufacturing. Comparing with passivation-free a-IGZO TFTs, passivated devices exhibit a superior stability against positive gate bias stress in different ambient gas, demonstrating that paraffin wax shows gas-resisting characteristics for a-IGZO TFTs application. Furthermore, light-induced stretch-out phenomenon for paraffin wax passivated device is suppressed. This superior stability of the passivated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities.

Effects of aluminum doping on lanthanum oxide gate dielectric films

This work reports a novel method for improving the electrical properties of lanthanum gate oxide (La2O3) by using aluminum doping and rapid thermal annealing (RTA) techniques. In the bulk of the Al-doped La2O3 film together with 600 °C RTA, we found that the aluminum atoms were incorporated into the oxide network and the film was transformed into lanthanum aluminate complex oxide. At the interface, a thin Al2O3 layer was formed. This interfacial Al2O3 layer suppressed the out-diffusion of substrate Si, the formation of interfacial silicate layer and silicide bonds. These effects resulted in a significant reduction on the bulk and interface trap densities and hence the gate leakage current.

Bias and temperature dependent charge transport in solution-processed small molecular mixed single layer organic light emitting devices

The authors investigate bias and temperature dependent current density-voltage (J-V) characteristics in solution-processed small molecular mixed single layer organic light emitting devices using Au/MoO3 as hole and Al as electron injection electrode. Hole and electron injections are primarily ascribed to the Schottky thermionic emission mechanism. However, at high field of >9×105 V cm−1, hole transport is found to be bulk trapped corresponding to space charge limited current with an exponential distribution of traps. The bulk trap density, about 1018 cm−3 in mixed organic layer, is evaluated by the differential method.

Charge Trapping and Detrapping Behavior of Fluorinated $\hbox{HfO}_{2}/\hbox{SiON}$ Gate Stacked nMOSFET

The charge trapping and detrapping characteristics of the fluorinated hafnium oxide/oxynitride (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiON) gate stack are investigated. Although incorporation of fluorine in the bulk stack had been proven to eliminate both bulk and interface trap densities due to Hf-F and Si-F bond formation, respectively, the effective trapping barrier of the device with fluorine incorporation (1.29 eV) is deeper than without fluorine incorporation (1.13 eV), indicating that the detrapping ability of the fluorinated devices may limit future fluorine process applications.

Effect of Trap Profile on Device Characteristics of Metal–Oxide–Semiconductor Field Effect Transistors with Hafnium-Based Dielectrics

The trap properties and performance of metal–oxide–semiconductor field effect transistors (MOSFETs) with either a HfSiO or HfO2 dielectric were determined using single-pulse Id–Vg and charge pumping measurements. The HfSiO dielectric shows a lower bulk trap density and a lower interface trap density than the HfO2 dielectric. Particularly, the trap depth profile as a function of distance from the Si/SiOx interface, which is obtained using frequency-dependent charge pumping measurements, shows a marked reduction in trap density in the HfSiO dielectric, unlike in the HfO2 dielectric. This significant reduction in trap density close to the Si/SiOx interface can contribute to the improvement in the carrier mobility of MOSFETs with a HfSiO dielectric.

The Effect of Density-of-State on the Temperature and Gate Bias-Induced Instability of InGaZnO Thin Film Transistors

The impact of a gate insulator (GI) material on the device instability of InGaZnO (IGZO) thin film transistors (TFTs) was investigated. The IGZO TFTs with GI showed consistently better stability against the applied temperature stress and positive/negative gate bias stress than their counterparts with GI. This superior stability of the -gated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities. Based on the Meyer–Neldel rule, the total DOS energy distribution for both devices was extracted and compared, which can explain the experimental observation.

Effect of illumination and annealing on electrical properties of indium tin oxide/poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate)/poly(3-hexylthiophene)/Al device

We have studied the modification of electrical properties in poly(3-hexylthiophene) (P3HT) thin film by means of illumination and annealing. The hole mobility of P3HT was monitored by impedance spectroscopy and the density of localized states in the band gap near the Fermi level was calculated using the step-by-step method based on the space-charge-limited-current model. With the illumination, we found that the bulk trap density increased from 2.51 to 2.85×1016 cm−3 eV−1 and the hole mobility of P3HT decreased from 1.88×10−4 cm2 V−1 s−1 to 4.22×10−5 cm2 V−1 s−1. With the annealing at 70 °C for 30 min, it is found that the mobility then partially recovers to 1.18×10−4 cm2 V−1 s−1.

Effects of fluorine incorporation into HfO2 gate dielectrics on InP and In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors

In this work, the effects of fluorine (F) incorporation on electrical characteristics of HfO2/InP and HfO2/In0.53Ga0.47As gate stack are presented. F had been introduced into HfO2 gate dielectric by postgate CF4 plasma treatment, which was confirmed by x-ray photoelectron spectroscopy analysis and a secondary ion mass spectrometry technique. Compared to the control sample, fluorinated samples had great improvements in subthreshold swing, hysteresis, the normalized extrinsic transconductance, and the normalized drain current. These improvements can be attributed to the reduction in fixed charge in the HfO2 bulk and less interface trap density at the HfO2/III–V interface.

Experimental Investigation of Effect of Channel Doping Concentration on Random Telegraph Signal Noise

Random telegraph signal (RTS) noise has become one of the most important problems in the continuous scaling down of field-effect transistors (FETs). In this study, we investigate experimentally the relationship between RTS amplitude and channel doping concentration (NA), which is a key parameter related to threshold voltage adjustment and short-channel effects, in 393,216 n-type FETs by a high-speed measurement method. We demonstrate that NA has a significant effect on RTS amplitude even at approximately the same interface and bulk trap densities of the gate insulator films, which are evaluated by the charge pumping method, by the quasi-static capacitance–voltage method, and on the basis of 1/f noise characteristics. An increase in RTS amplitude may arise from a more advanced channel nonuniformity as NA increases.

Correlation Between the $V_{\rm th}$ Adjustment of nMOSFETs With HfSiO Gate Oxide and the Energy Profile of the Bulk Trap Density

The change of the energy profile of the initially present HfSiO defects in nMOSFETs after Vth adjustment by As and Ar implantations is investigated. A fundamental correlation between the density of energetically deep traps and the initial Vth is revealed, suggesting that the negative bulk charge in HfSiO controls the Vth.

Effect of fluorinated silicate glass passivation layer on electrical characteristics and dielectric reliabilities for the HfO 2/SiON gate stacked nMOSFET

The superior characteristics of the fluorinated hafnium oxide/oxynitride (HfO 2/SiON) gate dielectric are investigated comprehensively. Fluorine is incorporated into the gate dielectric through fluorinated silicate glass (FSG) passivation layer to form fluorinated HfO 2/SiON dielectric. Fluorine incorporation has been proven to eliminate both bulk and interface trap densities due to Hf–F and Si–F bonds formation, which can strongly reduce trap generation as well as trap-assisted tunneling during subsequently constant voltage stress, and results in improved electrical characteristics and dielectric reliabilities. The results clearly indicate that the fluorinated HfO 2/SiON gate dielectric using FSG passivation layer becomes a feasible technology for future ultrathin gate dielectrics applications.

Improved performance and reliability for metal-oxide-semiconductor field-effect-transistor with fluorinated silicate glass passivation layer

The superior characteristics of the fluorinated HfO2/SiON gate dielectric are investigated comprehensively. Fluorine is incorporated into the gate dielectric through fluorinated silicate glass (FSG) passivation layer to form fluorinated HfO2/SiON dielectric. Fluorine incorporation has been proved to eliminate both bulk and interface trap densities due to Hf–F and Si–F bonds formation, which can strongly reduce trap generation as well as trap-assisted tunneling during subsequently constant voltage stress, and results in improved electrical characteristics and dielectric reliabilities. The results clearly indicate that the fluorinated HfO2/SiON gate dielectric using FSG passivation layer becomes a feasible technology for future ultrathin gate dielectric applications.

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.

Solution-processed flexible organic transistors showing very-low subthreshold slope with a bilayer polymeric dielectric on plastic

We demonstrate low-voltage, solution-processed organic transistors on rough plastic substrates with a carrier mobility over 0.2 cm2/V s, a turn-on voltage of near 0 V, and a record low subthreshold slope of ∼80 mV/decade in ambient conditions. These exceptional characteristics are attributed to (1) a device stacking architecture with a conducting polymeric gate and a double layered dielectric composed of low-temperature cross-linked poly(4-vinylphenol), (2) a low interface trap density achieved by modifying the dielectric surface with a phenyl-terminated self-assembled monolayer from 4-phenylbutyltrichlorosilane, and (3) controlled crystallization of a small-molecule organic semiconductor film with favorable charge transport microstructure and a low bulk trap density as deposited by an optimized solution-shearing process. The device performance under different operating voltages was also examined and discussed.

Experimental evidence of suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation

Experimental evidence of suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation is provided by using modified charge-pumping (CP) techniques. The original distribution of interface traps and bulk traps of pure HfO 2 and HfO 2/LaOx dielectric stack are extracted and compared by CP techniques. It is found that devices with HfO 2/LaOx dielectric stack have higher interface trap but lower bulk trap density than those with pure HfO 2. Especially, device with HfO 2/LaOx dielectric stack is highly resistant to constant voltage stress, which can be attributed to the suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation.

Investigation of Bulk Traps Enhanced Gate-Induced Leakage Current in Hf-Based MOSFETs

A comprehensive study on bulk trap enhanced gate-induced drain leakage (BTE-GIDL) currents in high-MOSFETs is reported in this letter. The dependence of GIDL for various parameters, including the effect of Zr concentration in , high-film thickness, and electrical stress is investigated. The incorporation of Zr into reduces GIDL. GIDL was also found to reduce with thinner high-film. In addition, a significant correlation between GIDL and bulk trap density in high- film is established. Possible mechanisms were provided to explain the role of bulk trapping in BTE-GIDL, observed in high-devices.