Bulk Silicon CMOS Research Articles

MEMS Thermocouple Sensor Based on 4H-Silicon-Carbide-On-Insulator (4H-SiCOI)

With the high thermal conductivity and breakdown voltage, silicon carbide (SiC) has been treated as a promising material to work in harsh environment especially high temperature. However, due to its chemical inertness and wide band-gap, it is difficult to achieve the ion implantation, etching and good ohmic contact. In this study, silicon carbide on insulator (4H-SiCOI) is applied to fabricate MEMS thermocouple sensor, which can simultaneously compatible with bulk silicon CMOS process. The stress and temperature distribution of the sensor was simulated by COMSOL. After optimized the process parameters, the sensor based on 4H-SiCOI was successfully fabricated. Preliminary test results demonstrated the sensor shows good sensitivity about 1.44 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{-{8}}\,\,{V}{m}^{{{2}}}/{W}$ </tex-math></inline-formula> and response time of 3.24ms, which also keeps good linearity and repeatability. This sensor can satisfy the needs of fast and high precision heat detection and our work may have a meaningful reference value for other same type SiC-based MEMS thermocouple sensor design and preparation.

Single Event Latch-up Effect of 130 nm Bulk Silicon CMOS Device Irradiated by Pulsed Laser

基于130nm体硅CMOS工艺，设计了具有不同阱/衬底接触与MOS管有源区间距、NMOS有源区与PMOS有源区间距的反相器链，利用脉冲激光试验开展了不同设计和不同工作电压下CMOS电路的单粒子闩锁效应敏感性研究.结果表明，随着阱/衬底接触与MOS管有源区的间距减小，以及NMOS与PMOS有源区间距的增大，电路抗SEL效应能力增强.此外，不同工作电压下电路的SEL效应规律表明，电压越大，反相器电路的SEL电流越大，且随着阱/衬底接触与MOS管有源区间距的减小以及NMOS与PMOS有源区间距的增大，电路出现SEL效应的开启电压增大.结合CMOS中寄生结构和单粒子闩锁效应触发机制，分析了相关因素影响电路单粒子闩锁效应敏感性的内在机制.

Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process

In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.

Examining the Thermal Stress Effect of Electromagnetic Susceptibility of Automotive CAN Controller

CAN controllers are responsible for the processing and transmission of CAN signals, which render them indispensable electronic devices in automotive cyber-physical systems. SJA1000T is one of the most common CAN communication chips which can be implemented through the use of bulk silicon CMOS technology. A susceptibility test platform is built based on the direct power injection method following IEC62132-4 to explore the electromagnetic susceptibility characteristics and the effects of thermal stress on CAN controller. Test results show that the susceptibility threshold curve is corresponded directly to frequency and temperature. The influence of thermal stress on the input and output characteristics of MOSFET is simulated and analyzed to verify the anti-interference ability and reduced reliability of the chip in a high temperature environment.

(Invited) Thin Film Transistor Technologies: Implementing Research Results in Higher Education to Prepare the Emerging Multidisciplinary Connected Objects

Thin film technologies, particularly thin-film transistors, have been the backbone of large-area electronics for decades, primarily for display applications such as flat panel displays. These devices were mainly manufactured on glass substrate. The processes have therefore been considered as a low temperature technology compared to bulk silicon CMOS technology processes. However, due to the huge development of integrated electronics in parallel driven by a steady size reduction to cope with Moore’s law, the CMOS thermal budget has been drastically lowered, which in-fine brought both technologies to comparable processing temperatures. Today, flexible plastics is used as a substrate. In addition, as the physical limitation of dimensions becomes close to the size of one monolayer, integration has shifted to the third dimension by stacking circuit substrates and other physical or electrical functions (more than Moore). As a result, electrical circuits become three-dimensional and increasingly involve thin-film technologies in new systems-on-a-chip (SOC) or systems-in-package (SiP). This trend allows creating new objects that are gathering several functions with communication capabilities, i.e. connected smart objects. The connected objects can contain sensors, actuators, signal processing circuits but also displays, energy harvesting device. In other words, they combine large area electronics and CMOS ones. The main advantage of the thin film technologies is also offering the possibilities to process multidisciplinary objects such as MEMS (micro-electrical-mechanical systems), BioMEMS for biological application, Optoelectronic systems, for example. The spectrum of combination is increasingly wider and hence addresses a large field of applications to many societal issues such as health, environment, security, transport, energy, communications, etc. The research activities for the development of thin film transistors technologies is mature even if progress still remain to reduce the power consumption and/or to improve the electrical characteristics, the sensitivity and the reliability. Important research efforts were devoted to improve the quality of the semiconductor materials, to adapt the thin layer deposition techniques to the nature of the substrate, to improve the interfaces at the border of the active zones, to minimize the density of defects despite a low temperature budget by involving several techniques of crystallization and/or depositions, by and also changing the architecture of the elementary device, and the design of the circuits, …. A large variety of skills has to be made available in order to keep the pace of this technology development. This means the training of skilled technicians, engineers, and researchers bearing PhD degrees. In a context of digital society, developing the skills of the graduate students is strongly linked to the knowledge and the associated know-how. The initial education of engineers and researchers must contain several practical training based on the outcome of research activity allowing an awareness of the students to the new challenge. Practical training to develop advanced know-how skills might be hindered by the cost of the equipment and the associated running expenses. To meet this challenge, the French CNFM (National coordination for Education in Microelectronics and Nanotechnologies) network strategy is sharing the fabrication facilities such as the cleanroom and the design tools. In this strategy, twelve microelectronics centers were created in the early 80’s, seven of them having cleanrooms opened to initial education, and lifelong learning. Today, these centers are organized in a network, recognized by the Ministry of Higher Education that financially supports at least partially, the common activities. In this network two important industrial partners are members of the CNFM BoD. Several CNFM centers have activities in the thin film technologies, mainly Rennes, Grenoble, Lille and Bordeaux centers. They have developed practicals for students that include amorphous and polycrystalline silicon thin film transistors technologies, and more recently organic semiconductors for photovoltaic and optoelectronics applications, graphene thin film devices, or insulator ultrathin films for memories (such as Metal-Insulator-Metal or MIM), but also sensors and actuators involving suspended gate thin film transistors, suspended membranes, nanowires or cantilevers, piezoelectric films, etc. After a presentation of the evolution of the thin film technologies thanks to the research activities, and of the societal issues for applications that include the development of connected objects, the presentation highlights the set-up of training covering the different aspects of the thin film technologies in order to train the graduate students for the future digital and connected society. This transfer from the research activities towards the Higher Education is the main mission of the University world.

Low-Loss 800-V Lateral IGBT in Bulk Si Technology Using a Floating Electrode

An 800V rated lateral insulated-gate bipolar transistor (LIGBT) for high frequency and low-cost applications is proposed. This LIGBT features a new method of adjusting the bipolar gain by using floating N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> regions connected by a floating electrode in front of the P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> collector. This floating structure lowers the injection efficiency at the collector side of the device, resulting in a very significant decrease in turn-off time and substantially lower turn-off losses. The device was fabricated in a 0.5μm bulk silicon CMOS technology at a commercial foundry without additional processing steps or process optimisation. Tests on fabricated devices showed equivalent Rdson below 70 mQ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 125 °C with switching times as low as 250 ns at 125 °C. The novel LIGBT device showed avalanche capability and low gate capacitance and was used for the first time, in an AC/DC converter operating at 200 kHz allowing significant improvements in performance, compactness, and reduced component count.

Predictions for proton and heavy ions induced SEUs in 65 nm SRAMs

We report on irradiation induced single event upset (SEU) by high-energy protons and heavy ions. The experiments were performed at the Paul Scherer Institute, and heavy ions at the SEE irradiating Facility on the HI-13 Tandem Accelerator in China's Institute of Atomic Energy, Beijing and the Heavy Ion Research Facility in Lanzhou in the Institute of Modern Physics, Chinese Academy of Sciences. The results of proton and heavy ions induced (SEU) in 65 nm bulk silicon CMOS SRAMS are discussed and the prediction on several typical orbits are presented.

Enabling Bulk Silicon CMOS Technology for Integration, Reliability, and Extended Lifetime at High Temperature

Silicon Space Technology has developed a commercial bulk CMOS process technology, HardSIL™, which allows optimization of performance, power, and lifetime at high temperatures. A method for preventing latchup, originally developed for use in the space radiation environment, is presently applied to terrestrial high-temperature environments. With the possibility of latchup eliminated in scaled CMOS technology nodes, further designs specific for high-temperature environments have proceeded well. This novel technology has been applied to our 18Mb synchronous burst SBRAM and our ARM® Cortex® M0 microcontroller, and in two CMOS processes at the 130nm technology node (Texas Instruments and GLOBALFOUNDRIES). Extensive temperature testing on these parts demonstrates that bulk silicon CMOS technology has a practical temperature limit of 250°C or higher. Both the microcontroller and the SBRAM have been tested with clock rates up to 70MHz and at temperatures up to 260°C. Both parts have performed without error and without latchup under these conditions, and with low operating current and low leakage current. For example, the 130 million-transistor 18Mb SBRAM has average core leakage current of 580mA at 250°C and core voltage of 1.5V with test lots and simulations showing further reduction in leakage in the next, terrestrial version of this part. In addition, the 18Mb SBRAM is undergoing an endurance test at 250°C, presently at the 2500 hour milestone. Operation at temperatures beyond the present limit of the testing equipment (260°C) appears possible from extrapolation of current data. Integration levels of greater than 8 million gates on a bulk CMOS device would allow multi-core processors with large on-chip secondary caches. Additional DSP engines or other compute engines can be accommodated for processing high resolution three dimensional images in real time. This would provide substantial distributed processing in drilling or jet engine control. These system-on-chip (SOC) integration levels can substantially reduce mechanical failures in a subsystem by reducing the number of wire bonds from greater than 1000 connections to less than 100 connections. Integration of mixed-signal A/Ds and D/As as well as on-chip power management provides a path to further reduction in mechanical connections in a sub-system.

Latchup Immunity in High Temperature Bulk CMOS Devices

High density, low power 180nm and 130nm CMOS SRAMs have been manufactured on bulk silicon wafers using a modified CMOS commercial process that hardens the junction isolation and has demonstrated latchup immunity at temperatures &amp;gt;200°C. TCAD simulations confirmed by high temperature testing indicate that a latch up free performance of SRAMs manufactured on bulk silicon modified by the HardSIL™ technology will easily extrapolate to 250°C. These process modifications result in significantly more robust CMOS circuits making them more suitable for highly reliable operations in extreme environments – such as radiation and high temperature. The unique capability of HardSIL™ technology to enhance existing IC products has demonstrated excellent results with several commercial circuits. This new approach enables the conversion of commercial off the shelf (COTS) circuits to hardened hi-rel commercial circuits with dramatically improved survivability to either radiation or high temperatures. Latchup immunity has been demonstrated on two high-density bulk silicon CMOS SRAMs: a 16Mbit asynchronous SRAM manufactured at the 180nm design node and an 8Mbit dual port synchronous SRAM manufactured at 130nm. Both parts were produced in a high-volume, low-defect commercial CMOS fabrication facility in the USA. The SRAM parts were packaged in ceramic packages and characterized at temperatures ranging from 25°C to 225°C. Characterization data indicates both excellent static leakage and dynamic circuit performance for both SRAMs at these elevated temperatures. Device test structures designed with typical layout spacing rules were evaluated to quantify latchup and isolate the various leakage mechanisms. Detailed results for these test structures are presented and compared to the SRAMs using the modified HardSIL™ process.

Negative bias temperature instability induced single event transient pulse narrowing and broadening

The effect of negative bias temperature instability (NBTI) on a single event transient (SET) has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter; but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter. Based on this study, for the first time we propose that the impact of NBTI on a SET produced by the heavy ion hitting the NMOS has already been a significant reliability issue and should be of wide concern, and the radiation hardened design must consider the impact of NBTI on a SET.

Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process.

Improving the yield and reliability of the bulk-silicon HV-CMOS by adding a P-well

In this paper, a novel high-yield and high-reliability High Voltage CMOS (HV-CMOS) compatible with 0.6 μm rules standard Bulk-Silicon (BS) CMOS process was proposed. The detailed discussion on how to avoid the influence of the lithography misalignment of the High Voltage PMOS (HV-PMOS) was given. The detailed analysis on the validity of the added p-well to prevent the High Voltage Double-Diffusion NMOS (HV-DNMOS) from punching through was also suggested. The experimental results show the yields of the HV-PMOS and the HV-CMOS are more than 98% and 95%, respectively, which are due to adding the p-well to HV-PMOS for eliminating the influence of the lithography misalignment during etching the unwanted thick gate oxide film of the HV-PMOS and that to HV-DNMOS for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be well applied in high voltage driver ICs, etc.

Improving the yield and reliability of the bulk-silicon HV-CMOS by adding a P-well

In this paper, a novel high-yield and high-reliability High Voltage CMOS (HV-CMOS) compatible with 0.6 μm rules standard Bulk-Silicon (BS) CMOS process was proposed. The detailed discussion on how to avoid the influence of the lithography misalignment of the High Voltage PMOS (HV-PMOS) was given. The detailed analysis on the validity of the added p-well to prevent the High Voltage Double-Diffusion NMOS (HV-DNMOS) from punching through was also suggested. The experimental results show the yields of the HV-PMOS and the HV-CMOS are more than 98% and 95%, respectively, which are due to adding the p-well to HV-PMOS for eliminating the influence of the lithography misalignment during etching the unwanted thick gate oxide film of the HV-PMOS and that to HV-DNMOS for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be well applied in high voltage driver ICs, etc.

High-voltage power integrated circuit technology using bulk-silicon for plasma display panels data driver IC

In this paper, a novel high-voltage CMOS (HV-CMOS) structure and a compatible bulk-silicon (BS) CMOS process for color plasma display panel (PDP) data driver ICs have been proposed. The breakdown voltage and the current of the PDP data driver IC using this technology were 100 V and 42 mA, respectively. The rise and fall time of the new PDP data driver IC was 19 and 23 ns, respectively. The cost was also reduced by 20% by using the BS substrate material compared with the silicon-on-isolator (SOI) material.

FAR–FUTURE TRENDS IN SOI TECHNOLOGY: A GUESS

The horizon of the Silicon On Insulator (SOI) technology is explored based on the compilation of many expert viewpoints. An SOI panel was organized at WOFE'02 with the aim of 'guessing' the shape of SOI and its industrial place in 10 years from now. SOI is expected to gradually take the role of bulk-silicon CMOS, reach the final stages of the ITRS roadmap in microelectronics, and enter the nanoelectronics world. The debate exhaustively examined the strategic and critical aspects of SOI technology. Only a few issues were retained as serious challenges.

Silicon on sapphire CMOS for optoelectronic microsystems

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues.

Computer-aided performance assessment of fully depleted SOI CMOS VLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies. >

Low temperature CMOS-a brief review

Bulk silicon CMOS applications at cryogenic temperatures are considered. It is argued that device improvements obtained from exploiting the dependence of physical characteristics of silicon at low temperature are above and beyond those improvements obtained from the usual geometric scaling of device dimensions. As device geometries continue to shrink into the deep submicrometer regime, second-order effects begin to limit further increases in device speed from scaling alone. Temperature scaling provides an additional variable for system optimization. The gain in performance at cryogenic temperatures, however, is at the expense of inconvenience and additional cost for system refrigeration, and of increased susceptibility to hot carrier degradation. Optimizing CMOS technology and design for low-temperature applications can increase performance and reduce power dissipation without increasing hot carrier degradation. Reliability considerations and a brief review of available refrigeration systems are also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A comparison of fine-dimension silicon-on-sapphire and bulk-silicon complementary MOS devices and circuits

The fabrication of fine-dimension silicon-gate MOS devices on both silicon-on-sapphire and bulk-silicon substrates has made possible a direct comparison of the electrical characteristics of devices based on these technologies. The same CMOS test chip design was used in both cases and provided both n- and p-channel devices having gate dimensions ranging down to submicrometer levels. Extensive electrical evaluation of the resulting devices has enabled quantitative comparison of carrier mobilities, short- and narrow-channel threshold voltage shifts, punchthrough, and subthreshold characteristics for SOS and bulk-silicon technologies. The effect of epitaxial film thickness on these properties for SOS devices is also discussed. An anomalous narrow-channel threshold voltage shift effect is observed in SOS devices and explained in terms of parasitic device characteristics. The general conclusion based on the observations made is that short-and narow-channel effects in SOS devices are significantly less of a problem than in bulk silicon devices at these gate dimensions. The direct comparison of the dynamic performance of SOS and bulk CMOS circuits can be obscured, for example by differences in gate oxide thickness and threshold voltages. In this case, however, both gate oxide thickness and threshold voltages have been closely matched. This, together with the fact that the circuits were fabricated by the same processing facility using the same chip design, should increase the reliability of any comparison. The results have indicated that at 1-µm dimensions the propagation delay of SOS CMOS circuits is 60 percent lower than that of equivalent bulk-silicon CMOS circuits.

Technology Independent Device Modeling for Simulation of Integrated Circuits for FET Technologies

A novel approach to device modeling for circuit simulation of integrated circuits is presented. This approach is based on general nonlinear network models in tensor product spline representation. As a consequnce this device modeling approach is technology independent and automatable. Tensor product spline representations of nonlinear branch elements are particularly useful, since the controlling variables are typically directionally dominant and only low rank tensors are needed. The basic properties of splines are reviewed for circuit simulation applications. Device model generation, software implementation, user interfaces and the circuit simulation environment within SPICE are described in detail. Realistic comparisons with conventional device models are given. The approach has been applied to several integrated circuit technologies (1/2-μm silicon MESFET logic, 7-μm CMOS/SOS logic, and 5-μm metal gate bulk silicon CMOS logic). Device models and simulated circuit results are in all cases in excellent agreement with measured device and circuit characteristics. This novel device modeling approach is particularly suitable for circuit design in quickly changing technological environments and for submicron VLSI.