Bulk nMOSFET Research Articles

The Effect of Deep N+ Well on Single-Event Transient in 65 nm Triple-Well NMOSFET

In a triple-well NMOSFET, a deep n+ well (DNW) is buried in the substrate to isolate the substrate noise. The presence of this deep n+ well leads to changes in single-event transient effects compared to bulk NMOSFET. In space, a single cosmic particle can deposit enough charge in the sensitive volume of a semiconductor device to cause a potential change in the transient state, that is, a single-event transient (SET). In this study, a quantitative characterization of the effect of a DNW on a SET in a 65 nm triple-well NMOSFET was performed using heavy ion experiments. Compared with a bulk NMOSFET, the experimental data show that the percentages of average increase of a SET pulse width are 22% (at linear energy transfer (LET) = 37.4 MeV·cm2/mg) and 23% (at LET = 22.2 MeV·cm2/mg) in a triple-well NMOSFET. This study indicates that a triple-well NMOSFET is more sensitive to a SET, which means that it may not be appropriate for radiation hardened integrated circuit design compared with a bulk NMOSFET.

Parallel domain decomposition methods for a quantum-corrected drift–diffusion model for MOSFET devices

In this paper, we describe parallel domain decomposition methods based on the restricted additive Schwarz (RAS) method for a quantum-corrected drift–diffusion (QCDD) model for MOSFET devices. We have developed hybrid Message Passing Interface (MPI)/OpenMP parallelization algorithms of the QCDD system. For internode parallelization, two extensions of the RAS method are newly developed for the QCDD model. For intranode parallelization, we combine the conjugate gradient (CG) and BiCGSTAB procedures with a splitting-up operator method to realize parallelization of the incomplete factorization. The parallel numerical results for a three-dimensional Si bulk n-MOSFET on a multi-core NEC SX-ACE parallel computer are demonstrated. The intranode parallel numerical results are further evaluated on a many-core Cray XC40 parallel computer.

Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process has been fabricated by integration of polysilicon-filled trenches. We have simulated its electrical characteristics by using TCAD software and compared them with results obtained from electrical measurements. The threshold voltage and the subthreshold slope of the top gate have been extracted and we found a good accordance, for both parameters, between the measurements (VTH=0.59V, S=90mV/dec) and simulations (VTH=0.50V, S=92mV/dec). The surface channel effective mobility of this multi-gate MOSFET was extracted and evaluated with both effective length and surface. The studies revealed that mobility degraded towards smaller dimensions of the MOS channel. At last, the Si/SiO2 interface quality studies were carried out. We noticed that the injected donor traps have a larger influence on the current–voltage characteristics than acceptor-like traps. With its good electrical performances, this low-cost multi-gate MOSFET technology presents interesting perspective in CMOS image sensors and more generally in analog application taking benefit of the multi-threshold for example.

Extension of Planar Bulk n-Channel MOSFET Scaling With Oxygen Insertion Technology

An experimental and simulation study of short-channel planar bulk nMOSFET performance enhancement achieved with oxygen insertion technology is presented. The benefits of this technology for low-power digital logic circuits make it a promising evolutionary approach to extend bulk MOSFET scaling.

Drain-current variability in 45 nm bulk N-MOSFET with and without pocket-implants

In this work, the drain-current mismatch is characterized from linear to the saturation regime. Characterizations are performed for N-MOS transistors with and without pocket-implants. A general drain-current mismatch model for transistors without pocket-implants, valid for any operation region, is also presented. It has been shown that correlated mobility and threshold voltage fluctuations must be considered to qualitatively model the experimental results. A comparison between devices with and without pocket-implants is performed and an important drain-current mismatch enhancement in the latter case is reported and discussed.

Analytical Modeling of Source-to-Drain Tunneling in Nanoscale Silicon MOSFET

Sub-10-nm bulk n-MOSFET (metal-oxide-semiconductor field effect transistor) direct source-todrain tunneling current density using WentzelKrammers-Brillouin (WKB) transmission tunneling theory has been simulated. The dependence of the source-to-drain tunneling current on channel length and barrier height is examined. Inversion layer quantization, band-gap narrowing, and drain induced barrier lowering effects have been included in the model. It has been observed that the leakage current density increases severely below 4 nm channel lengths, thus putting a limit to the scaling down of the MOSFETs. The results match closely with the numerical results already reported in literatures.

(Invited) Impact of Stress and Defects on Advanced Junction Leakage

Comparison of relative strengths of different leakage mechanisms in stress-free vs stressed, defect-free vs full-of-defects, planar MOSFET vs FinFET is performed. First, all major junction leakage mechanisms are analyzed using numerical models in a stress-free and defect-free 30 nm planar bulk NMOSFET. Then, the impact of stress on silicon bandgap is described along with the appropriate modeling guidelines. The magnitude and the current flow patterns for different leakage mechanisms affected by mechanical stress and by crystal defects are systematically analyzed. Junction leakage increase of 30 times under 2 GPa compressive stress is expected according to both the models and the available measurements. Junction leakage increase ranges from 10 pA to 100 pA per trap depending on the particular trap location relative to the drain junction. Based on results of this analysis, suggestions are given for finding the best trade-offs in designing transistors with stress engineering and occasional defects.

Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET

A quantitative evaluation of the contributions of different sources of statistical variability, including the contribution from the polysilicon gate, is provided for a low-power bulk N-MOSFET corresponding to the 45-nm technology generation. This is based on a joint study including both experimental measurements and ldquoatomisticrdquo simulations on the same fully calibrated device. The position of the Fermi-level pinning in the polysilicon bandgap that takes place along grain boundaries was evaluated, and polysilicon-gate-granularity contribution was compared to the contributions of other variability sources. The simulation results indicate that random discrete dopants are still the dominant intrinsic source of statistical variability, while the role of polysilicon-gate granularity is highly dependent on Fermi-level pinning position and, consequently, on the structure of the polysilicon-gate material and its deposition and annealing conditions.

Analytical model for quantization on strained and unstrained bulk nMOSFET and its impact on quasi-ballistic current

This work presents a fully analytical model for the evaluation of quasi-ballistic transport in advanced bulk nMOS devices. Starting from the Lundstrom approach, an original analytical evaluation of energy levels advantageously replaces numerical time-consuming Poisson–Schrödinger simulations or usual analytical single subband approximations. This model allows an accurate estimation of quantum mechanical effects and their impact on quasi-ballistic performances. Based on an improved Airy method, it accounts for the non-linearity of the depletion potential, the wave function oxide penetration and a generalized concept of effective field. As it relies on subband structure, it can easily be extended to biaxially strained devices provided that the band modifications are known. Interest of strained channels is confirmed even on the base of ballistic or quasi-ballistic hypothesis. This model has been used for the evaluation of the “ballisticity” along the ITRS roadmap, showing for next generation devices a quasi-ballistic current slightly higher than that predicted with the usual drift diffusion and saturation velocity equations. However, as already reported, MOS devices still operate far from their ballistic limit down to HP45 nm node.

Effects of inversion layer quantization on channel profile engineering for nMOSFETs with 0.1 μm channel lengths

This paper presents a systematic theoretical investigation of the effects of inversion layer quantization on the performance of nMOSFET devices fabricated with different shapes of channel doping profiles. The bulk nMOSFET simulation structures of effective channel length near 0.1 μm were generated with gate oxide thickness of 3 nm. Abrupt- and graded-retrograde profiles with low surface and high substrate concentrations, and conventional step profiles with high surface and low substrate concentrations were used for channel doping. A hydrodynamic model for semiconductors was used to simulate various device characteristics with and without the quantum mechanical effects in the inversion layer of the devices. The simulation results indicate that the increase in the threshold voltage due to quantum mechanical effects in the inversion layer of the devices and the resulting degradation in the current drivability, drain-induced barrier lowering, and subthreshold slope depend on the shape of the channel doping profiles. The devices with retrograde channel doping profiles provide a superior control of the device performance and the shift in the device performance due to quantum mechanical effects than the devices with step channel doping profiles. It is shown that for nano-MOSFET devices, the impact of quantum mechanical effects and the variation in the device performance due to dopant fluctuations can be optimized by channel profile engineering. The paper, also, demonstrates the importance of QM effects for predictive device simulation.

High-gain lateral bipolar action in a MOSFET structure

A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25- mu m base width have been successfully fabricated in a p-well 0.25- mu m bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>