Abstract
Comparison of relative strengths of different leakage mechanisms in stress-free vs stressed, defect-free vs full-of-defects, planar MOSFET vs FinFET is performed. First, all major junction leakage mechanisms are analyzed using numerical models in a stress-free and defect-free 30 nm planar bulk NMOSFET. Then, the impact of stress on silicon bandgap is described along with the appropriate modeling guidelines. The magnitude and the current flow patterns for different leakage mechanisms affected by mechanical stress and by crystal defects are systematically analyzed. Junction leakage increase of 30 times under 2 GPa compressive stress is expected according to both the models and the available measurements. Junction leakage increase ranges from 10 pA to 100 pA per trap depending on the particular trap location relative to the drain junction. Based on results of this analysis, suggestions are given for finding the best trade-offs in designing transistors with stress engineering and occasional defects.
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