Bulk Microdefect Density Research Articles

The Role of Oxygen on Defects Formation during Advanced Silicon Process Technologies

Impact of oxygen in silicon substrates and the formation of oxide precipitates have been widely studied in the past because of the detrimental electrical recombination and its effect on yield [1,2]. The origin of interstitial oxygen (Oi) is not only limited to the substrate but also comes from the nature of the oxide that may be deposited on it [3]. Interstitial oxygen plays a direct role in the formation of bulk microdefects (BMDs) resulting from oxygen precipitation during low-temperature Front-End anneals at 650-800°C [4,5]. The latter are of interest for the mechanical robustness of substrates, contributing to the pinning of slip lines (SL) and for the reliability of devices thanks to an internal gettering effect, but can also be harmful by emitting dislocations when they are too numerous (> 1 x 1010 BMD.cm-3) [5, 8].In this paper, we have reviewed the different impacts of interstitial oxygen on silicon substrates during thermal annealing through 3 phenomena: (i) the influence of Oi on the reduction of the slip lines by the pinning effect, (ii) the formation of BMDs induced by Oi and their interactions with dopants during implantation processes, (iii) the BMDs limited formation in the specific case of high resistivity (HR) silicon substrates. We focused on standard and high resistivity silicon substrates obtained by Czochralski (CZ) method, used in advanced technologies for various applications (digital, bipolar, power, photonic, etc.).To highlight the impact of interstitial oxygen, firstly on the mechanical properties of substrates, we studied the same p-type silicon substrates with two ranges of Oi concentration (5.33 x 1017 and 7.23 x 1017 at.cm-3), both annealed by furnace oxidation below 1000°C and N2 annealing above 1000°C. Figure 1 clearly shows the effect of a minor difference in Oi concentration on the number of slip lines detected by Pattern Wafer Geometry (PWG) measurements (Figure 2). Despite extrinsic process parameters to consider in the occurrence of slip lines, these results demonstrate the enhancement of slip line pinning by interstitial oxygen.Bulk microdefects in silicon are known to interact with dopants [6]. To investigate this point, we compared the BMD occurrence in non-implanted and antimony-implanted (2 x 1015 at.cm-2) silicon substrates using micro-photoluminescence imaging. These substrates contain relatively high Oi concentrations (up to 6.7 x 1017 at.cm-3) and have been subjected to oxidation and rapid thermal annealing (RTA) above 900°C. After adjusting for background contrast in the implanted and non-implanted regions, Figure 3 shows different trends in BMD density evolution as a function of the probed depth. We assume that a mechanism based on a mechanical stress field induced by the position of the Sb-implanted atoms in the lattice limits the nucleation of oxide precipitates [7]. However, further characterization methods are required to confirm the influence of dopants on the BMD density.Finally, high resistivity silicon substrates are being considered to significantly improve devices performance, particularly in high frequency and photonics applications [8, 9]. However, the understanding of BMD formation is poorly documented in the literature. These CZ-Si substrates are characterized by low oxygen content (< 3 x 1017 at.cm-3) and low boron dopant concentration (< 1 x 1014 at.cm-3). At such low values, the expected oxygen precipitation is very different from that of standard p-type silicon [8, 10]. We investigated the effect of these parameters on BMD formation through precipitation thermal treatments (N2 + O2 anneal > 1000°C). Figure 4 illustrates the important difference in BMD formation depending on the substrate characteristics (standard resistivity high-Oi versus high resistivity low-Oi silicon) after the same thermal treatment. BMD defects were generated in large quantities in standard silicon (3 x 109 BMD.cm-3), whereas no BMDs were observed in HR silicon.In summary, we have demonstrated the impact of interstitial oxygen (coming from substrates and processes) on defect generation, particularly BMD, in silicon technology. In controlled proportions, they play an important role in the proper functioning of devices and very often result from the fine tuning between substrate characteristics and process conditions.[1] Jun Fujise et al 2018 JJAP. 57 035501[2] Zijing Wang et al 2022 APE 15 071004[3] G. Kissinger et al 2019 ECS J3ST. 8 N79[4] Maria Porrini et al 2018 ECS Trans. 86 7[5] Hirofumi Shimizu et al 1985 JJAP. 24 815[6] Hideki Tsuya et al 1983 JJAP. 22 L1[7] Oleksandr Oberemok et al 2014 PSS. 11 163439[8] Isabelle Bertrand et al 2022 ECS Trans. 31 108[9] Jarosław Judek et al 2017 JEM. 46 5589-5592[10] Kaoru Kajiwara et al 2019 PSS. 17 216 Figure 1

Optimization of bulk microdefect performance in epitaxial silicon wafer

Bulk microdefects (BMDs) in epitaxial silicon wafers are pivotal for advanced node integrated circuits, offering enhanced mechanical strength and metal gettering capabilities. This study introduces two heat treatment procedures to optimize BMD density and radial uniformity in lightly doped wafers, addressing the challenges associated with large-diameter crystal growth and the thermal budget constraints of advanced node processes. We demonstrate that Rapid Thermal Annealing (RTA) at temperatures exceeding 1175 °C significantly improves BMD uniformity. A post-RTA stabilization step, when performed prior to epitaxial growth, enhances BMD density by retaining nuclei generated by RTA. Conversely, when the RTA with stabilization step follows epitaxial growth, a higher BMD density and larger BMD size are achieved. Light Scattering Tomography (LST) analysis confirms the optimal conditions for these treatments. The findings contribute to the semiconductor industry by optimizing wafer properties for high-performance ICs.

The effect of RTP pretreatment on slip-lines of argon annealed silicon wafer

In this research, Rapid Thermal Process (RTP) pretreatment technology was used to study the slip-lines of 12-inch light boron-doped silicon wafer with Oxidation Induced Stacking Fault (OISF) ring which will be used for argon annealing. X-ray Diffraction Topography (XRT) test results were shown that Rapid Thermal Processing (RTP) pretreatment below 1250 °C would lead to the deterioration of slip-lines during argon annealing, and that RTP pretreatment no less than 1250 °C would eliminate slip-lines. Bulk Micro Defects (BMD) tests show that RTP pretreatment can deteriorate or eliminate slip-lines resulted from argon annealing. When the RTP pretreatment temperature is lower than 1250 °C, the native BMD nuclei smaller than the critical size will eliminate. During argon annealing, the growth of the residual native BMD nuclei formed during ingot pulling process is the dominant process, while formation and growth of new nuclei are less, resulting in both the reduction of BMD density and broadening distribution of BMD size. Then we see the slip-lines of silicon wafer will become worse due to the increase of thermal stress in the silicon wafer. However, when the RTP pretreatment temperature is no less than 1250 °C, the native BMD nuclei will be completely eliminated and a vacancy enriched layer will be formed in the silicon wafer. During argon annealing, vacancies promote the uniform nucleation of BMD, the density of BMD increases and the size distribution becomes narrow, and the thermal stress in the silicon wafer is relatively lower, thus the slip-lines are eliminated.

Effect of Germanium Codoping on the Grown‐In Oxide Precipitates in Nitrogen‐Doped Czochralski Silicon

The effects of germanium (Ge)‐codoping at 1018, 1019, or 1020 cm−3 level on the grown‐in oxide precipitates in 1014 cm−3 level nitrogen (N)‐doped Czochralski (NCZ) silicon have been investigated. It is found that Ge‐codoping enhances the formation of relatively larger grown‐in oxide precipitates. However, such enhancement effect weakens with the increasing Ge‐codoping concentration. On this basis, the effect of 1018 cm−3 level Ge‐codoping on the near‐surface denuded zone (DZ) and bulk microdefects (BMDs) associated with oxygen precipitation in NCZ silicon subjected to an anneal at 1100 °C for 4 h (1100 °C/4 h) has been paid close attention. Moreover, the sustainability of the DZ in the 1100 °C/4 h ‐annealed NCZ silicon subjected to a “copper decoration” or a rigorous oxygen precipitation anneal featuring a prolonged nucleation anneal has been addressed. Thus, it is technologically significant to learn that for the 1100 °C/4 h ‐annealed NCZ silicon, the 1018 cm−3 level Ge‐codoping can remarkably increase the BMD density to better satisfy the requirement of internal gettering (IG) and also ensure the existence of a well‐defined DZ. Finally, the mechanism underlying the effect of Ge‐codoping on the formation of grown‐in oxide precipitates in NCZ silicon has been tentatively elucidated.

The effects of pre-annealing on oxygen precipitation in silicon P/P-epitaxial wafers

Abstract Herein, the effect of pre-annealing on oxygen precipitation in a silicon P/P-epitaxial wafer was investigated using an experimental approach. Czochralski-grown silicon wafers were annealed at 800–900 °C to enhance their bulk micro defects (BMDs), before the epitaxial growth process. The effect of the pre-annealing temperature on oxygen precipitation was greater than that of the pre-annealing time, and the effect of pre-annealing temperature varied between polished and epitaxial wafers. Regarding pre-annealed epitaxial wafers that were annealed at low temperatures, the pre-annealing time also had as large an effect on BMD formation as the pre-annealing temperature. These experimental results were used to determine the optimal pre-annealing temperature for enhancing oxygen precipitation in epitaxial wafers. The experimental results regarding the optimal conditions were consistent with prior hypotheses. Crystal originated particles (COPs) and COP-free crystals exhibited their highest BMD density values at similar pre-annealing temperatures.

Characterization of internal gettering of copper in the vertical direction of p-type silicon wafer

We determined characteristics of internal gettering of copper in the vertical direction of p-type silicon wafer. Bulk micro-defects (BMDs) caused by oxygen precipitation and the gettering efficiency of Cu along the vertical direction from the surface into the bulk were investigated for Si wafers with and without rapid thermal annealing (RTA) process. Based on scanning infrared microscopy, secondary ion mass spectrometry, and local etching results, the density of BMDs in Si wafers with RTA process was higher than that in Si wafer without RTA process. Depth profile of Cu concentration was strongly related to the BMD density profile in the vertical direction. According to the transmission electron microscopy analysis, Cu impurities were trapped at BMDs through precipitation of copper silicides. It is proposed that the RTA process can improve the internal getterig efficiency of copper in the vertical direction of p-type silicon wafer.

VOn Complexes in RTA Treated Czochralski Silicon Wafers Investigated by FTIR Spectroscopy

Oxygen-vacancy complexes formed after rapid thermal annealing in silicon wafers were investigated by FTIR spectroscopy at 6 K. It was found that VO4 is the only detectable complex. The concentration of VO4 complexes increases with increasing temperature of RTA treatment in the temperature range between 1250°C and 1400°C. The concentration at maximal temperature is equal to 4.5 × 1013 cm−3. The experimental results were compared with concentrations of VOn complexes in silicon wafers obtained using ab-initio calculations combined with rate equation modelling. The simulated concentration of VO4 corresponds well to the measured concentration. The bulk microdefect density increases with increasing VO4 concentration. The vacancies stored in VOn complexes after RTA are slowly released during further annealing and enhance oxide precipitation.

Carbon effect on the survival of vacancies in Czochralski silicon during rapid thermal anneal

Rapid thermal anneal (RTA) at high temperatures can be employed to introduce vacancies to control oxygen precipitation (OP) behavior in Czochralski (CZ) silicon. Such excessive vacancies survive from the recombination of silicon-interstitials and vacancies (V-I recombination) during the RTA. In this work, we aim to elucidate the carbon effect on the survival of vacancies in CZ silicon during the high temperature RTA by means of gold diffusion in combination with deep-level transient spectroscopy. It is revealed that the existence of ∼1017 cm−3 carbon atoms significantly increases the amount of survival vacancies in the form of vacancy-oxygen (VOm, m ≥ 2) complexes in CZ silicon when subjected to the 1250 °C/60 s RTA. Moreover, such an increase in the number of vacancies becomes more significant with the increase in the cooling rate of RTA. The density functional theory calculations suggest that the V-I recombination is to some extent unfavorable as a carbon atom is close to the silicon-interstitial. Alternatively, it is believed that the substitutional carbon (Cs) atoms tend to trap the silicon-interstitials, thus forming Ci complexes (Cs + I → Ci) in CZ silicon during the RTA. In this context, the V-I recombination is suppressed in a manner, leading to the survival of more vacancies, thus generating more VOm complexes. Furthermore, after the 1250 °C/60 s RTA, the oxide precipitate nucleation based on the VOm complexes is more significant in carbon-rich CZ (CCZ) silicon than in the conventional CZ counterpart. Hence, when subjected to the same OP anneal consisting of the nucleation anneal at 650 or 800 °C for 4 h and the subsequent growth anneal at 1000 °C for 16 h, CCZ silicon possesses a higher density of bulk microdefects and therefore stronger internal gettering capability than CZ silicon. However, the nucleation temperature for OP should be carefully selected as 650 °C for CCZ silicon in order to form an oxide precipitate-free denuded zone.

Depth Profile Analysis of Metals Gettered By Bulk Micro-Defects (BMDs) in Silicon Substrates

As semiconductor devices continue to shrink, metallic contamination on silicon surfaces becomes to have a detrimental impact on ULSI device performance and yield [1]. Several gettering techniques have been proposed, and one of the intrinsic gettering techniques is gettering using BMDs (bulk micro defects, oxygen precipitates) in silicon. In this technique, the total surface area of the BMDs is known to affect the gettering efficiency [2, 3]. However, the depth profiles of metals gettered by the BMDs have not been reported. We have experimentally demonstrated the depth profiles of metals gettered by BMDs in silicon wafers with different densities and sizes of BMDs. CZ-Si (100) wafers A, B, and C with different densities and sizes of BMDs were prepared by C- or N-doping and annealing. These wafers were quantitatively contaminated with Cr, Fe, and Cu. The surface concentrations were 2 × 1015 atoms/cm2. The wafers were then annealed at 1000 ºC for 30 min. The surface of the wafers was finally cleaned to remove residual metals. The BMDs in the wafers were measured by laser scattering tomography. The metal concentration at the depths from the surface to 50 μm of the wafers was analyzed using secondary ion mass spectrometry (SIMS). 50-70 nm diameter BMDs are uniformly distributed at a depth of more than 10 μm in wafer A. The deviation of the diameter of BMDs changes from 50-60 nm to 120nm at a depth of more than 13 μm in wafer B. The densities of the BMDs of wafer A and B are more than 6.2 × 109 cm-3 and 3.5 × 109 cm-3 saturated at depths of 10 μm and 13 μm, respectively. Figure 1 shows a sharp rise in the total surface areas of BMDs produced by the densities and sizes at a depth of around 10 μm and 13 μm and then the total surface area of the BMDs is saturated for wafer A, while it slightly rises with increasing depth. This means that the denuded zones of wafer A and B are 10 μm and 13 μm, respectively. The SIMS depth profiles of the metals in the wafers show that Cr, Fe, and Cu concentrations are extremely low at the depth from the surface to 10 μm and 13 μm, while the concentrations are highest at around the depth where the total surface area of the BMDs sharply rises, and the concentrations then decrease with increasing depth, regardless of the BMD size and density profiles, as shown in Fig. 1. The critical surface area of the BMD (S = 4πr2 NBMD d) for effective gettering was observed to be approximately 2 x 10-2, where 4π r2 is each BMD surface area, NBMD is the BMD density, and d is the wafer thickness. This value agrees well with an example in the literature [2, 3]. The total surface area of the BMDs of wafer C at the depth from the surface to 50μm is less than 2 x 10-2, and no metals were detected using SIMS. Modified wafer A with a denuded zone of 2 μm instead of 10 μm also gives the peak of Cr concentration at the depth where the surface area of BMD sharply rises and the Cr concentration at the peak gives approximately a fifth of that of wafer A. It should be noted that although the size or density of the BMDs is dispersed uniformly through the wafers or slightly increases with depth, more metals are gettered at around the depth where the total surface area of the BMDs sharply increases. It is considered that metals diffused in the deeper regions are dispersedly gettered by each BMD in deeper regions during cooling, while metals diffused in the denuded zone (DZ) are gettered by BMDs near the DZ during cooling. For effective gettering by the BMDs, sufficient total surface area of the BMDs should be close to the DZ. Reference [1] K. Saga, et.al, ECS Journal of Solid State Science and Technology, 4 (5) P131-P136 (2015). [2] K. Sueoka, ECS Journal of The Electrochemical Society, 152 (10) G731-G735 (2005).[3] D. Kot, et, al, ECS Transactions, vol.16 no.6, 207-218 (2008). Figure 1

Effect of pressure and temperature on bulk micro defect and denuded zone in nitrogen ambient furnace

The effect of temperature and pressure in the nitrogen ambient furnace on bulk micro defect (BMD) and denuded zone (Dz) is experimentally investigated. It is found that as pressure increases, Dz depth increases with a small decrease of BMD density in the range of temperature, <TEX>$100{\sim}300^{\circ}C$</TEX>. BMD density with hot isostatic pressure treatment (HIP) at temperature of <TEX>$850^{\circ}C$</TEX> is higher than that without HIP while Dz depth is lower due to much higher BMD density. As the pressure increases, BMD density is increased and saturated to a critical value, and Dz depth increases even if BMD density is saturated. The concentration of nitrogen increases near the surface with increasing pressure, and the peak of the concentration moves closer to the surface. The nitrogen is gathered near the surface, and does not become in-diffusion to the bulk of the wafer. The silicon nitride layer near the surface prevents to inject the additional nitrogen into the bulk of the wafer across the layer. The nitrogen does not affect the formation of BMD. On the other hand, the oxygen is moved into the bulk of the wafer by increasing pressure. Dz depth from the surface is extended into the bulk because the nuclei of BMD move into the bulk of the wafer.

Proximity Gettering of Copper via Oxygen Precipitates for Silicon-on-Insulator Wafer

Silicon-on-insulator (SOI) technology has attributed attention because it enables device to operate in high speed with reducing parasitic capacitance and body effect. However, in the conventional SOI wafer without any gettering site, a very small amount of metallic contaminants degrades the transistor. During fabrication of copper through-silicon-via (TSV) for 3D device structure, copper contaminants after copper damascene chemical-mechanical-polishing (CMP) are accumulated at top silicon layer, BOX layer and silicon substrate resulting in gate oxide leakage, junction leakage current, and threshold voltage shift, etc. Particularly, since the copper solubility in oxide layer is higher than that in silicon, the implementation of gettering sites for copper contaminants in SOI wafers is fundamentally difficult. Thus, a design of gettering for copper contaminants in SOI wafers has been a key engineering to improve device characteristics. In this study, we investigated the effect of oxygen precipitates, produced by rapid-thermal annealing (RTA), on gettering efficiency of copper for SOI wafers after a dynamic-random-access-memory (DRAM) heat-treatment. To design a desirable distribution of oxygen precipitates for the gettering sites, the wafers were subjected to a RTA at 1150, 1175 and 1200 ºC for 10 s in an NH3 and Ar gas mixture. In addition, the substrate wafers were annealed at 800 ºC for 4 h in a nitrogen ambient to grow the oxygen precipitates and then followed at 1000 ºC for 16 h. Then, the bonded SOI wafers with proximity gettering sites and conventional SOI wafer were intentionally contaminated with copper of 1 × 1012 atoms/cm2 on the wafer surface, and then all SOI wafers were subjected to a typical DRAM heat-treatment. We correlated concentration of the oxygen precipitate with gettering efficiency of copper contaminants. Figure. 1 shows the distribution of bulk micro defects (BMDs) in the substrate wafer with a different heat-treatment condition. It shows that the substrate wafer subjected to a RTA and two-step heat-treatment has the highest density of BMDs. A SOI wafer was conventionally fabricated and subjected to a DRAM heat-treatment after copper contamination intentionally. In this wafer, concentration of copper contaminants was measured via dynamic secondary ion mass spectroscopy (D-SIMS). As shown in Fig. 2, concentration of copper on top silicon, BOX layer and bulk silicon is high because there is no gettering site. In Fig. 3, a substrate wafer was subjected to a RTA at 1175 ºC for 10 s and then followed two-step heat-treatment. The concentration of copper contaminants was relatively lower than that of Fig 2. This means that coppers were well gathered at oxygen precipitates located at underneath buried oxide after DRAM heat-treatment, verifying an excellent gettering efficiency for copper contaminants. In our presentation, we will discuss the detailed gettering mechanism for copper contaminants in SOI wafers and report proximity gettering of copper via oxygen precipitates for SOI wafer.* This work was financially supported by the Brain Korea 21 Plus Program in 2013 and SiWEDS (Silicon Wafer Engineering and Defect Science).Reference[1] S.M. Myers et al., J. Appl. Phys. 88 (2000) 3795[2] Lixia Lin et al., Solid-State and Integrated Circuit Technology (2010) 1563

A New Type of TSV Defect Caused by BMD in Silicon Substrate

This paper reports on a new type of through-silicon via (TSV) defect, silicon fin defect, which was found after TSV deep-reactive-ion-etching (DRIE) process for TSV integration with front-end-of-line (FEOL) devices. One possible root cause for this defect is that the bulk micro defect (BMD) in silicon substrate serves as a micro-mask during etching and results in silicon fin defects at TSV bottom. These defects have to be eliminated as they are killer TSV defects for several reasons: (1) could serve as a weak point for isolation liner deposition; (2) could be a weak point for barrier/seed layer deposition; and (3) may cause mechanical failures during TSV backside reveal. Previously, silicon fin defects were removed by switching to a non-BMD silicon substrate for interposer application. However, for TSV integration with FEOL devices, the BMD layer serves as an intrinsic gettering layer for devices, therefore, it cannot be removed from the silicon substrate, which makes it challenging to get rid of silicon fin defects. In order to establish a non-destructive in-line detection method of the fin defects, scanning electron microscope (SEM) automatic process inspection (API) was set up to image the fin defects at the bottom of the trench. A special working point with high depth of focus (DoF) and contrast was created to obtain good top-down SEM imaging of the defects at the bottom of this high-aspect-ratio (HAR) structure. Three types of silicon substrates (A, B, and C) were used for this study to investigate the potential root cause. SEM API results show defect rates of 20%, 3.3% and 0% for substrates A, B, and C, respectively. This is in good agreement with both BMD simulation results and benchmarking data in which substrates A, B, and C had normalized BMD densities of 11.7, 5.74, and 1 cm-3, respectively, with a comparable BMD size of 80~90 nm and a denuded zone (DNZ) depth of 10~15 μm. The correlation between BMD density in a silicon substrate and silicon fin defect rate indicates that BMD is a key root cause for silicon fin defects. To eliminate silicon fin defects, an optimized DRIE process has been developed. On the same type of substrate, the DRIE process with a typical voltage bias results in a defect rate of 6.7%, while no silicon fin defect was detected out of 200 TSVs with a polynomial bias ramp to relatively higher final voltage bias during the last 15 μm etch. The hypothesis is that higher voltage bias is able to sputter away BMD and shows potential to get rid of the silicon fin defects at the TSV bottom. In summary, a capable inspection method, a preferred silicon substrate with BMD spec range, and a promising way for DRIE process optimization to eliminate the silicon fin defect at the TSV bottom have been identified and developed in this work. Detailed results and analysis, particularly the fin defect images, statistical inspection results, BMD benchmarking data, simulation results, and TSV profile with optimized process will be discussed in the paper.

Nitrogen Doped 300 mm Czochralski Silicon Wafers Optimized with Respect to Voids with Laterally Homogeneous Internal Getter Capabilities

An internally gettering bulk defect zone and a defect denuded zone of at least 5 µm below the wafer surface were generated by out-diffusion of interstitial oxygen during annealing at temperatures in the range 1075-1100 °C in argon atmosphere. The CZ silicon material used was optimized with respect to voids and contained a central OSF region and an outer Pv region. Due to co-doping of at least 3×1013cm-3nitrogen, a laterally homogeneous bulk microdefect density was obtained which is independent of the temperature of the out-diffusion anneal. The internal getter created in this way efficiently getters nickel impurities as demonstrated in a getter test with 6.6×1011cm-3of intentional Ni contamination. In the central OSF region of the as-grown nitrogen co-doped wafers, the nuclei capable of generating OSFs also degrade the gate oxide integrity. Out-diffusion annealing at 1075-1100°C dissolves most of the defects capable of generating OSFs and it strongly improves the integrity of 5 nm gate oxides.

Structure, chemistry and electrical properties of extended defects in crystalline silicon for photovoltaics

AbstractThe electronic properties of present‐day multicrystalline silicon (mc‐Si) materials for photovoltaic applications are strongly influenced by point defects, their mutual interaction and their interaction with dislocations and grain boundaries. This paper presents results from fundamental investigations of metal impurity interaction with extended defects, namely a small‐angle grain boundary and bulk microdefects. It is shown that the distribution of copper silicide precipitates closely follows the density of bulk microdefects indicating the underlying physics of ‘good’ and ‘bad’ grains frequently observed in mc‐Si. Co‐precipitation of copper and nickel in the same samples leads to virtually the same distribution of multimetal silicide precipitates which according to light‐beam induced current measurements show the same recombination activity as single‐metal silicide particles. Transmission electron microscopy is used to show that for copper‐rich and nickel‐rich conditions two types of silicides co‐exist, i.e. Cu3Si precipitates containing a small amount of nickel and NiSi2 precipitates containing some copper. Finally, phosphorus‐diffusion gettering (PDG) is discussed as the main gettering process used in presentday silicon photovoltaics. Special emphasis is put on the effect of extended defects and their interaction with metal impurities on PDG kinetics. It is shown that different limiting processes will be simultaneously operative in mc‐Si as a result of inhomogeneous bulk defect distributions (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Internal gettering for germanium-doped Czochralski silicon: Treated by rapid-thermal-anneal based processing simulation

Intrinsic gettering (IG) in germanium-doped Czochralski (Cz) silicon wafer has been investigated through a processing simulation of dynamic random access memory fabrication involved with rapid-thermal-anneal (RTA). Compared with that of conventional Cz silicon, both the good quality defect-free denuded zone (DZ) with a slightly narrower width and the gettering region with a slightly higher density of bulk micro-defects (BMDs) could be generated in germanium-doped Cz (GCz) silicon during the device fabrication. These phenomena were interpreted through the generation of denser oxygen precipitates in GCz silicon than Cz silicon, which were considered to be ascribed to the enhancement of precipitate nucleation by the germanium doping. It is therefore believed that the germanium doping could improve the IG capability for Cz silicon wafer.

Characteristic of Junction Leakage Current with Bulk Micro Defect Density in p-n+ Junctions

We investigated the correlation between the junction leakagecurrent and bulk micro-defect (BMD) density for p-n+ junctions fabricated on Czochralski (CZ) Si wafers. In order to measure BMD, the wafers were annealed at 800oC for 4hr, followed by 1000oC for 8, 16, and 24 hr in a N2 ambient. After that, they were polished by 15 μm to remove the denuded zone (DZ) to disclose the BMD for detection using p-n+ junctions. We confirm the junction depth and dopant concentration of the p-n+ junctions by using secondary ion mass spectrometry (SIMS). After the electrical measurements we confirmed that the junction leakage current increases with increasing BMD density. The correlation factor between the junction leakage current and BMD density was about 99%.

An attempt to specify thermal history in CZ silicon wafers and possibilities for its modification

The term thermal history of silicon wafers represents the whole variety of process parameters of crystal growth. The aim of this contribution is an attempt to specify thermal history by one parameter that is directly correlated to the bulk microdefect density. The parameter that reflects thermal history and correlates it with nucleation of oxide precipitates is the concentration of VO 2 complexes. The VO 2 concentration in silicon wafers is too low to be measured by FTIR but it can be obtained from the loss of interstitial oxygen during a standardized thermal treatment. Based on this, the vacancy concentration frozen during crystal cooling in the ingot can be calculated. RTA treatments above 1150 °C create a well defined level of the VO 2 concentration in silicon wafers. This means that a well controlled modification of the thermal history is possible. We also investigated the kinetics of reduction of the as-grown excess VO 2 concentration during RTA treatments at 950 °C and 1050 °C and the effectiveness of this attempt to totally delete the thermal history.

Effects of two‐step rapid thermal processing in different ambients on denuded zone and oxygen precipitation in Czochralski silicon

AbstractThe effects of two‐step rapid thermal processing (RTP) sequentially in different ambients on the formation of denuded zone (DZ) and oxygen precipitation in the Czochralski (CZ) silicon wafers have been investigated. With the first‐step RTP in Ar ambient, no obvious DZ but a high density of bulk micro‐defects (BMDs) were formed in the sample with the second‐step RTP in N2 ambient, while the BMD density in the sample with the second‐step RTP in O2 ambient was remarkably low. With the first‐step RTP in N2 ambient, a high density of BMDs and a width of DZ could be formed in either of the samples with the second‐step RTP in Ar or O2 ambient, but the DZ width in the two samples differed to a certain extent. With the first‐step RTP in O2 ambient, the two samples with the second‐step RTP in Ar and N2 ambients respectively possessed reasonably comparable DZ width and BMD density. (© 2007 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Denuded zone in Czochralski silicon wafer with high carbon content

The thermal stability of the denuded zone (DZ) created by high–low–high-temperatureannealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralskisilicon (Cz-Si) has been investigated in a subsequent ramping and isothermal1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ werechecked. It was found in the L[C] Cz-Si that the DZ shrank and the densityof bulk micro-defects (BMDs) reduced with the increase of time spent at1050 °C. Also, theDZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volumeof BMDs first decreased then increased and finally decreased again during thetreatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs,indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

Rapid-thermal-processing-based internal gettering for heavily boron-doped Czochralski silicon

The effect of rapid-thermal processing (RTP) ambients on the formation of oxygen precipitates and denuded zone (DZ) in heavily boron-doped (HB) Czochralski (Cz) silicon by a low-high (L-H) two-step annealing (800°C∕4h+1000°C∕16h) has been investigated. It was found that after the L-H two-step annealing, there was a high density of bulk microdefects (BMDs) and no observable DZ was formed near the surface in HB Cz silicon wafers preannealed by the RTP in Ar ambient, while the BMD density was quite low in HB Cz silicon wafers preannealed by the RTP in O2 ambient. However, applying the preannealing of RTP sequentially in Ar and O2 ambients allowed us to obtain a high density of BMDs in combination with a sufficient DZ by the subsequent L-H two-step annealing. This approach offers a pathway to optimize internal gettering for HB Cz silicon.