Bulk Fin Field Effect Transistor Research Articles

Bulk-fin field-effect transistor-based capacitorless dynamic random-access memory and its immunity to the work-function variation effect

In this study, we developed a capacitorless dynamic random-access memory (DRAM) (1T-DRAM) device based on a junctionless (JL) bulk-fin field-effect transistor structure with excellent reliability and negligible variability against work-function variation (WFV). We investigated the variation in the transfer characteristics and memory performance of the memory cell owing to WFV. In particular, to investigate the WFV effect, we analyzed the transfer characteristics and memory performance of 200 samples using four metal-gate materials—TiN, MoN, TaN and WN. Consequently, we discovered that the WFV affected the transfer characteristics of the JL bulk-fin field-effect transistor. However, the proposed 1T-DRAM demonstrated that the sensing margin and retention time produced minimal effect owing to the adoption of a structure storing holes in the fin region. Consequently, the proposed 1T-DRAM exhibited strong WFV immunity and excellent reliability for memory applications.

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient (SET) pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor (FinFET) inverter chains with different driven strengths are measured at different temperatures. Three-dimensional (3D) technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature. Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk FinFET technology, resulting in the increase of SET pulse width. On the other hand, the increase of inverter driven strength will change the layout topology, which has a complex influence on the SET temperature effects of FinFET inverter chains. The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

Characterization of charge sharing induced by high LET heavy ions using inverter chains in a commercial bulk FinFET process

The inverter is one of the most important cell types in any standard cell library at each technology node, and it is also very important for single-event research. The distributions and cross-sections of single-event transients (SETs) and single-event multiple transients (SEMTs) were characterized using 14/16 nm bulk fin field-effect transistor (FinFET) inverters under heavy ion radiation. An inverter with double driving strength (INVX2) was used as an instantiate object to observe the SET and SEMT response. 181Ta with energies of 1891 GeV and 2000.5 MeV were used respectively in the experiments, of which the linear energy transfer (LET) values were 87.4 MeV cm2 mg−1 and 75.4 MeV cm2 mg−1. The test results indicated that: (a) the mean pulse widths of the SET and SEMT were less than 100 ps, and decreased with LET decreasing; (b) there was charge sharing between abutted INVX2 inverters placed horizontally, and the generation probability of SEMT induced by charge sharing was less than 1% even if the LET of heavy ion reached 87.4 MeV cm2 mg−1. The results were beneficial for a better understanding of SET and SEMT tolerance for inverters in FinFET technology.

重离子在14-nm FinFET SRAM器件引起的单粒子翻转

The characteristic of single-event upset(SEU) in a 14-nm bulk fin field-effect transistor (FinFET) static random access memory(SRAM) is investigated by heavy-ion experiments. The linear energy transfer(LET) threshold 0.1 MeV/(mg/cm2) is obtained by fitting the SEU cross-section using the Weibull function. The contribution of multiple-bit upset(MBU) is investigated. The results show that when the LET is equal to 40.3 MeV/(mg/cm2), greater than 95% of SEU comes from the MBU. Additionally, the SEU cross-section of the FinFET SRAM presents anisotropies for incident angles associated with the fin direction. This research has a certain kind of guiding role in designing of radiation-hardened complementary metal-oxide semiconductor(CMOS) integrated circuits(ICs) based on FinFET technology.

Machine Learning Approach for Prediction of Point Defect Effect in FinFET

As Fin Field Effect Transistor (FinFET) scales aggressively, even a single point defect becomes a source of performance variability. The point defect is inevitably introduced not only by process damage such as epitaxial growth and ion implantation but also by cosmic rays. Technology computer-aided design (TCAD) is able to simulate the characteristics of the device with the defect. In this work, a machine learning algorithm is tested if it can reproduce the TCAD results. The impact of point defect in bulk FinFET is used as test vehicle to validate the machine-learning algorithm. TCAD is used first to generate a massive number of current-voltage characteristics dataset. The TCAD dataset is then exclusively divided into groups for machine learning training, validation and test. The trained model provides high accuracy test results within 1 % error, showing the possibility to expedite failure analysis cycle via machine learning.

Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs

A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET

The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are experimentally compared to bulk fin field effect transistors (FinFET) over a wide range of temperatures (25–125 °C). A similar temperature dependence of threshold voltage (VTH) and subthreshold swing (SS) is observed for both devices. However, effective mobility (μeff) shows significant differences of temperature dependence between GAA NW-FET and FinFET at a high gate effective field. At weak Ninv (= 5 × 1012 cm2/V∙s), both GAA NW-FET and FinFET are mainly limited by phonon scattering in μeff. On the other hand, at strong Ninv (= 1.5 × 1013 cm2/V∙s), GAA NW-FET shows 10 times higher dμeff/dT and 1.6 times smaller mobility degradation coefficient (α) than FinFET. GAA NW-FET is less limited by surface roughness scattering, but FinFET is relatively more limited by surface roughness scattering in carrier transport.

Effect of source-drain conduction in single-event transient on nanoscaled bulk fin field effect transistor

Fin field effect transistor (FinFET) is a most widely used structure when the field effect transistor is scaled down to 30 nm or less. And there are few studies on single-event transient of FinFET devices with gate length below 30 nm. The single-event-transient on FinFET with gate length below 30 nm is worth studying. The single-event-transient responses of bulk FinFETs with 30 nm, 40 nm, 60 nm and 100 nm gate length are examined by using the pulsed laser and technology computer-aided design (TCAD) simulation in this article. First, we use the pulsed laser to ionize the gate of the FinFET device and detect the transient drain current of the FinFET device. The experimental results show that there are obvious platforms for the transient drain current tails of FinFETs with different gate lengths, and the platform current increases as the gate length of FinFET becomes shorter. The charges collected in the platform of FinFET devices with gate lengths of 100, 60, 40, and 30 nm are 34%, 40%, 51%, and 65% of the total charge collected in transient drain current, respectively. Therefore, when the FinFET device with the gate length below 100 nm, the platform current will seriously affect the device performance. Second, we use TCAD to simulate the heavy ion single-event effect of FinFET device and study the generation mechanism of platform region in transient drain current. The TCAD simulation explains this mechanism. Laser or heavy ions ionize high concentration electron-hole pairs in the device. The holes are quickly collected and the high concentration electrons are left under the FinFET channel. High concentration electrons conduct source and drain, generating the source-to-drain current at the tail of the transient drain current. Moreover the source-drain conduction enhances the electrostatic potential below the FinFET channel and suppresses high-concentration electron diffusion, making source-to-drain current decrease slowly and form the platform. The transient drain current tail has a long duration and a large quantity of collected charges, which seriously affects FinFET performance. This is a problem that needs studying in the single-event effect of FinFET device. It is also a problem difficult to solve when the FinFET devices are applied to spacecraft. And the generation mechanism of the transient drain current plateau region of FinFET device can provide theoretical guidance for solving these problems.

Interface state degradation during AC positive bias temperature instability stress

The reliability of a bulk fin field-effect transistor (FinFET) with a high-k dielectric/metal-gate stack has been investigated by comparing the effects of DC and AC stresses. It is well known that the relaxation during the off-cycle of the AC stress decreases the Vth shift and enhances the device lifetime due to electron detrapping from the high-k dielectric. We found that the relaxation in the interface traps is significantly weaker than that of bulk traps during the unipolar and bipolar AC stresses. The weak recovery is attributed to the concurrent interface state generation during a positive-bias temperature instability (PBTI) stress. Eventually, the interface traps became a major source of the device drift (over 60%) at the high temperature of 400 K. This finding suggests that a new strategy is required to address the PBTI reliability focusing on the residual interface states as well as the bulk trapping, particularly at a high temperature.

Low trigger voltage bulk FinFET silicon controlled rectifier in nanotechnology

The bulk fin field-effect transistor (FinFET) has been the primary semiconductor technology in nanotechnology. To protect low supply voltage circuits based on FinFET, trigger voltage [Formula: see text] of the silicon controlled rectifier (SCR) which acts as electrostatic discharge (ESD) protection device should be lowered further. In this paper, in order to lower the [Formula: see text] an extra implant technique is proposed to form bridging well low trigger voltage FinFET SCR (FinFET BRLVTSCR). The experiments demonstrate that the trigger voltage can be lowered effectively. Moreover, the TCAD simulations bring an in-depth physical understanding of ESD current conduction and failure mechanism during ESD protection. Finally, the turn-on characteristic demonstrates proposed novel SCRs are fast and effective under TLP and very fast TLP (VFTLP) stress.

Bulk FinFET EOT Extraction from Accumulation Capacitance Measurements

In this paper, a new method for equivalent oxide thickness extraction from accumulation capacitance measurements is proposed, which is suitable for fully depleted channels with a body contact such as bulk fin field-effect transistor (FinFET) devices. First, the limitation of the previous approaches reported in the literature is discussed. A new implicit relationship between the semiconductor charge and the surface potential taking into account the increase in the sub-band energies above the conduction/valence band edge is proposed and utilized as a basis for the new extraction method. The efficiency of this method is tested through experimental measurements on a FinFET capacitance and TCAD simulations.

Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques

Single-event transients (SETs) in 16-/14-nm bulk fin field effect transistor (finFET) logic chains have been measured using a custom-designed test IC. A variety of logic gate chains were designed, and SET pulse widths were obtained across a wide range of supply voltages. In light of the increased SET response at reduced supply voltages, the efficacy of filter-based mitigation is assessed by analyzing the voltage dependence of SET duration against the characteristic electrical inverter delay.

Angular Effects on Single-Event Mechanisms in Bulk FinFET Technologies

Angular single-event (SE) mechanisms and experimental upset data for 14-/16-nm bulk fin field-effect transistor (FinFET) technologies are presented and analyzed. The discrete structure of FinFETs introduces unique geometrical and orientation dependences for angular SE mechanisms and SE upset (SEU) responses of FinFET circuits. Geometric analyses and 3-D technology computer-aided design results effectively explain the angular mechanisms behind experimentally observed SE cross-sectional responses. Results show that angular SEU cross-sectional characteristics can be attributed to the proportional contributions of charge deposition regions in the fin structure and the subfin bulk substrate.

Three-dimensional Finite Elements Method simulation of Total Ionizing Dose in 22 nm bulk nFinFETs

Finite Elements Method simulation of Total Ionizing Dose effects on 22nm bulk Fin Field Effect Transistor (FinFET) devices using the commercial software Synopsys Sentaurus TCAD is presented. The simulation parameters are extracted by calibrating the charge trapping model to experimental results on 400nm SiO2 capacitors irradiated under zero bias. The FinFET device characteristics are calibrated to the Intel 22nm bulk technology. Irradiation simulations of the transistor performed with all terminals unbiased reveal increased hardness up to a total dose of 1MRad(SiO2).

Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process**Project supported by the National Natural Science Foundation of China (Grant Nos. 61376109, 61434007, and 61176030).

Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor (FinFET) technology. However, the studies of charge sharing induced single-event transient (SET) pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design (3DTCAD) mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing (RBB), the circuit with forward body-biasing (FBB) is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.

실리콘 트랜치 구조 형성용 유전체 평탄화 공정

Silicon trench process for bulk fin field effect transistor (finFET) is suggested without using chemical mechanical polishing (CMP) that cause contamination problems with chemical stuff. This process uses thickness difference of photo resistor spin coating and silicon nitride sacrificial layer. Planarization of silicon oxide and silicon trench formation can be performed with etching processes. In this work 50 nm silicon trench is fabricated with AZ 1512 photo resistor and process results are introduced.

A Si-based bulk FinFET by novel etching process with mask-less and photoresist-free lithography technique

In this study, we used maskless and photoresist–free nano injection lithography (NIL) to develop a sub–10 nm fin width for a Si–based fin field–effect transistor (FinFET) with a 50–nm fin pitch. The active layer was fabricated using double alignment technology (electron–beam lithography and NIL), and the fin trench was filled perfectly by using a high–density plasma chemical vapour deposition process. Advanced plasma and wet etching processes were employed to obtain the fin height. The fabricated FinFET could provide a pathfinding solution for the continuous scaling of complementary metal oxide semiconductor technology.

Effects of fin width on high‐ κ /metal gate bulk FinFET devices

The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (C ox, C s and R s) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.

Sidewall Crystalline Orientation Effect of Post-treatments for a Replacement Metal Gate Bulk Fin Field Effect Transistor

The crystalline orientation effect is investigated for post-treatments of a replacement metal gate (RMG) p-type bulk fin field effect transistor (FinFET). After post-deposition annealing (PDA) and SF6 plasma treatment, the hole mobility is improved. From low-frequency noise analysis, reduction of the trap density and noise level is observed in PDA- and SF6-plasma-treated devices. (100) sidewall-oriented FinFETs show a lower noise level because of fewer interface traps compared to (110) sidewall-oriented devices. SF6 plasma affects the interface traps, whereas PDA relatively more affects bulk oxide traps for RMG high-k last FinFET.

Current–Voltage Model of Bulk Fin Field-Effect Transistors with a Half-Circle Corner

The drain current of fully depleted (FD) nanoscale bulk FinFETs with the top-channel of a half-circle shape was modeled, for the first time, systematically in all operational regions and compared with the data obtained from three-dimensional (3D) device simulation. In the current model of these devices, it is very important to have accurate threshold voltages for side-channels and top-channel, and take the field penetration effect induced by the top-gate near the top of a fin body into account the threshold voltage (Vth) models for top-channels and side-channels, respectively. So, we obtained successfully the Vth models [Vth0t (Vth model of top-channel at a low drain bias) and Vth0s (Vth model of side-channels at a low drain bias)] considering the field penetration effect for both channels (top- and side-channels) to model the current behaviors in the doped bulk FinFETs with the top-channel of a half-circle shape. Our compact current model with Vth0t and Vth0s predicted accurately the current behaviors of the devices and shown a good agreement with 3D simulation.