Built-in Self-test Research Articles

Design of Front-End Receiver and Matrix for 2–18 GHz with a Searching and Tracking Function for an ELINT System

In this paper, we describe the design and fabrication of a front-end receiver and matrix modules for 2−18 GHz with high gain, good phase matching characteristics, and reliability; this was accomplished by applying a chip-and-wire process using a bare-type monolithic microwave integrated circuit (MMIC) device. To compensate for the mismatch among many sub-modules, a front-end module, matrix module, and built-in test module suitable for sub-band frequency characteristics were designed and applied to the direct receiver. The matrix box used a high-pass filter to remove unwanted low frequencies and a 4-way divider to distribute single input BIT signals. The broadband receiver module had two paths: a phase path and an amplitude path. Phase- and amplitude-matched radio frequency semi-rigid cables of different lengths were used to connect to the internal sub-modules of the matrix receiver. The main RF line was a dielectric substrate, RT/Duroid 5880, with a relative dielectric constant of 2.2 and a dielectric thickness of 0.127 mm. The sizes of the front-end receiver and matrix box were 137 mm × 120 mm × 31 mm and 250 mm × 238 mm × 138 mm, respectively. In the wideband frequency receiver module, the gain was 22.99 dB at mid-band (frequency 2−6 GHz) with a return loss of about 14.76 dB. Th e gain was 23.25 dB at a high band (frequency 6−18 GHz), having a return loss of about 11.63 dB. The peak values of phase matching among the channels for 2–6 GHz were ±3.30°, and the peak values of phase matching among the channels for 6–18 GHz were ±8.24°.

A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process

AbstractAn ultra‐low‐energy SRAM composed of single‐ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1‐kb SRAM prototype based on the single‐ended cells with built‐in self‐test (BIST) and power‐delay production (PDP) reduction circuits was realised on silicon using 40‐nm CMOS technology. Theoretical derivations and simulations of all‐PVT‐corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock.

A Universal BIST Approach for Virtex-Ultrascale Architecture

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs’ capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost.

Specifikacije modernog informacionog sistema za održavanje medicinske opreme u zdravstvu

Effective management of the maintenance of medical equipment (ME), especially high-tech one, is one of the main issues for the quality of health care, for the provision of cost-effective health services and for saving , even in developed countries, insufficient resources. Medical equipment maintenance (EM) includes all activities related to ensuring an adequate level of service and limiting the downtime of medical equipment in a healthcare organization. Traditionally, EM is categorized as preventive maintenance (PM) and corrective maintenance (CM). The principle of PM is prediction. PM can be planned and predictive, ie. Just-In-Time (JIT) maintenance. Predictive maintenance can only be applied to new high-tech medical devices that have built-in self-testing. Planned preventive maintenance is carried out in accordance with the maintenance plan for a certain period of time. As a rule, when creating the plan, we follow the manufacturer's recommendations for preventive maintenance of ME given in the technical documentation of the ME, especially in the instructions for the maintenance of the ME. Predictive or JIT maintenance makes it possible to detect and solve the problem before problems and contingencies actually occur, and this is done on the basis of intelligent monitoring and analysis of the state of ME at the right moment, which ensures the optimal time for intervention, so that maintenance performed only when necessary. The information system for the management of the maintenance of ME in healthcare institutions would interconnect healthcare institutions and enable the fast and safe exchange of data and information related to the maintenance of ME and enable the optimal maintenance of ME in healthcare institutions, increasing the availability of this equipment, especially high-tech equipment, with significant reduction of the total cost of maintaining ME (of the order of 30%). One of the main reasons for the unsustainability of the existing approach to the maintenance of ME in the healthcare institutions of Serbia is that each healthcare institution independently takes care of the maintenance of its own ME. This approach is expensive and significantly affects high maintenance costs. This approach needs to change.

BIST-Supported Cryogenic Write Trimming With In-MRAM Computing Case Study

In the processor-memory separated von- Neumann computation paradigm, the “memory-wall” effect becomes critical due to large access latency and tremendous amount of data movement. In this work, we pursue cryogenic temperature based memory design and focus on spin-transfer-torque magnetoresistive random access memory (STT-MRAM) at 77-Kelvin (achieved with low-cost liquid nitrogen). Cryogenic compact model and its related cryogenic bit-cell are investigated, based on 77 K experiment data of magnetic tunnel junction (MTJ) and CMOS transistor. Compared with the simulated room temperature results, 70% reduction of sensing latency can be obtained at 0.7 V supply voltage, whereas writing latency and yield performance are significantly degraded. In order to overcome the above drawbacks, a novel joint trimming system is proposed including a build-in- self-test (BIST) block and a string of multi-stage level shifters (LS). A case study is executed with in-MRAM computing (IMC). Results show that cryogenic IMC with write trimming provides performance improvements of 33% on average, and concurrently reduces memory energy consumption by 70% on average. The proposed 77 K cryogenic design method can be further applied to other energy constrained applications.

Storage and Counter Based Logic Built-In Self-Test

Storage and Counter Based Logic Built-In Self-Test

Low Power Scan-based Built-in Self-test Based on True Random Number Generator Using Multistage Feedback Ring Oscillator

Low Power Scan-based Built-in Self-test Based on True Random Number Generator Using Multistage Feedback Ring Oscillator

BUILT-IN SELF-TEST AND SELF-CORRECTION METHOD FOR MIXED-SIGNAL INTEGRATED CIRCUITS

In modern integrated circuits the number of devices have strongly increased. As a result, identifying the issues which have an impact on their performance stands out as a very complicated and challenging problem. In digital integrated circuits there are methods which are known, as well as some others which are in the active development stages targeted to enable the built-in self-tests, identify, and report those issues. At that, for mixed signal circuits, where the calculations or functions are performed based on the voltage levels, it is much complicated to develop self-testing mechanisms. A novel method of identifying the lack of clock signal and its duty cycle variation is proposed in this paper. The developed architectures and solutions are capable of detecting the lack of the clock signals, as well as informing the digital parts of the systems about the requirement for the coarse or fine tunings of the clock generation systems outside their autocalibration and loops.

Embryonic Architecture with Built-in Self-test and GA Evolved Configuration Data

Embryonic Architecture with Built-in Self-test and GA Evolved Configuration Data

Universal Address Sequence Generator for Memory Built-in Self-test*

This paper presents the universal address sequence generator (UASG) for memory built-in-self-test. The studies are based on the proposed universal method for generating address sequences with the desired properties for multirun march memory tests. As a mathematical model, a modification of the recursive relation for quasi-random sequence generation is used. For this model, a structural diagram of the hardware implementation is given, of which the basis is a storage device for storing so-called direction numbers of the generation matrix. The form of the generation matrix determines the basic properties of the generated address sequences. The proposed UASG generates a wide spectrum of different address sequences, including the standard ones, such as linear, address complement, gray code, worst-case gate delay, 2i, next address, and pseudorandom. Examples of the use of the proposed methods are considered. The result of the practical implementation of the UASG is presented, and the main characteristics are evaluated.

Built-in Self-Test Algorithm for Functional Broadside Tests

Built-in Self-Test Algorithm for Functional Broadside Tests

A BIST Scheme for Dynamic Comparators

This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injected into the real circuit. The test results were consistent with the simulation results.

A Hybrid Test Scheme for Automotive IC in Multisite Testing

This article proposes a hybrid test scheme based on interleaved test applications to increase the efficiency of multisite testing of integrated circuits (ICs) by solving problems related to test coverage, which is an important feature in automotive IC, and test costs, including the number of test pins and the volume of test data. To solve the problems, a hybrid test scheme that combines the merits of broadcast-based scan compression and built-in self-test (BIST) is proposed. The proposed scheme not only generates deterministic test patterns, similar to scan compression, but also requires fewer test pins, similar to BIST, thereby increasing the efficiency of multisite testing. With appropriately designed linear-feedback shift registers (LFSRs) and seeds periodically inserted through the reduced test pins, the test application process combines deterministic testing and random testing. The random testing stage can compensate the seed-insertion time for the subsequent deterministic testing stage and reduce the number of required deterministic patterns by detecting easy-to-detect faults. For further reduction of the volume of test data and hardware overhead, some compatible scan chains (SCs) are grouped and receive test data from an LFSR. The experimental results show that the proposed method increases the efficiency of multisite testing with a reduced pin count.

SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks

Reconfigurable scan networks (RSNs) enable an efficient reliability management throughout the device lifetime. They can be used for controlling integrated instruments, such as aging monitors or built-in self-test (BIST) registers, as well as for collecting the evaluation results from them. At the same time, they may impose a security threat, since the additional connectivities introduced by the RSN can possibly be misused as a side channel. This article presents an approach for security compliance analysis and resynthesis (SCAR) of RSNs to integrate an RSN compliant with the security properties of the initial design. First, the reachability properties of the original design are accurately computed. The connectivities inside the RSN, which exceed the allowed connectivity of the initial design, are identified using the presented security compliance analysis. Next, all violations are resolved by automated Resynthesis with a minimized number of structural changes. As a result of SCAR, any information leakage due to the RSN integration is prevented, while the accessibility of the instruments through the RSN is preserved. The approach is able to analyze complex control dependencies and obtains a compliant RSN even for the largest available benchmarks.

Novel Built-In Test Equipment for Phase Measurement in Millimeter-Wave Phased Arrays Integrated Circuits With Absolute Phase Measurement Capabilities

This article presents a novel built-in test equipment (BITE) for phase measurements in millimeter-wave integrated circuits (ICs). The BITE targets 5G New Radio (NR) applications. It is able to measure the phase in good agreement with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {S_{21}}$ </tex-math></inline-formula> measurements and has a relative rms phase error lower than 6° over the frequency band of interest. Aside from the relative phase, this BITE also addresses the absolute phase difference of all ICs on the same phased array. To the authors’ best knowledge, this is the first BITE and built-in self-test (BIST) to do so. The BITE is able to reduce the absolute phase discrepancy by a factor of 3. To reduce the measurement complexity, the BITE is implemented as a homodyne architecture to output a dc voltage relative to the phase of the channel. A built-in algorithm is used, mitigating the impairments normally associated with a homodyne receiver. This reduces the design complexity and hence the area overhead. The BITE occupies an area of 480 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\mu m} \times 135\,\,\mathbf {\mu m}$ </tex-math></inline-formula> , facilitating easy integration.

Research on Low Power BIST Based on LFSR Reseeding

With the increasing scale and complexity of the internal circuit, the function of the chip is more powerful, but it will bring serious problems to the test of the chip. The internal power consumption of the chip in the test mode is much higher than that in the normal working mode, especially in the process of built-in self-test, the excessive power consumption will damage the circuit under test and lead to the failure of the chip. The low power test vector generation technology reduces the test power by preprocessing the test vector set. However, the modification of the test vector set results in the low failure coverage in the test process. LFSR replaying technology is a common method of generating test vectors in built-in self-test. It can improve the coverage of test faults by loading test vector seeds into linear feedback shift register. However, while improving the fault coverage, the technology will generate high test power consumption in the circuit under test. In design for testability (DFT), it is a hot topic to generate low-power test vectors by combining LFSR reseeding technology with low-power test vector generation technology. Aiming at the problem of high power consumption caused by test vectors in built-in self-test, this paper proposes a low power test vector generation method based on LFSR reseeding. On the basis of studying the influence of test vector on dynamic test power consumption, the linear correlation between test vector seed and test vector is analyzed deeply. A model of dynamic test power consumption optimization based on Hamming distance sorting test vector seed is proposed to realize the design of low-power test vector seed generation algorithm. Combined with LFSR reseeding technology, a low-power test vector generator based on test vector seed sorting is designed. The simulation design of test vector generator is based on ISCAS85 and ISCAS89. The experimental results show that the total number of test vector seed storage bits is reduced by 64.39%, the average fault coverage is 97.42%, the average area overhead is 4.32%, and the dynamic test power consumption is reduced by 44.21%. Compared with other schemes, the proposed low-power test vector generation technology based on LFSR reseeding has some comprehensive advantages in reducing the number of seed storage bits, improving fault coverage, reducing circuit area overhead and reducing power consumption.

Design of a fully integrated VHF CP‐PLL frequency synthesizer with an all‐digital defect‐oriented built‐in self‐test

This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect-oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40–100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of −132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6μ complementary metal-oxide-semiconductor process.

A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs

Three-Dimensional Integrated Circuit (3D IC) based on Through-Silicon-Via (TSV) has brought a drastic change in IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for system operation. Therefore, testing of TSV is essential for 3D IC. In this article, we propose a cost-effective Built-In Self-Test (BIST) method to test the TSVs of a 3D IC. The test method aims at identifying single and multiple defective TSVs using low test time with small hardware overhead. Further, we introduce a BIST partitioning scheme to reduce the test time and hardware overhead for many TSVs. We also present EBIST, an extended-BIST, to enhance BIST reliability with the least hardware cost. The time cycle needed for testing is calculated and compared with previously proposed methods. The simulation result shows that the proposed BIST reduces the test time by 87% compared to prior works. Moreover, the approach yields reduced area as compared to existing test architecture.

Component-Based Software Testing Method Based on Deep Adversarial Network

With the continuous updating and application of software, the current problems in software are becoming more and more serious. Aiming at this phenomenon, the application and testing methods of componentized software based on deep adversarial networks are discussed. The experiments show that: (1) some of the software has a high fusion rate, reaching an astonishing 95% adaptability. The instability and greater potential of component-based software are solved through GAN and gray evaluation. With the evaluation system, people are dispelled. Trust degree. (2) According to the data in the graph and table, the deep learning adversarial network solves the vulnerability and closedness of the general network, and the built-in test method with experimental data reaching an average accuracy rate of 90% is the best test method for this system. With the deep learning adversarial network, the average test level of component-based software reaches level 7, which makes the new software industry of component-based software have a long way to go.

Adaptive BIST for Concurrent On-Line Testing on Combinational Circuits

Safety-critical systems embedding concurrent on-line testing techniques are vulnerable to design issues causing the degradation of totally self-checking (TSC) property, which is proved to be fatal for further operations (e.g., space electronics, medical devices). In addition to the exploration of the degradation of TSC property over time, a concurrent on-line testing architecture is offered that adjusts the input activity, addressing the absence of input values or the low frequency of their appearance (e.g., during sleep mode). During concurrent on-line testing, the inputs of the circuit under test (CUT) are, at the same time, its test vectors. This architecture tolerates possible degradation of the terms that contribute to the calculation of the totally self-checking goal (TSCG(t)). An adaptive built-in self-test (BIST) unit is proposed that dynamically applies test vector subsets when permitted, based on the frequency of appearance of the input values. The clustering of the inputs is based on the k-means algorithm and, in combination with the ordering of the test vectors to minimize the subsets, results in partitioning the test procedure in a significantly shorter time. The comparison to other solutions used for concurrent on-line testing showed that the proposed adaptive BIST has significant advantages. It can cope with rare occurrences, or even no occurrence, of input values by enabling the BIST mechanism appropriately. The results showed that it may increase the TSCG(t) up to almost 90% when applied during a low-power mode and present better concurrent test latency (CTL) when assumptions regarding the availability of all input values and the probability of occurrence are not realistic.