Logic BIST Research Articles

Logic Diagnosis Based on Logic Built-In Self-Test Signatures Collected In-Field from Failing System-on-Chips

Modern embedded nanoelectronic devices, particularly in safety-critical sectors, require high dependability throughout their lifecycle. To address this, designers have started integrating extra circuitry for on-device self-testing, such as the Logic Built-In Self-Test (LBIST). However, while automatic test equipment (ATE) ensures exhaustive testing during manufacturing, in-field testing capabilities are limited. This study introduces a novel methodology for in-field data collection of failure information from LBIST engines and a subsequent logic diagnosis strategy to facilitate failure analysis of field returns. The information is collected from key-on and key-off self-tests, executed by central processing units (CPUs) with a fixed seed and different frequency configurations, primarily addressing transition delay (TRN) faults. The proposed approach capitalizes on the constrained in-field configurability of LBIST and does not require a custom architecture, making it highly practical and readily applicable to real-world devices. The logic diagnosis strategy significantly reduces the number of candidate faults by exploiting the first failing pattern index found during the in-field testing and data collection. Reducing fault candidates could enhance accuracy during failure analysis, especially when field return devices exhibit a “No Trouble Found” (NTF) behavior. The experimental results are reported for ITC’99 benchmarks and an industrial automotive system-on-chip (SoC) produced by STMicroelectronics, with about 20 million gates.

Reduced On-chip Storage of Seeds for Built-in Test Generation

Logic built-in self-test ( LBIST ) approaches use an on-chip logic block for test generation and thus enable in-field testing. Recent reports of silent data corruption underline the importance of in-field testing. In a class of storage-based LBIST approaches, compressed tests are stored on-chip and decompressed by an on-chip decompression logic. The on-chip storage requirements may become a bottleneck when the number of compressed tests is large. In this case, using each compressed test for applying several different tests allows the storage requirements to be reduced. However, producing different tests from each compressed test has a hardware overhead. This article suggests a new on-chip storage scheme for compressed tests that eliminates the additional hardware overhead. Under the new storage scheme, a set of N B -bit compressed tests targeting a set of faults F 0 is translated into a sequence S of N ⋅ B bits. Every B consecutive bits of S are considered as a compressed test. The sequence S thus yields close to N ⋅ B compressed tests, magnifying the test data stored in S almost B times. Taking advantage of the extra tests, the article describes a software procedure that is applied offline to reduce S without losing fault coverage of F 0 . Experimental results for benchmark circuits demonstrate significant reductions in the storage requirements of S and significant increases in the fault coverage of a second set of faults, F 1 .

Storage-Based Logic Built-In Self-Test With Cyclic Tests

Logic built-in self-test (LBIST) eliminates the need for external test data, and thus facilitates in-field testing. Instead of pseudo-random tests that are typically produced by on-chip test generation logic, storage-based LBIST uses deterministic test data entries, which are stored on-chip, for applying tests that are closer to deterministic tests. This article describes a storage-based LBIST approach that uses a unique type of scan-based tests referred to as cyclic tests. Cyclic tests have cyclic scan enable and scan in sequences, with a higher proportion of functional capture cycles compared with conventional scan-based tests. This results in more clock cycles where fault effects can be captured in the flip-flops. The improved fault detection capabilities this provides helps balance the number of applied tests and the storage requirements. Experimental results for benchmark circuits demonstrate the effectiveness of cyclic tests.

Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests

Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests

Storage and Counter Based Logic Built-In Self-Test

Storage and Counter Based Logic Built-In Self-Test

Storage-Based Logic Built-in Self-Test With Multicycle Tests

Storing deterministic test data on-chip allows logic built-in self-test (LBIST) to produce a special type of random test that consists of random combinations of deterministic test data. Such tests can achieve a higher fault coverage than random tests whose bits are determined randomly. A bottleneck of this approach is the volume of test data that needs to be stored. This article observes that the use of multicycle tests can address this bottleneck by reducing the number of tests needed for detecting target faults and, thus, the volume of test data needed for producing them. A software procedure is described to support this solution. Experimental results for benchmark circuits demonstrate the effectiveness of multicycle tests in this context.

Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion

Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion

LBIST for Automotive ICs With Enhanced Test Generation

Contemporary and emergent automotive systems are heavily populated by complex integrated electronics. The number of safety-critical devices used in advanced driver-assistance systems or autonomous vehicles is growing with high-end models containing hundreds of embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that might be costly to engineer. Therefore, to address challenges posed by high-quality and long-term reliability requirements, this article presents low-cost test pattern generation schemes for a scan-based hybrid logic BIST of automotive ICs. It may allow one to optimize test coverage and test time during in-system test applications. The first presented technique deploys a seed-flipping PRPG to periodically complement PRPG stages in a methodical tree-traversal manner. The second scheme is based on a seed-sorting approach that allows additional tradeoffs between test data volume and test coverage. As shown in this article, the proposed schemes can be easily integrated with a test compression environment and deployed in different modes of in-system testing, such as key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes.

Test power and area optimized logic built-in self-test with higher fault coverage for automobile SoCs

With higher computerization in the automobile stream, the built-in self-test is essential for high quality and high-reliability SoCs. BIST is a self-testing method for the larger SoC designs. This paper presented a new logic BIST architecture with a new weighted pseudorandom TPG and a hybrid test point allocation method. The proposed architecture is optimized for the physical factors such as the test power consumption, the fault coverage, the WSA, and the area overhead during the scan-in testing phase. The proposed method initiated the sharing concept of flip-flops in the test gate strategies to optimize the area overhead. It also demonstrated the test point allocation enabled using the weighted patterns to enhance the fault coverage throughout the scan chains. The primary seeds are flipped and sorted into weighted patterns to obtain the transition delay faults as their complete fault coverage. Simulation works are examined in SilTerra 0.13 μm on Mentor Graphics IC design tool. Experimental results of the logic BIST architecture are executed, and the results are tabulated. The performance comparison of proposed logic BIST with the existing BIST architectures is also analyzed. Consequently, the proposed BIST is employed in the automobile SoC as an application. The ADAS automobile SoC scan circuits were tested in this paper for their self-testing phenomenon. The tabulated results for the physical factors showed that valuable improvements could be accomplished using the proposed BIST compared with the existing authors.

Time multiplexed LBIST for in-field testing of automotive AI accelerators

Logic BIST is a safety mechanism, which performs testing for Automotive electronics. However, pseudorandom LBIST patterns results in increased test time and test power. In this letter, a novel time multiplexed LBIST is presented to overcome test related problems of AI accelerators. First, the accelerator array is divided into smaller sub arrays, which are tested on time multiplexed clock cycles. This: 1) improves overall test time, under the given test power limit, 2) allows reduction in shift power, under given test time limits and 3) since only one sub array is clocked at a time, the peak power is reduced.

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT-LFSR-TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan

Hybrid test schemes comprising on-chip test compression and logic built-in self-test are expected to play a pivotal role in the design of new integrated circuits and delivering high quality tests. As architectural differences between these two paradigms are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This article presents maXpress-an X-tolerant tunable compactor deploying a new scan chain selection mechanism capable of completely masking X states, as required by many in-system or one-directional streaming test applications, within redefinable groups of scan chains and designated scan shift cycles. The proposed scheme is also supporting separate observation scan chains that, in contrast to conventional scan, capture faulty effects every shift cycle, while their content is gradually shifted into a compactor shared with the remaining chains. In addition to a new layout-friendly architecture, the article proposes algorithms to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs

Scan-based logic built-in self-test (LBIST) is widely used for supporting the in-system test in automotive systems. Although this technology has the advantage of low-cost testing, it suffers from low fault coverage and high switching activity during the test. This can lead to many undetected defects, excessive heat dissipation, and IR drop, inducing catastrophic risks to functional safety. Therefore, improving these two key factors is crucial to alleviate reliability problems in the automotive domain. Most previous works have focused on controlling the enormous toggling level of random patterns; however, one of the main disadvantages of these approaches is low fault coverage. Unfortunately, additional hardware costs associated with memory elements or test points are required for detecting the remaining faults. We propose a novel LBIST scheme based on weight-aware scan grouping and scheduling (WGS) to overcome these difficulties. Since the required test time of each automotive product is limited, the proposed scheme freezes the test time and focuses on improving both aforementioned factors significantly. Our approach divides scan cells into two categories: the coverage-efficient scan group and power-efficient scan group, and then it conducts weight-based scan cell reordering. Biased random patterns are fed to enhance fault coverage for the first category. For the second category, scheduling and disabling are performed to reduce switching activity. Finally, physical-aware reordering based on an inverter is performed to reduce routing overhead. Experimental results demonstrate the feasibility of the WGS methodology on the ITC’99 and OpenRISC benchmark circuits.

Power Optimization by Using Reconfigurable LFSR with Gated Clock

LFSR are the most commonly used test pattern generators due to its efficiency than any binary counters. This paper presents the design of a novel reconfigurable LFSR with clock gating for VLSI testing. The technology advancement in VLSI has increased the complexity of chip testing. This complexity in testing has made the Logic BIST (LBIST) more popular than Automatic Test Equipment. This helps the testing with an additional hardware added inside the circuit. ATE does not apply any test patterns but the test patterns are generated by the testing circuits which are inbuilt in the hardware. Thus the cost of testing is greatly reduced. In the LBIST, reconfigurable LFSR are used for the test pattern generation which improves the fault coverage in IC testing. This increases the generation of random test pattern. To increase the speed of testing and reduce the power required a clock gating is introduced in the reconfigurable LFSR. In traditional testing more transistors are required in the circuits resulting in consumption of more power than power required for the functioning of the circuit. Conventional clock circuit consumes 70% of the clock buffer. This reduces the number of switching activities in the BIST. The power consumption of the proposed reconfigurable LFSR with gated clocking is significantly reduced when compared with the conventional LFSR with clocking circuits.

Logic BIST with Observation Scan Improves Functional Safety for Automotive ICs

Logic BIST with Observation Scan Improves Functional Safety for Automotive ICs

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.

VLSI Implementation of Linear Feedback Shift Register (LFSR) based Test Pattern Generator for Pseudo Exhaustive Testing

Advanced strides of improvement in programmable logic density, enhancements in speed and hardware description language (HDL) are empowering design engineers to implement highly performing and testable digital systems. Linear feedback shift registers (LFSR) are the critical elements in the testing and self testing of contemporary complex electronic systems like processors, Built-in-self-test (BIST) controllers and integrated circuits (ICs) etc. Fundamentally BIST is a Design-for-Testability (DFT) technique meant to configure testing functions physically with the circuit under test (CUT). To enhance the percentage of fault coverage as a part of BIST operations (testing the IC), LFSRs are deployed (as test pattern generator) to generate the test vectors inside logic BIST for testing digital systems. Proposed work is focused upon designing a fast adder based variable length pseudorandom binary sequence pattern generator (PRBSPG) and experimental validations. LFSR possess characteristics of high speed, better encoding efficiency, high fault coverage, low test volume data and low power consumption specially suitable in processing environment where uniform distribution random numbers are required. Verilog HDL is employed for structuring the modular design units while Xilinx ISE tool is deployed for validating the proposed LFSR design work and associated modular units.

Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures

This article analyzes and rationalizes the capabilities of inversion test points (TPs) when implemented in lieu of traditional test point architectures. With scaling transistor density, logic built-in self-test (LBIST) quality degrades and additional efforts must keep LBIST quality high. Additionally, delay faults must be targeted by LBIST, but delay faults can be masked when using control-0/1 (i.e., traditional) TP architectures. Although inversions as TPs have been proposed in literature, the effect inversion TPs have on fault coverage compared to traditional alternatives has not been explored. This study extends work previously presented in the North Atlantic Test Workshop (NATW’19) and finds both stuck-at and delay fault coverage improves under pseudo-random tests using inversion TPs, and extended data collection finds noteworthy trends on the effectiveness of TP architectures.

Reduction of Test Data with Hybrid Test Points

ATPG vectors for a combinational circuit exhibit correlations among the bits of a test vector. We propose a BIST circuit design methodology using spectral methods which utilizes the correlation information. This circuit serves dual purposes. It generates BIST vectors that are similar to the ATPG vectors with higher test coverage as compared to random and weighted random vectors. The same circuit can also function as a test data de-compressor for compressed ATPG vectors applied from an external tester. Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts cannot guarantee desired random testability. We present a hybrid test point technology designed to reduce deterministic pattern counts and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. We also exhibit test data compression capabilities of the proposed BIST architecture. This architecture provides a maximum test data compression exceeding and a proportional test time reduction for serial interface reseeding.

Implementation and Utilization of LBIST for 16 bit ALU

This paper refers to implementation of Low Power Built-In-Self-Test (LBIST) and its utilization for testing of 16 bit ALU core. Low Power Test Pattern (LP) Generator is programmable and able to produce pseudorandom test patterns. The programmability feature brings in selectiveness in toggling levels of test patterns. This helps to increase the error coverage gradient. This low power pattern generator consists of a pseudo random pattern generator (PSPR) which can be a linear feedback shift register or ring generator. The test pattern generator allows the production of binary sequences by devices with that selected toggling rate is defined as ‘Preselected toggling’ (PRESTO) activity. In this methodology, controls for operation of generator are selected automatically. Selection of all the controls is made simple and accurate for the tuning. Using this method fault coverage of test pattern generator can be improved as well as pattern count ratio gets improved. The proposed low power test compression method helps to get predictable test patterns. Here preselected toggling based logic BIST is used to get flexible and accurate test patterns hence high quality testing is achieved here with integration of PRESTO and LBIST method.