Built-in Self-test Research Articles

Low-Cost Direct Digital Synthesis-Based On-Chip Waveform Generation for Analog/Mixed Signal BIST Applications

Waveform generation as part of on-chip built-in self-test (BIST) circuitry often necessitates sufficient linearity without expensive hardware overhead. Achieving high linearity is critical for accurate signal generation, especially in applications requiring high precision, such as biomedical and instrumentation applications. Currently, achieving the high linearity and precision required in signal generators often relies on costly hardware such as automated test equipment (ATE). This paper presents a DAC-based arbitrary waveform generator (AWG). We use a low-cost DAC and a fully digital on-chip testing and calibration approach to nullify the effect of the DAC’s non-linearity on the generated waveform. The ultra-low cost and high linearity benefit of the proposed waveform generator makes it highly suitable for integration into resource-constrained systems. The proposed approach is validated using simulation results of the small-area DAC designed in TSMC 0.18 μm technology and the testing and calibration algorithms implemented in MATLAB. The DAC, designed with a matching accuracy at only the 5-bit level, is able to generate a signal with an ENOB of 12 bits alongside an SFDR and THD surpassing 100 dB. This high level of signal purity is consistently maintained across 100 Monte Carlo simulations, demonstrating the robustness of the architecture against PVT variations as well as random mismatches.

Field programmable gate array implementation frameworks of a variable-length pseudorandom pattern generator

A pseudorandom pattern generator produces sequences similar to true random sequences. A variable length pseudo-random pattern generator (PRPG), which can be used as a pattern generator for various applications like built-in self-test (BIST) or cryptography, is proposed in this paper. Our work is based on a linear feedback shift register circuit platform. The proposed design can generate patterns corresponding to different characteristic polynomials of any given polynomial degree. These characteristic polynomials are integrated into the linear feedback shift register circuit by providing an option to select the feedback paths of any of these polynomials. This paper implements and evaluates the proposed design for primitive and non-primitive characteristic polynomials of degrees 3 to 15. The circuit generates output patterns of different periods based on user inputs. Compared to other pseudorandom pattern generator circuits, the proposed circuit can generate a large set of patterns and consumes less power. Adequate results from the experiments demonstrate the functionalities and performance of the proposed pattern generator from degrees 3 to 15. The proposed circuit generates pseudorandom patterns that can be used not only for built-in self-test but also for cryptography and wireless communication applications.

A new 13N-complexity memory built-in self-test algorithm to balance static random access memory static fault coverage and test time

As memories dominate the system-on-chip (SoC), their quality significantly impacts the chip manufacturing yield. There is a growing need to reduce the chip production time and cost, which mainly depends on the testing phase. Hence, a memory built-in self-test (MBIST) utilizing a low-complexity, high-fault-coverage test algorithm is essential for efficient and thorough memory testing. The March AZ1 algorithm, with 13N complexity, was created earlier to balance the test length and fault coverage. However, poor positioning of a write operation in its test sequence caused the reduction of the transition coupling fault (CFtr) detection. This paper presents the creation of the March AZ algorithm, modified from the March AZ1 algorithm, to increase CFtr coverage while preserving the same complexity. It was accomplished by analyzing the fault coverage offered by the March AZ1 algorithm and then reorganizing its test sequence to address the limitation in detecting CFtr. The newly produced March AZ1 algorithm was successfully implemented in an MBIST controller. The simulation tests validated its functionality and demonstrated that the CFtr coverage was enhanced from 62.5% to 75%, achieving an overall fault coverage of 83.3%. Therefore, with 13N complexity, it offers the best fault coverage among all the existing test algorithms with a complexity below 18N.

A Decoupling Method for Multimode Flexible Capacitive Sensors to Decouple Spatial Forces and Dynamic Humidity.

This paper focuses on a four-capacitor flexible sensor composed of two electrode materials; also, the decoupling method and sensing performance for multimodal sensing of spatial forces and dynamic humidity are described. In previous work, decoupling of multimode sensors is mostly done by monitoring the types of signals, numerical differences of the same signal, and stacking multiple parameter-sensitive materials. This paper mainly uses the different characteristics of the two electrode materials; in the simulation and experiment of humidity, the moisture-sensitive electrode quickly wets from the outside to the inside and expands, and the contact angle quickly decreases from 58.5 to 3.7° within 12.04 s, while the copper electrode has no obvious change; in the simulation and experiment of force, the capacitance value of the capacitor composed of the two electrodes changes steadily with the magnitude of the force. That is, the moisture-sensitive electrode can respond to both force and humidity, while the copper electrode responds only to force. So, we use the copper electrode to decouple the spatial force information and calculate the capacitance value of the moisture-sensitive electrode under the influence of only spatial force. The capacitance value of the moisture-sensitive electrode only affected by humidity can be obtained by the difference between the measured capacitance value and the capacitance value under the influence of only spatial force, and then, the humidity value can be obtained according to the material properties. When a single physical quantity changes, the built-in test platform of the experiment verifies that the decoupling accuracy of the force in the dual-mode sensor is as high as 0.95, and the decoupling accuracy of humidity is as high as 0.97. When the two physical quantities change synchronously, the decoupling accuracy of the force is relatively uniformly distributed within the range, and the decoupling accuracy of humidity can reach as high as 0.99 within the range of 31%RH-56%RH. As a humidity sensor, the sensitivity gradually decreases as the humidity increases. During the repeated changes from low humidity to high humidity, the dynamic characteristics, stability, and repeatability have very good performance. The repetition rate is 97.64%, the response time is 11.3 s, the recovery time is 6.8 s, and the capacitance value for 24 days remains basically unchanged. All of these provide some insight into the application of multimode sensors.

Varying Periods of In-Field Testing With Storage and Counter Based Logic Built-In Self-Test

Varying Periods of In-Field Testing With Storage and Counter Based Logic Built-In Self-Test

Intelligent built-in test of wheel speed sensor in aircraft braking system based on FPGA acceleration

Intelligent built-in test of wheel speed sensor in aircraft braking system based on FPGA acceleration

Digital-like built-in defect-oriented test for analog-mixed signal circuits

Digital-like built-in defect-oriented test for analog-mixed signal circuits

Контурні моделі середовища електронної книги в системі «JETIQ VNTU»

The article contains the results of the development of contour models for the e-book environment in the JetIQ VNTU information ecosystem. The authors continued the study of contour models of the educational electronic information environment, one of the elements of which is an electronic book. It is considered as a separate environment for independent and mixed learning, it forms an environment for studying specific topics and performing practical tasks. Such electronic textbooks or laboratory practices have built-in tests, allow the teacher to enter tasks, determine the time for completing tasks, and integrate the obtained grades into an electronic journal. The distribution of contours by type allows researchers to focus their attention on the development of each of the contours - functional, communication, managerial, motivational and emotional. The relationship between them also shows the impact on the level of quality of the educational electronic environment. In addition, it is important to develop a security circuit to preserve one's own knowledge base based on an e-book, to develop author's electronic educational materials.

Implementation of Seed Flipping Test Pattern to Detect Faults in LBIST

Design and manufacturing challenges posed by the increasing transistor count and shrinking feature size in modern chips have significantly heightened the occurrence of defects. As a result, rigorous testing has become indispensable in the VLSI design process. Unfortunately, amidst the lengthy design cycles, test procedures often take a back seat, overshadowed by the primary focus on design development. To ensure high quality and reliability, it is imperative that any VLSI design be entirely fault-free before deployment. Design for Testability (DFT) techniques play a crucial role in facilitating error detection and ensuring robustness during testing phases. Among these techniques, Logic Built in Self-Test (LBIST) stands out for its effectiveness in achieving comprehensive fault coverage. Here it is implemented LBIST with a focus on enhancing fault coverage for a 16-bit test pattern using SFRG (Seed Flipping Ring Generator). This approach not only maximizes fault detection capabilities but also optimizes area and power efficiency compared to alternative pattern generators. By leveraging this test pattern, we aim to address the growing complexity and reliability demands of modern integrated circuits effectively. The code is written in HDL language with Verilog code, and it is implemented using Xilinx Vivado software tool.

Logic Diagnosis Based on Logic Built-In Self-Test Signatures Collected In-Field from Failing System-on-Chips

Modern embedded nanoelectronic devices, particularly in safety-critical sectors, require high dependability throughout their lifecycle. To address this, designers have started integrating extra circuitry for on-device self-testing, such as the Logic Built-In Self-Test (LBIST). However, while automatic test equipment (ATE) ensures exhaustive testing during manufacturing, in-field testing capabilities are limited. This study introduces a novel methodology for in-field data collection of failure information from LBIST engines and a subsequent logic diagnosis strategy to facilitate failure analysis of field returns. The information is collected from key-on and key-off self-tests, executed by central processing units (CPUs) with a fixed seed and different frequency configurations, primarily addressing transition delay (TRN) faults. The proposed approach capitalizes on the constrained in-field configurability of LBIST and does not require a custom architecture, making it highly practical and readily applicable to real-world devices. The logic diagnosis strategy significantly reduces the number of candidate faults by exploiting the first failing pattern index found during the in-field testing and data collection. Reducing fault candidates could enhance accuracy during failure analysis, especially when field return devices exhibit a “No Trouble Found” (NTF) behavior. The experimental results are reported for ITC’99 benchmarks and an industrial automotive system-on-chip (SoC) produced by STMicroelectronics, with about 20 million gates.

A portable test system for the radar

Abstract In order to adapt to the increasingly fierce battlefield confrontation scenarios, a portable, fast deployment and folding test system for the radar is proposed. The corresponding key test items of radar such as spectrum, waveform, lobe, target tracking and data analysis can be completed on the test system. After the Built-in-Test (BIT) information and test system results are integrated, the corresponding evaluation report and implementation recommendations can be provided to the maintenance personnel. This paper expounds the design of each subsystem step by step. The Main Control Unit (MCU) is the task scheduling and information integration center for the system. The corresponding high frequency components, processing components, storage components have been implemented systematic and miniaturized design. In the end, the improvement direction and prospect of the test system are given.

In-field Built-in Self-Test for Detecting Incipient Faults in Analog Reconfigurable Filters

In-field Built-in Self-Test for Detecting Incipient Faults in Analog Reconfigurable Filters

PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST

Reversible logic has gained popularity recently because it allows circuits to use significantly less power. Due to the inherent reversibility of quantum operation, there is enormous interest in designing and optimizing reversible circuits. In this work, a new gate named as transvidkan gate, Quantum Random Reversible Flip Flop, Sequence generator, and Build in Self-Test (BIST) has been proposed. Quantum Random Reversible Flip Flop (QRRFF) is an emerging technology that is used in a variety of apps that use modern security and encryption systems. For creating a random string, typical approaches combine an entropy source with an elimination or bit-generation system. Quantum computing reversible logic chips and Low-power design are emerging as intriguing research topics. A classical logic-based 8-bit reversible comparator is represented using existing reversible gates. This study provides a BIST-based architecture for a comparator design that reduces the garbage outputs, quantum cost, and constant inputs. According to simulation result, the proposed approach outperforms traditional methods in terms of hardware complexity and quantum cost.

Differential-Mode Power Detection for Built-In Self-Test of SiGe Automotive Radar Transceiver Front Ends

Differential-Mode Power Detection for Built-In Self-Test of SiGe Automotive Radar Transceiver Front Ends

A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test

—The built-in self-test (BIST) circuit is designed to be highly integrated with ADC under test and tests the static linearity based on the stimulus error identification and removal (SEIR) method. A novel level shift generator is proposed for high-precision ADC testing to break the resolution limitation caused by thermal noise and non-linearity. The double sampling operation realized by the chopper circuits cancels the sampling kT/C noise, and the circuit further reduces the amplifier's thermal noise by reducing the noise bandwidth. Besides, this paper presents a new method to achieve a highly linearity-constant voltage shift by applying the negative-C technique. Implemented in 180 nm CMOS process, the simulation results show that the noise power of the voltage shift is reduced by 10 dB, and the constancy of voltage shift is only 3.7 ppm over the entire ADC input range. Benefitting from the noise and linearity performance enhancement, this BIST circuit can test 18-bit ADC to 18-bit accuracy level with one-tenth sampling points.

Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

This paper presents a novel approach to optimizing power usage in scalable Built-In Self-Test (BIST) controllers. While BIST mechanisms are crucial for maintaining the reliability of digital circuits, they can be excessively power-hungry during testing phases, particularly in applications where energy consumption is a concern. We propose an innovative architecture incorporating reversible logic gates and circuits to overcome this challenge. Reversible logic is renowned for its low power consumption as it retains information. By integrating reversible logic into our architecture, we can significantly reduce power usage during test cycles, making it an ideal solution for scalable systems ranging from 8 to 32 bits. Our trials showed substantial power savings compared to traditional BIST approaches without sacrificing test coverage or efficiency. Our research provides new opportunities to develop energy-efficient testing methods for digital circuits, contributing to broader efforts in sustainable electronics design.

Method of determination of integral and differential nonlinearities of ADC by three histograms during tests of diagnostic channels in complex magnetotherapy

One of the most important components of modern electronic systems in the fields of medical technology, automotive, 5G communications, etc. are microchips containing analog-to-digital converters (ADCs) on a single chip. Aging effects, environment and mechanical vibrations have a significant impact on the operation of electronic systems, so microcircuits need to be periodically verified, calibrated and even replaced. For this reason, in order to control metrological and technical characteristics of hardware and software of the "Multimag-M" complex, which contains diagnostic channels for measuring pulse wave, respiration process, blood pressure and blood oxygen saturation (saturation), it was proposed to introduce an automated block of control, testing and self-calibration into the structure of the chronomagnetotherapy complex [1]. Application of BIST (Build-in Self Test) - built-in means of self-testing is a promising approach to solving problems of reliability improvement of modern microcircuits [2]. Most of the known BIST methods of ADCs require on-chip highly linear test signal generator (TS) [3-4], which is the most complex block. The ability to test ADCs with a large number of digits is limited by the linearity of the TS generator and as the resolution of ADCs increases, it becomes a difficult task to provide linear TS generation on-chip. The aim of the work is to develop a method for determining the integral and differential nonlinearities of ADC independent of the linearity of the test signal. A method for determining the integral and differential nonlinearities of the ADC, taking into account the nonlinear component of the TS, is proposed. This is achieved by sequentially feeding to the input of the tested ADC a periodic TS of triangular shape, a level-shifted down TS and a level-shifted up TS. The first histogram of ADC codes distribution at absence of TS offset, and also the second and the third histograms at TS downward and upward shifting. Using the three linked histograms, the contribution of the nonlinear component of the TS to the integral nonlinearity for each ADC code is determined. Given the nonlinear component of the TS, the integral nonlinearity for each ADC code is further determined, and then the differential nonlinearity of the ADC is determined from the integral nonlinearity. In addition, the method determines the displacement voltages of the TS, which reduces the requirements for the accuracy of the displacement signal reference. The practical value of the research result lies in the application of the method reducing requirements to TS linearity at self-diagnostics and self-calibration of microcircuits containing ADCs will allow to reduce the complexity of crystal design.

Testing nanometer memories: a review of architectures, applications, and challenges

Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

Reduced On-chip Storage of Seeds for Built-in Test Generation

Logic built-in self-test ( LBIST ) approaches use an on-chip logic block for test generation and thus enable in-field testing. Recent reports of silent data corruption underline the importance of in-field testing. In a class of storage-based LBIST approaches, compressed tests are stored on-chip and decompressed by an on-chip decompression logic. The on-chip storage requirements may become a bottleneck when the number of compressed tests is large. In this case, using each compressed test for applying several different tests allows the storage requirements to be reduced. However, producing different tests from each compressed test has a hardware overhead. This article suggests a new on-chip storage scheme for compressed tests that eliminates the additional hardware overhead. Under the new storage scheme, a set of N B -bit compressed tests targeting a set of faults F 0 is translated into a sequence S of N ⋅ B bits. Every B consecutive bits of S are considered as a compressed test. The sequence S thus yields close to N ⋅ B compressed tests, magnifying the test data stored in S almost B times. Taking advantage of the extra tests, the article describes a software procedure that is applied offline to reduce S without losing fault coverage of F 0 . Experimental results for benchmark circuits demonstrate significant reductions in the storage requirements of S and significant increases in the fault coverage of a second set of faults, F 1 .