Built-in Self-test Controller Research Articles

Built-In Self Test (BIST) Architecture Simulation for Testing Crosstalk Effects in Array Structured Through Silicon Vias (TSV) in 3DICs

In this research, a BIST (built in self test) architecture for testing crosstalk effects in highly dense Through Silicon Via (TSV) placed in structured array form, in 3DICs (Three Dimensional integrated circuits), designed and simulated using the Xilinx ISE tool and the VHDL language. A novel methodology is proposed, and simulated, to observe the test responses of the victim TSVs in the chosen group simultaneously. Boundary-scan cell structures are modified, created for the purpose of operating in different modes such as shift, update and capture in either conventional serial shift mode as well as in proposed parallel broadcasting mode. Output Response Analyzers (ORA), or signature analyzers that have been simulation-verified. In this study, we suggested a novel encoder-based signature generator to locate faulty TSVs in the parallel-observed TSVs. This paper discusses the whole BIST architecture, the BIST controller built on an algorithmic state machine, the design of TPG (Test Pattern Generator), and the faulty TSV signature generator. Comparing the BIST architecture, to serial shift based interconnect tests done by IEEE 1149.1 (JTAG) such as EXTEST and IEEE 1838 standards, the test’s time complexity of BIST is relatively very low. The entire TSV array test is completed in just 32 clock cycles. The design is adaptable and can be used to broadcast test patterns to a group or to transmit test patterns serially using IEEE 1838 or 1149.1.

Synthesis of Built-in Self-Test Control Circuits Based on the Method of Boolean Complement to Constant-Weight 1-out-of-n Codes

We consider the problem of designing a built-in control circuit with full self-testability of control equipment based on the method of Boolean complement to constant-weight 1-out-of-n codes. A method is proposed for determining complementary functions considering the formation of the necessary set of test combinations for a complete check of each element of modulo-2 addition in the structure of the Boolean complement block. Due to the introduction of uncertainties in the selection of values, it is possible to minimize the complexity of control functions, which makes it possible to simplify the control logic block. An algorithm for the synthesis of a built-in self-test control circuit based on the method of Boolean complement to a preselected constant-weight 1-out-of-n code is given.

Performance Analysis of BIST Algorithms

Objective: Performance analyses of March LR and March C- are presented to achieve high fault coverage, low power dissipation, less area utilization and minimum testing time. Methods: Testing of memory consist of Built-In-Self-Test (BIST) controller and circuit-under-test. BIST algorithms are resided inside the BIST controller. BIST algorithms such as March LR and March C- are coded in term of finite state machine. Memory is modeled in verilog and simulated in ModelSims for testing memory faults and it is synthesized by using Xilinx Vivado 2012.2 EDA tool for power, area and timing analysis. Findings: Memory tests are conducted to verify the correctness of each memory location. It involves writing a particular set of data to each memory location and checking that data by reading it. After reading back, if the values are same as those of writing values, then the test is past. If not, the test is fail. Various test methodologies have been developed to detect the memory defects. One such test is BIST technique. Before implementing BIST algorithm, it is necessary to study the various functional faults models for memory defects. The commonly occurs faults are Stuck-At Fault (SAF), Stuck Open Fault (SOF), Transition Fault (TF), Coupling Fault (CF) etc. These functional faults are model and write the code in verilog. Faults are inserted and detected using ModelSims. Using Xilinx Vivado 2012.2 EDA tool, power, area and timing are analyzed. Comparison is made between March C- and march LR. Even though March LR has more length (14N), it has high fault coverage and lesser power dissipation. Thus, March LR is more efficient than March C-. Applications/Improvements: The fault coverage is improved by using March LR. More improvement in March LR can detect more faults which result in the efficiency for online BIST. Keywords: BIST Algorithm, Built-In-Self-Test (BIST), March C- and March LR, Memory Testing

Error Detection of Data Conversion in Flash ADC using Code Width Based Technique

Abstract The high integration density of the complex electronic system requires the multi-functional testing facility to ensure the accuracy of the circuit function. In addition, the wide population of submicron technologies results in the persistent requirements of high precision analog and mixed-signal (AMS) circuits. In the complex, high-density circuits, observing the correctness of output are limited due to the limitations of input and output pins which develop the AMS circuit test as very difficult and expensive. A digital built-in self-test (BIST) scheme has been presented in this paper for testing an analog to digital converter (ADC) in the time domain. The testing scheme consists of the linear analog ramp generator, ADC as a circuit under test, output response analyzer and a BIST controller. Bootstrap linear ramp generator is used to generate the linear analog ramp signal which is applied to ADC to develop the digital word sequence for testing. Among various types of ADCs, here a Flash ADC has used since it is fastest and accurate in digital conversion. A Flash ADC has been designed with the seven-bit resolution and tested using the proposed digital BIST scheme. The ADC comprises a sample-hold circuit, 2N -1 comparator, XOR gates, and encoder block. The output response analyzer verifies the digital output sequence to validate the static test parameters of ADC called monotonicity, missing codes, DNL, and INL error. The BIST controller generates the control signals to control the test sequence. The complete test sequence of ADC BIST has simulated in Tanner EDA with TSMC 0.18um technology. ORA is used to analyze the presence of monotonicity, missing codes, DNL and INL error in the ADC output.

An Efficient Ic On chip Test Framework To Embed Tsv Testing In Memory Bist Using Dynamic Technique

An end-to-end design of a built-in self-test (BIST) infrastructure for 3D-stacked ICs that facilitate the use of BIST at multiple stages of 3D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both pre-bond and post-bond testing. We also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. It results on synthetic stacks assess the impact of inserting BIST in these designs in terms of area, timing, and power overhead. Results show that the overhead due to BIST is negligible. It also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and power constraints, and use two algorithms based on bin packing for solving the problem.

A D-M Chaotic Model ATPG in Mixed Circuits BIST

In order to realize BIST (Built-In Self-Test) of mixed circuits, the D-M chaos ATPG (Auto Test Pattern Generator) method is proposed in this paper. The features of time series generated by D-M chaos model are analyzed to prove that it can be used in ATPG. The ATPG is a wide spectrum of signal sequences, and its correlation is small and close to the white noise, so it can be used in digital circuits BIST. Furthermore, in order to make it can be used in the test of analog circuits, the chaotic time series is reconstructed. FPGA is used as BIST controller of digital-analog mixed circuits test system to validate this method. The experimental results show that the proposed method can effectively identify the fault in mixed-signal circuits, and it can be used in mixed circuits BIST as a general method.

A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs

We present an end-to-end design of a built-in self-test (BIST) and BIST-based diagnosis infrastructure for 3-D-stacked integrated circuits (ICs) that facilitates the use of BIST at multiple stages of 3-D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both prebond and post-bond testing. We also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. A framework for fault diagnosis using the BIST infrastructure for 3-D-stacked ICs is also proposed. We present results on synthetic stacks created from ITC’99 and Open-Core benchmark circuits and assess the impact of inserting BIST in these designs in terms of area, timing, and power overhead. Results show that the overhead due to BIST is negligible. We also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and power constraints, and use two algorithms based on bin packing for solving the problem.

FPGA based High Speed Memory BIST Controller for Embedded Applications

In the current high speed, low power VLSI Technology design, Built in Self Test (BIST) is emerging as the most essential part of System on Chip (SoC). The industries are flooded with diverse algorithms to test memories for faults. The March based algorithms are become popular so quickly for locating faults in memories. This research study attempt to design the memory BIST controller for March 17N as selected algorithm. It tests various memories for faults. A simple architecture is implemented in Verilog Hardware Description Language (HDL), which can be easily integrate with SoC and is able to locate the fault location in the semiconductor memories. Integration of memory BIST controller in SoC design improves chip yield. The design has achieved 497.47MHzof maximum frequency by use of only 158 slice LUTs on Virtex-7 Field Programming Gate Array (FPGA) device. The proposed memory BIST controller is suitable for SoC integration to test various memories at high speed with very low area overhead.

Design and Implementation of Microcode based Built-In Self-Test for Fault Detection in Memory and its Repair

Memories are the most dominating blocks present on a chip. All types of chips contain embedded memories such as a ROM, SRAM, DRAM, and flash memory. Testing of these memories is a very tedious and challenging job as area over head, testing time and cost of the test play an important role. Embedded memories are occupying a significant portion of the System-on-chip area. Because of this trend and the nature of memory’s small geometry, implementing a good memory testing strategy is one of the most significant decision making. Built-In Self-Test, a design technique which uses parts of the circuit to test the circuit itself is used for testing. BIST controller is used to control the total testing process of the memory. General Terms Built in self test (BIST); Built in self repair (BISR);

Fpga Based Implementation of Bist Controller Using Different Approaches

 Abstract—Testing of integrated circuits (IC's) is of crucial importance to ensure a high level of quality in product functionality in both commercially and privately produced products. Due to complex systems, its very difficult to test it. One solution to this problem is to add logic to the IC so that it can test itself. This is referred to as Built in self Test (BIST). In this work, we are designing BIST controller which will detect and correct errors while computing greatest common divisor (gcd) of two non-negative integers using two approaches i.e Euclid's algorithm and Stein's algorithm and comparing the results of both approaches , that we are using in this work. The most efficient way that will come can use for the applications for finding gcd.

Built-In Self-Test Scheme for All-Digital Phase-Locked Loops

This paper presents a low-cost Built-In Self-Test (BIST) scheme, which is based on the principle of parity check code. The proposed circuit is consisted of a XOR network, a frequency decrease module, a BIST controller and a fault detector module. Different from the previous methods of PLL BIST, digital signals from the divide-by-N are grouped as transmission codes, and parity check codes are produced synchronously by the BIST controller. Then the results of parity checking are imported to the fault detector and final test results are generated. Purely digital design flow is adopted and hybrid faults models are used to evaluate the efficiency of the circuit. Experimental results indicates that the proposed method can provide the highest test coverage and lower area overhead, which are 98.3% and 4.2%, respectively.

Design for Testability Technique for Microcontroller

Testing of embedded system including microcontroller is difficult task with external Automatic Test Equipment (ATE). Therefore, empowering the microcontroller to test itself as software-based self-testing (SBST) looks the suitable solution like the microprocessor testing. Practically, the SBST is not suitable for microcontroller testing. It utilizes large space area in the program memory inside the microcontroller that has limited space area in the available memory. Also, it cannot test all microcontroller internal modules and when it test internal modules it cannot make sure that the General Purpose Input Output (GPIO) of the microcontroller work probably without using external ATE. So the Design for Testability (DFT)methodology that uses Instruction Set Architecture (ISA) of the microcontroller family to generate test subroutines and for the Test Pattern Generator (TPG) and part of the Built-In Self-Test (BIST) control unit and uses the external ATE for the other part of the BIST control unit and for the test response compaction (TRC) and evaluation. This paper introduces a hybrid testing methodology that combines both SBST and hardware-based self-test (HBST) for microcontroller testing as an efficient DFT methodology. It introduces for either in the field or as part of a production test of a microcontroller as an example of the system of chip (SoC). This DFT methodology is based on divide and conquer algorithm and requires knowledge of the ISA of the microcontroller to test not only the embedded processor found in microcontroller but also test other peripherals found in it using brute force technique. The comparison between the SBST and the presented hybrid methodology is based on memory utilization, number of clock cycles that was taken to complete each test and the number of modules that can be tested using each of them. Experimental results indicate that the presented methodology is superior in memory utilization, test time and can test all microcontroller modules for both 18F4X2 and 16F87X families.

BIST-Based Fault Diagnosis for Read-Only Memories

This paper presents a built-in self-test (BIST)-based scheme for fault diagnosis that can be used to identify permanent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

Optimized reseeding by seed ordering and encoding

Mixed-mode logic built-in self-test (BIST) applies both pseudorandom test patterns and deterministic test patterns [from an automatic test pattern generation (ATPG) tool] to the combinational portion of the circuit under test. Each scan-test cycle consists of: 1) shifting a test pattern into the scan chains; 2) capturing the response to that pattern; and 3) shifting the captured response out of the scan chains. The shifting of the test pattern out of the scan chains is overlapped with shifting in the next test pattern. The pattern shifted into the scan chains comes from the output of the pseudorandom pattern generator (PRPG); this pattern is determined by the initial state or seed of the PRPG (the contents of the PRPG at the beginning of the shifting operation). In a pseudorandom cycle, the initial state is the final state (last PRPG contents) from the previous cycle. The initial state of a deterministic cycle is shifted into the PRPG either from an a tester or from an on-chip BIST controller. This paper describes techniques to minimize the number of deterministic seeds that must be used: the number of seeds determines the required storage either on the ATE or the chip being tested. These techniques interleave pseudorandom and deterministic cycles rather than first applying all of the pseudorandom cycles and then the deterministic cycles. The decision of when to change from a pseudorandom cycle to a deterministic cycle is made by comparing the final state of the pseudorandom cycle with previously generated ATPG patterns or by carrying out fault simulation on the final state. Which deterministic pattern is chosen for the deterministic cycle critically influences the remainder of the test. A methodology for doing this is described. In addition to interleaving test cycles, it is possible to use partial cycles in which the PRPG operates for a few clocks without loading the scan chains. This allows a new seed to be present without loading the seed from the ATE or controller. As might be suspected, this reduces the number of stored seeds at the penalty of more complexity in the control sequence. These techniques were simulated and compared with conventional reseeding for some ISCAS'89 benchmarks. Improvements varied between 25% and 85% in the required seed storage.

A BIST scheme for RTL circuits based on symbolic testability analysis

This paper introduces a novel scheme for testing register-transfer level (RTL) controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) graph. This TCDF is used to derive a set of symbolic justification and propagation paths (known as the test environment) to test some of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDF's, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability. The test environment of an operation (variable) guarantees the existence of a path from the primary inputs of the circuit to the inputs of the module (register) to which the operation (variable) is mapped, and a path from the output of the module (register) to a primary output of the circuit. Since the search for a test environment is done symbolically, it is very fast and needs to be done only once for each module or register,in the circuit. This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit. The test responses can he analyzed with signature analyzers which are only placed at the primary outputs of the circuit. Unlike many RTL BIST schemes, an increase in the data path bit-width does not adversely impact the complexity of our testability analysis scheme since the analysis is symbolic. Every module in the module library is made random-pattern testable, whenever possible, using gate-level testability insertion techniques. This is a one-time cost. Finally, a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed on the circuit. Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with our scheme. The average area overhead of the scheme is 6.9% which is much lower than many existing logic-level BIST schemes. The average delay overhead is only 2.5%. The test application time to achieve the high fault coverage for the whole circuit is also quite low.

On improving test quality of scan-based BIST

In this paper, we explore two techniques, under the existing scan-based built-in self-test (BIST) architectures, for improving the test quality with practically no additional overhead. The proposed techniques are an almost-full-scan BIST strategy and a general scan-based BIST test application scheme. We first demonstrate that under the scan-based BIST architecture, full scan may not result in the highest fault coverage (FC) and unscanning a small number of scan flip-flops may increase the BIST FC. We then present an algorithm for identifying those not-to-be-scanned flip-flops. We further show that the proposed general scan-based BIST test application scheme could also result in higher BIST FC and only requires a minor modification to the BIST controller. Experiments have been conducted using an industrial tool, psb2, on benchmark circuits to illustrate the effectiveness of the proposed techniques and algorithms. The results have demonstrated that both techniques are able to maximize the FC and reduce the test application time without additional test hardware compared to the conventional scan-based BIST architectures.

A MIMD-based video signal processing architecture suitable for large area integration and a 16.6-cm/sup 2/ monolithic implementation

The architecture and implementation of a programmable video signal processor dedicated as building block of a multiple instruction multiple data (MIMD)-based bus-connected multiprocessor system is presented. This system can either be constructed from several single processor chips, or it can be integrated on a large area integrated circuit containing several processors. The processor allows an efficient implementation of different video coding standards like H.261, H.263, MPEG-1 and MPEG-2. It consists of a RISC processor supplemented by a coprocessor for computation intensive convolution-like tasks, which provides a peak performance of more than 1 giga-arithmetic operations per second (GOPS). A large area integrated circuit integrating 9 processor elements (PE's) on an area of 16.6 cm/sup 2/ has been designed. Due to yield considerations redundancy concepts have been implemented, that-even in the presence of production defects-result in working chips utilizing a lower number of PE's. Each PE has built-in self-test (BIST) capabilities, which allow for an independent test of itself under the control of its integrated fault-tolerant BIST controller. Defective PE's are switched off. Only the PE's passing the BIST are used for video processing tasks. Prototypes have been fabricated in a 0.8 /spl mu/m complementary metal-oxide-semiconductor (CMOS) process structured by masks using wafer stepping with overlapping exposures. Employing redundancy, up to 6 PE's per chip were functional at 66 MHz, thus providing a peak arithmetic performance of up to 6 GOPS.

The compiled logic simulator

A two-value, zero-delay simulator that computes signatures and analyzes fault coverage for circuits with built-in self-test (BIST) is described. The simulator, called the compiled logic simulator (CLS), is used with a monitor that simulates BIST control logic at a high level. The simulator's compiled code is well suited to the IBM 3090 pipeline and fault simulation using flat random patterns. The linear-feedback-shift-register simulation monitor is discussed. Performance results are presented. Fault simulation with one million random patterns on a 40000-gate circuit was done in 16 CPU minutes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>