Built-in Logic Block Observer Research Articles

An Optical BILBO for Online Testing of Embedded Systems

This paper discusses an online testing strategy based on BIST approaches where a novel optical built-in logic-block observation (OBILBO) register was proposed. The OBILBO is similar to the conventional one in addition to optical probing capability, since novel optical probes (OPs) are considered in its architecture. Preliminary simulation results show that, for duplex system cases, fault detection of the normal function of the system is carried out concurrently. In others words, we should emphasize that no tests are applied. Therefore, there is no need to stop the current application. This is achieved through the exploitation of optical beams produced by the OBILBO according to the captured data present at the outputs of the OBILBO, and then sent to a remote system equipped with optical sensors such as a PIN diode. Thus, a comparison is possible in real time. Furthermore, the proposed approach can also be used in the offline mode by selecting the MISR mode of the OBILBO and analyzing the signature in the remote system. Compared to the previous research work, the proposed solution handles the problem of observing test results more efficiently since novel OPs are considered. So, the proposed scheme has very low error detection latency at the expense of extra hardware. In future research work, a complete investigation of benefits and drawbacks of optics-based testing approach will be considered.

Construction of BILBO FF with Soft-Error-Tolerant Capability

In this paper, a soft-error-tolerant BILBO (Built-In Logic Block Observer) FF (flip-flop) is presented. The proposed FF works as a soft-error-tolerant FF in system operations and as a BILBO FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft-error-tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF. The proposed FF contains a reconfigurable C-element with XNOR calculation capability, which works as a C-element for soft-error-tolerance during system operations and as an XNOR gate employed in linear feedback shift registers (LFSRs) during manufacturing testing. The evaluation results shown in this paper indicate that the area of the proposed FF is 8.5% smaller than that of a simple combination of the existing BISER and BILBO FFs. In addition, the sum of CLK-Q delay and D-CLK setup times on system operations for the proposed FF is 19.7% shorter than that for the combination.

An Improved Soft-Error Rate Measurement Technique

Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies, and the trend is expected to get worse. The measurement unit for failures due to soft errors is failure in time (FIT) that represents the number of failures encountered per billion hours of device operation. FIT rate measurement is time consuming and calls for accelerated testing. To improve effectiveness of soft-error rate (SER) testing, the patterns must be targeted toward detecting node failures that are most likely. In this paper, we present a technique for identifying soft-error-susceptible sites based on efficient electrical analysis that treats soft errors as Boolean errors but uses analog strengths to decide whether such errors can propagate to the next stage. Next, we present pattern generation techniques for manifestable soft errors such that each pattern targets a maximal set of soft errors. These patterns maximize the likelihood of detecting a soft error when it occurs. The pattern generators target scan architecture. It is well known that scan test time is dominated by scan shifts, when no useful testing is being done. To improve efficiency of scan-based testing, we extend the functionality of the existing built-in logic block observation (BILBO) architecture to support test-per-clock operation. Such targeted pattern generation and test application improve SER characterization time by an order of magnitude.

A SIC PAIR GENERATOR FOR A BILBO ENVIRONMENT

Built-In Self Test (BIST) techniques are commonly used as an efficient alternative to external testing in today's high-complexity VLSI chips since they provide on-chip test pattern generation and response verification. Among the BIST techniques, Built-In Logic Block Observation (BILBO) has been widely used in practice. Test patterns generated by BILBO structures target the detection of stuck-at faults. It has been shown that most common failure mechanisms that appear into current CMOS VLSI circuits cannot be modeled as stuck-at faults. These mechanisms, modeled by sequential (i.e., stuck-open and delay) faults models, require the application of two-pattern tests (vector pairs) in the circuit-under-test inputs. Single Input Change (SIC) pairs are pairs of patterns where the second pattern differs from the first in only one bit and have been successfully used for two-pattern testing. In this paper we present the BILBO-oriented SIC pair Generator technique that extends BILBO in order to generate SIC pairs; in this way, sequential faults are also detected.

Application of merged current switch logic for a built-in logic block observer operating at 1 Gbit/s and 1.2 V supply

The authors show that merged current switch logic is an excellent candidate for enabling low supply voltages and maintaining an operating speed in the GHz range. The demonstration circuit fabricated in a 0.8 µm BiCMOS process operates at supply voltages as low as 1.2 V, with a bit rate of 1 Gbit/s. The dynamic power consumption is 461 µW/gate.

Concatenated LFSR makes a weighted built-in logic block observation

The length of a test sequence is reduced when using random test vector sequences with a weighted probability, provided that the probabilistic distribution in the inputs of the circuit has been optimized using a suitable method. There are algorithms that determine the probabilistic distribution for the logic 1s in the inputs of the circuit under test. In this paper, we propose a circuit structure that allows generation of random test vectors with a weighted probability, and analysis of the response, using multiple input registers implemented as BILBO registers. Accordingly, we have proceeded with the incorporation of these BIST structures in different benchmark circuits, one of them being the ALU of a communication processor.

Optimization of test parallelism with limited hardware overhead

The main considerations for built-in self-test (BIST) for complex circuits are fault coverage, test time, and hardware overhead. In the BIST technique, exhaustive or pseudo-exhaustive testing is used to test the combinational logic in a register sandwich. If register sandwiches can be identified in a complex digitial system, it is possible to test several of them in parallel using the built-in logic block observation (BILBO) technique. Concurrent built-in logic block observation (CBILBO) technique can further improve the test time, but it requires significant hardware overhead. A systematic scheduling technique is suggested to optimize parallel tests of register sandwiches. Techniques are proposed to deal with shared registers for parallel testing. The proposed method attempts to reduce further the test time while only modestly increasing the hardware overhead.

Realization of a three-valued logic built-in testing structure

It is argued that the practical realization of n-valued logic (n>or=3) built-in testing circuits is not an obvious extension of the binary case. To support this claim, the implementation of a testing technique for ternary CMOS VLSI circuits is presented. A three-valued logic built-in logic block observer (BILBO) has been engineered to operate in four modes: reset, normal, scan path, and signature analysis. The main objective is to provide a method of design and implementation of three-valued logic circuits that are easy to test and able to test themselves. BILBO allows both random testing (signature analysis) and deterministic testing (selected test vectors).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cellular automata circuits for built-in self-test

Results are presented for a variation on a built-in self-test (BIST) technique based upon a distributed pseudorandom number generator derived from a one-dimensional cellular automata (CA) array. These cellular automata logic block observation (CALBO) circuits provide an alternative to conventional design for testability circuitry such as built-in logic block observation (BILBO) as a direct consequence of reduced cross-correlation between the bit streams which are used as inputs to the logic unit under test. The issue of generating probabilistically weighted test patterns for use in built-in self test is also addressed. The methodology presented considers the suitability of incorporating structures based on cellular automata, a strategy which, in general, improves test pattern quality. Thus, CA-based structures quality as attractive candidates for use in weighted test pattern generator design. The analysis involved in determining and statistically evaluating these potential models is discussed, and is compared with that for previous as well as statistically independent models. Relevant signature analysis properties for elementary one-dimensional cellular automata are also discussed. It is found that cellular automata with cyclic-group rules provide signature analysis properties comparable to those of the linear feedback shift register. The results presented here are based upon simulation.

A built-in test module for fault isolation

A broad-level implementation of signature analysis that uses a built-in test module called a testing switch is presented. It is shown how board designers can incorporate the testing-switch modules to reduce the time it takes to isolate faulty chips. Both the test time and the power overhead are better with the testing-switch implementation than with schemes using built-in logic block observer circuits. The proposed technique is especially useful when boundary scan and self-test cannot be implemented in every chip of a board. >

Design for testability and built-in self test: a review

A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered. >

Circular self-test path: a low-cost BIST technique for VLSI circuits

A technique for designing self-test VLSI circuits, referred to as circular self-test path (CSTP), is introduced. The CSTP is a feedback shift register (output of the last flip-flop is supplied to the first flip-flop) with a data communication capability. It serves simultaneously for test pattern generation and test response compaction, thereby minimizing the test schedule complexity; the whole chip is tested in a single test session. A distinguishing attribute of built-in self-test (BIST) chips designed using this technique is a low silicon area overhead, slightly exceeding that of scan path designs, but substantially lower than that of built-in logic block observer (BILBO)-based circuits. Theoretical and simulation studies were performed to demonstrate that the test pattern generation efficiency of the CTSP is comparable to that of a pseudorandom generator, regardless of the functionality of the circuit under test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

ESTA: an expert system for DFT rule verification

A description is given of ESTA, an expert system for the automation of design for testability (DFT) verification. The system takes descriptions written in a conventional hardware description language as input, translates them into a intermediate Prolog form and checks whether they comply either with the level sensitive scan design (LSSD) DFT method of B. Eichelberger and T.W. Williams (1977) or the built-in logic block observation (BILBO) DFT techniques of B. Konemann et al. (1979).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

BILBO registers with nonlinear feedback

Built in logic block observation (BILBO) has become one of the most widely accepted techniques for self-testing of complex digital ICs. This technique is based on grouping the storage elements of the circuit in the two registers which give this technique its name. A BILBO register has four functional modes: with each of the stages acting as independent registers; as a generator of pseudorandom sequences; as analyser of multiple-input signatures; and reset of all stages. For a BILBO register to perform these four functions correctly the feedback from its state to its first stage must satisfy certain conditions. First, the pseudorandom sequence that it generates must be of maximum length, i.e. it must run through all possible states except zero. Secondly, when it is acting as a parallel signature analyser the number of stages must be large enough for the error escape probability to be negligible. Normally the feedback of a BILBO register is linear. We propose the use of nonlinear feedback, through Exclusive-Nor gates, which conserves the properties of linear feedback and provides the advantage that the fourth functional mode, reset, serves as a seed for the other modes. Additional logic is not required and a seed does not have to be introduced from an external source.

Off Line, Built-in Test Techniques for VLSI Circuits

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.