Abstract

A broad-level implementation of signature analysis that uses a built-in test module called a testing switch is presented. It is shown how board designers can incorporate the testing-switch modules to reduce the time it takes to isolate faulty chips. Both the test time and the power overhead are better with the testing-switch implementation than with schemes using built-in logic block observer circuits. The proposed technique is especially useful when boundary scan and self-test cannot be implemented in every chip of a board. >

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