Built-in Hardware Research Articles

Testing Analog and Mixed-Signal Circuits With Built-In Hardware—A New Approach

This paper aims to develop an approach to test analog and mixed-signal embedded-core-based system-on-chips (SOCs) with built-in hardware. In particular, oscillation-based built-in self-test (OBIST) methodology for testing analog components in mixed-signal circuits is implemented in this paper. The proposed OBIST structure is utilized for on-chip generation of oscillatory responses corresponding to the analog-circuit components. A major advantage of the OBIST method is that it does not require stimulus generators or complex response analyzers, which makes it suitable for testing analog circuits in mixed-signal SOC environments. Extensive simulation results on sample analog and mixed-signal benchmark circuits and other circuits described by netlist in HSPICE format are provided to demonstrate the feasibility, usefulness, and relevance of the proposed implementations

Development of an FPGA-Based Data Acquisition Module for Small Animal PET

We report on the design of a data acquisition (DAQ) module for a small animal PET camera developed at our institutes. During the design an important guideline was to develop a system which is built up from strictly identical DAQ modules, and which has no built-in hardware limitation on the maximum number of modules. The developed DAQ module comprises of an LSO scintillator crystal block, a position sensitive PMT, analog signal conditioning circuits, a digitizer, an field programmable gate array (FPGA) for digital signal processing, and a communication module through which the collected data are sent to a cluster of computers for postprocessing and storage. Instead of implementing hardware coincidence detection between the modules, we attach a precise time stamp to each event in our design, and the coincidence is determined by the data collecting computers during postprocessing. The digital CFD algorithm implemented in the FPGA gives a time resolution of 2 ns FWHM for real detector signals

Getting Errors to Catch Themselves—Self-Testing of VLSI Circuits With Built-In Hardware

As the electronics industry continues to grow, technology feature sizes continue to decrease, and complex systems and levels of integration continue to increase, the need for better and more effective methods of testing to ensure reliable operations of chips, the mainstay of today's all digital systems, is being increasingly felt. One obvious way to significantly improve the testability of digital VLSI circuits and save testing time is to use built-in self-testing (BIST), where the basic idea is to have the chip test itself. BIST is a design methodology that combines the concepts of built-in test (BIT) and self-test (ST) in one, termed BIST. This technique generates test patterns and evaluates test responses inside the chip system, and has been widely used in many commercial VLSI products with appreciable success. The subject paper endeavors to present a comprehensive overview of the general methodology of BIST from its various perspectives, and in the sequel attempts to relate its significance in the particular context of modern embedded cores-based system-on-chip (SOC) technology.

ChipLock

The increasing need for security has caused system designers to consider placing some security support directly at the hardware level. In fact, this is starting to emerge as an important consideration in processor design, because the performance overhead of supporting security in hardware is usually significantly lower than a complete software solution. In this paper, we investigate integrating some security support into hardware. We show that security support can be added at some acceptable cost in area and performance. We propose a processor extension called ChipLock. It provides hardware security support for a mostly untrusted operating system to ensure the integrity and confidentiality of all computational results. ChipLock's modular design can be easily integrated into existing hardware platforms with only slight modification to the operating system. ChipLock includes a built-in hardware Key Manager that supports symmetric key assignment, and a read-only-memory, TrustROM, that executes secure hardware routines. The software required is a small trusted portion of the operating system called Trust-Code. We modeled ChipLock's architecture on a full system simulator and showed that, for SPEC2000 benchmarks, it adds about an average of 20% to the execution time, primarily from cryptographic and verification latencies. In addition, layout studies show an area cost of about 8 mm 2 in 180 nm technology. This translates to an area overhead of 5% ~ 15% depending on the processor type.

Self-testing of cores-based embedded systems with built-in hardware

One obvious way to significantly improve the testability of evolving embedded cores-based system-on-a-chip (SoC) and save testing time is to use built-in self-testing (BIST), where the basic idea is to have the chip test itself. This technique generates test patterns and evaluates test responses inside the chip system. The technique has been widely used in commercial VLSI products with appreciable success. The general methodology of BIST in the particular context of today's cores-based SoC technology is presented.

Recovery Schemes for Mesh Arrays Utilizing Dedicated Spares

In this paper, new schemes are presented in which the spare nodes of a permanent-fault-tolerant processing array are utilized in their idling state to aid in an online transient-error recovery process. Though spares-based methods are well-known solutions to permanent-fault tolerance, the cost of these solutions and the idling spare capacity during normal operation have limited their widespread use. Manufacturers must be offered fault tolerance solutions which provide useful work at all times. We propose the enhanced utility of spares-based methods by commissioning idling spares (those spares remaining after fabrication and subsequent replacement of faulty units) to perform transient-error recovery tasks. Our scheme will commission idling spares to perform periodic on-line testing (verifying whether system is functioning correctly), and recovery point validation during normal operation. When an error occurs, the spare will perform additional testing to select recovery points. Transient-error recovery is required in harsh environments, such as high radiation, where frequent transient errors are unavoidable. In these environments, the cost of job completion can be extremely high without some form of error recovery. Successful job completion can be attained in environments frequented by error bursts by identifying reliable data through the process of periodic on-line testing. We apply our scheme to a mesh array architecture that has applications in digital signal processing. Simulations highlight the overhead of our schemes in terms of job completion time in environments burdened with frequent transient random errors and burst errors. The proposed strategies for recovery are limited to systems of regular structure. There are many applications in signal and image processing that require array processing in which the various nodes perform similar operations with different data sets. Therefore, it is not necessary to switch the application algorithms for the spares when they perform redundant computation in a staggered mode. While this is a significant feature, there is a small cost associated with presenting the same data to a node as well as a spare. With built-in hardware and reconfiguration switches in the fault tolerant arrays, we believe this cost will be insignificant. Extension of our work to more general systems requires consideration of many issues including system timing, and sub-unit communication & dependence. This is a problem for future research.

Helper threads via virtual multithreading on an experimental itanium ® 2 processor-based platform

Helper threading is a technology to accelerate a program by exploiting a processor's multithreading capability to run ``assist'' threads. Previous experiments on hyper-threaded processors have demonstrated significant speedups by using helper threads to prefetch hard-to-predict delinquent data accesses. In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading, capable of fly-weight multiplexing of event-driven thread executions on a single processor without additional operating system support. The compiler plays a key role in minimizing synchronization cost by judiciously partitioning register usage among the user-level threads. The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread would be otherwise stalled.The concept of VMT is prototyped on an Itanium ® 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors. On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads, ranging from single-threaded workstation benchmarks to heavily multithreaded large scale decision support systems (DSS) using the IBM DB2 Universal Database. We measure a wall-clock speedup of 5.8% to 38.5% for the workstation benchmarks, and 5.0% to 12.7% on various queries in the DSS workload.

Helper threads via virtual multithreading on an experimental itanium ® 2 processor-based platform

Helper threading is a technology to accelerate a program by exploiting a processor's multithreading capability to run ``assist'' threads. Previous experiments on hyper-threaded processors have demonstrated significant speedups by using helper threads to prefetch hard-to-predict delinquent data accesses. In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading, capable of fly-weight multiplexing of event-driven thread executions on a single processor without additional operating system support. The compiler plays a key role in minimizing synchronization cost by judiciously partitioning register usage among the user-level threads. The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread would be otherwise stalled.The concept of VMT is prototyped on an Itanium ® 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors. On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads, ranging from single-threaded workstation benchmarks to heavily multithreaded large scale decision support systems (DSS) using the IBM DB2 Universal Database. We measure a wall-clock speedup of 5.8% to 38.5% for the workstation benchmarks, and 5.0% to 12.7% on various queries in the DSS workload.

Helper threads via virtual multithreading on an experimental itanium ® 2 processor-based platform

Helper threading is a technology to accelerate a program by exploiting a processor's multithreading capability to run ``assist'' threads. Previous experiments on hyper-threaded processors have demonstrated significant speedups by using helper threads to prefetch hard-to-predict delinquent data accesses. In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading, capable of fly-weight multiplexing of event-driven thread executions on a single processor without additional operating system support. The compiler plays a key role in minimizing synchronization cost by judiciously partitioning register usage among the user-level threads. The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread would be otherwise stalled.The concept of VMT is prototyped on an Itanium ® 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors. On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads, ranging from single-threaded workstation benchmarks to heavily multithreaded large scale decision support systems (DSS) using the IBM DB2 Universal Database. We measure a wall-clock speedup of 5.8% to 38.5% for the workstation benchmarks, and 5.0% to 12.7% on various queries in the DSS workload.

Korean Standard Nuclear Power Plant Response to Common Mode Failure of the Digital Plant Protection System

The Korean Standard Nuclear Power Plant (KSNP) has adopted the digital plant protection system (PPS) to enhance the reliability and safety of the plant. Although the digital PPS can be designed with high reliability, it is considered to be vulnerable to common mode failure (CMF) in the system software, resulting in a total loss of the built-in hardware redundancy. Therefore, a comprehensive evaluation has been performed to demonstrate the intrinsic capability of the KSNP design in coping with the design-basis events concurrent with CMF in the digital PPS. Instead of the conservative bounding analysis methodology, a best-estimate analysis methodology has been developed and utilized since the design-basis events accompanied by CMF in the digital PPS are categorized as beyond-design-basis events. An additional reactor trip function on high containment pressure in the diverse protection system (DPS), which is totally diverse from the PPS and is not affected by the CMF in the digital PPS, has been proposed to meet the acceptance criteria of the evaluation results. A variety of diverse means such as the DPS, process control systems, and operator actions including design modification have been verified to be effective in mitigating the design-basis events with CMF in the digital PPS.

Defense-in-depth and diversity evaluation to cope with design bases events concurrent with common mode failure in digital plant protection system for KNGR

The Korean Next Generation Reactor (KNGR) has been evolved to adopt an advanced design feature, a digital Plant Protection System (PPS) as an effort of enhancing reliability and safety of the plant. Although the digital PPS can be designed with high reliability, it is considered to be vulnerable to the Common Mode Failure (CMF) in the system software resulting in a total loss of the built-in hardware redundancy. Therefore, a comprehensive evaluation has been performed to demonstrate the intrinsic capability of the KNGR design in coping with the design basis events concurrent with CMF in the digital PPS. Instead of the conservative bounding analysis methodology, a best-estimate analysis methodology has been developed and utilized since the design basis events accompanied by CMF in the digital PPS are categorized as beyond design bases events. A variety of diverse means such as Alternate Protection System (APS), process control systems, and timely operator actions have been verified to be effective in mitigating the design basis events with CMF in the digital PPS.

Built-in self-test

The increasing requirements of product quality and availability demand an effective discipline in quality assurance. The continuous expansion of the capabilities of new products, and the need to reduce their life-cycle cost and realization intervals add more stringent requirements to the above quality assurance needs. This paper discusses an approach consisting of a self-contained and reusable built-in hardware capability. In its basic form, this built-in solution performs built-in self-test, and can be extended to built-in self-diagnosis and built-in self-repair for reliability and availability purposes. Moreover, this discipline not only provides an effective quality assurance, but also helps reduce the life-cycle cost and the realization interval of a product.

Signature Analysis for Test Responses of Sequential Circuits

Many test schemes use signature analyzers to compact the responses of a circuit under test. Unfortunately, there can be some faulty circuits with erroneous test responses but exactly the same signature as in the fault-free case. Hence, methods are required to determine how many faults become undetectable due to aliasing. Whereas previous work concentrated on combinational circuits, this paper investigates signature analysis for a wide range of sequential circuits, where the errors in successive responses are correlated. It is shown that for almost all faults of these circuits the probability of aliasing in a signature analyzer with k bits asymptotically approaches 2−k or is 0 if a signature analyzer with an irreducible characteristic polynomial is used and certain test lengths are avoided. The limiting value can be used as a good approximation for practical test lengths. These results are particularly useful for advanced built-in self-test techniques with low hardware overhead.

Multimedia processors

This paper describes large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. General-purpose microprocessors for workstations and personal computers (PCs) use special built-in hardware for multimedia processing, so the multimedia processors described include these modified general-purpose microprocessors. After reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PCs, embedded RISCs, low-power digital signal processors (DSPs), which are mainly used for mobile communications devices, and media processors that support PCs for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSPs. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including system on a chip, and their applications are also discussed.

Fully parallel 30-MHz, 2.5-Mb CAM

Translation functions in high-speed communications networks such as Internet protocol and asynchronous transfer mode are requiring larger and faster lookup tables. Content addressable memories (CAMs) provide built-in hardware lookup capability with high speed and high flexibility in address allocation. Previous high-capacity CAMs have been inadequate for emerging applications; comparators are time-shared among multiple bits or multiple words, resulting in serialized operation, Fully parallel architectures represent the best solution for high-speed operation, but previous fully parallel CAMs have lacked the capacity required for leading-edge networking applications. This paper describes a fully parallel (single-clock-cycle) CAM chip. The chip uses a 0.35-/spl mu/m digital CMOS technology to achieve 2.5 Mb of CAM storage and 30-MHz operating frequency. Innovative layout techniques are used to achieve two-dimensional decoding, a traditional problem with high-capacity CAMs. Architecture and operation of the chip are described, including a novel NAND match architecture, operation-specific self-timing loops, and on-board cascade management circuits. The chip functions at 31 MHz, with a search access time of 26 ns and an average search power dissipation of 5.2 W at 25 MHz.

Characterization of alpha AXP performance using TP and SPEC workloads

The characteristics of several commercial and technical workloads on the DEC 7000 AXP system are compared using built-in hardware monitors. The data analyzed include total instructions, cycles, multiple-issued instructions, stall components, cache misses, and instruction types. The data indicates that the two classes of workloads have vastly different characteristics and impose different requirements on the system design. Compared to VAX, Alpha AXP takes advantage of lower cycles per instruction and cycle time to achieve a significant performance advantage. The cache and memory interconnect subsystems are expected to play a crucial role in the performance of future systems. A simple model for evaluating the effects of various design tradeoffs based on the data collected by using hardware monitors is proposed.

Data-driven array processor for video signal processing

A software approach to digital video signal processing which is based on a programmable array processor that can be used as a building block to construct systems of arbitrary complexity is presented. The processor consists of 16 individually programmable cells with 12-bit RISC (reduced instruction set computer) architectures; the peak performance is 4 GOPS, the maximum data transfer rate across chip boundaries is 750 Mbytes/s. The processor executes statistically scheduled data flow programs. To this end, all communication-whether between cells or between processors-is data-driven (as opposed to clock-driven). Self-timed hardware mechanisms that handle the synchronous data flows automatically and transparently are provided. The technology enables the integration of 1.2 million transistors on a single chip, and clock rates up to 125 MHz. The data flow processor architecture allows the parallelisms inherent in many video applications to be fully exploited; at the same time, the programming task is facilitated through the built-in hardware support for intercell and interprocessor communication.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A microcomputer-based software interface for automatic acquisition of fetal monitoring data.

At University Hospital, interfaces are being designed to link-stand-alone patient care devices to Hospital Information System (HIS). The objective is to have an integrated HIS comprising of data from bedside patient monitors and from stand-alone devices such as infusion pumps, fetal monitors, and pulse oximeters. Interfaces are implemented with standard hardware and software design tools. The feasibility of designing a general purpose interface hardware based on a common microprocessor has been demonstrated for an IMED model 960 infusion pump. The present paper describes the implementation of the software component of the interface using standard microcomputer software packages. The device of choice was the Corometrics model 115 fetal monitor for implementing the software because it is used extensively at University Hospital and has built-in data communication hardware. The Corometrics model 115 fetal monitor was interfaced to an IBM Personal Computer (PC) model XT. Data acquired from the fetal monitor was used to provide data tables and graphs. The feasibility of designing and implementing a software interface capable of acquiring and processing data received from a stand-alone device (fetal monitor) was demonstrated. A description of the important aspects of the interface software design is presented in this paper. This design will eventually be part of the HIS. A brief discussion about the design modifications necessary to acquire data from multiple devices simultaneously is also included.

A CAMAC crate controller for the IBM PC/XT family computers with built-in selftest features

A CAMAC crate controller for the IBM PC/XT was developed at the Laboratory of Nuclear Problems of JINR, Dubna, USSR. The following features were included in the controller: a) access to CAMAC registers treated as memory locations; b) hardware for fast LAM processing and execution of multicrate commands; c) up to 7 crates in one CAMAC system; d) built-in hardware for controller and crate dataway test.

Design of a logic circuit for microprocessor recovery from a power failure and a transient fault

Nonredundant microprocessor ({\mu}p) controlled systems often necessitate the use of built-in algorithms and/or hardware logic in order to ensure reliable and smooth functioning of the {\mu}p whenever a fault occurs during normal operation or power-up sequence. In this paper, we present a class of fault-detection algorithms and hardware recovery circuit along with their implementation methodology. The novelty of the proposed design lies in the simplicity of the logic circuit and software algorithms and their ready adaptability to any {\mu}p .