Oxide Charge Buildup Research Articles

Numerical Modeling of Oxide and Interface Charge Buildup in Field Oxide Transistors During Irradiation and Annealing

Numerical Modeling of Oxide and Interface Charge Buildup in Field Oxide Transistors During Irradiation and Annealing

Threshold-voltage bias-instability in SiC MOSFETs: effects of stress temperature and level on oxide charge buildup and recovery

In this study we performed slow and fast bias temperature instability (BTI) measurements on n-channel silicon carbide (SiC) metal-oxide-SiC field effect transistors. Threshold voltage (V th) shifts as well as recovery observed during and after stress applied at different temperatures and stress levels were used to understand the dynamics of charge trapping/capture and detrapping/emission at gate oxide defects. It is deduced from the results that no new defects are created by the stress at the levels used in this study and V th shifts are due to the injected electron capture and trapping at existing oxide border traps. Positive gate-voltage BTI induced V th shift is observed to follow a power law on stress time with an exponent, n, dependent on stress temperature and level, such that 0.03 ⩽ n ⩽ 0.09. Electron emission and/or defect interactions are found to proceed with a low activation energy of the order of 0.01 eV and are suggested to be responsible for oxide charge reduction and, consequently, V th recovery.

First-principles calculations of F-, Cl-, and N-related defects of amorphous SiO2 and their impacts on carrier trapping and proton release* *Project supported by the Science Challenge Project (Grant No. TZ2016003-1-105), CAEP Microsystem and THz Science and Technology Foundation (Grant No. CAEPMT201501), the National Basic Research Program of China (Grant No. 2011CB606405), and Tianjin Natural Science Foundation, China (Grant No. 20JCZDJC00750).

The first-principles calculations based on density functional theory are performed to study F-, Cl-, and N-related defects of amorphous SiO2 (a-SiO2) and their impacts on carrier trapping and proton release. The possible geometric configurations of the impurity-related defects, the formation energies, the hole or electron trapping of the neutral defects, and the mechanisms to suppress proton diffusion by doping N are investigated. It is demonstrated by the calculations that the impurity atoms can interact with the oxygen vacancies and result in impurity-related defects. The reactions can be utilized to saturate oxygen vacancies that will cause ionization damage to the semiconducting devices. Moreover, the calculated formation energy indicates that the F- or Cl-related oxygen vacancy defect is a deep hole trap, which can trap holes and prevent them from diffusing to the a-SiO2/Si interface. However, three N-related defects, namely N(2)o–H, N(2)o=O, and N(3)o–V o, tend to act as shallow hole traps to facilitate hole transportation during device operation. The N(2)o and N(3)o configurations can be negatively charged as deep electron traps during the oxide charge buildup after ionization radiation. In addition, the nudged elastic band (NEB) calculations show that four N-related defects, namely N(2)o, N(2)o–H, N(2)o=O, and N(3)o are capable of capturing protons and preventing them from diffusing to and de-passivating the interface. This research reveals the fundamental properties of the F-, Cl-, and N-related defects in amorphous silica and the details of the reactions of the carrier trapping and proton release. The findings help to understand the microscopic mechanisms that alleviate ionization damage of semiconducting devices by doping a-SiO2.

A combined surface and bulk TCAD damage model for the analysis of radiation detectors operating at HL-LHC fluences

In this work we present the development and the application of a new TCAD modelling scheme to simulate the effects of radiation damage on silicon radiation detectors at the very high fluence levels expected at High Luminosity LHC (up to 2 × 1016 1MeV n/cm2). In particular, we propose a combined approach for the analysis of the surface effects (oxide charge build-up and interface trap states introduction) as well as bulk effects (deep level traps and/or recombination centers introduction). Experimental measurements have been carried out aiming at: i) extraction from simple test structures of relevant parameters to be included within the TCAD model and ii) validation of the new modelling scheme through comparison with measurements of different test structures (e.g. different technologies) before and after irradiation. The good agreements between experimental measurements and simulation findings foster the suitability of the TCAD modelling approach as a predictive tool for investigating the radiation detector behavior at different fluences and operating conditions. This would allow the design and optimization of innovative 3D and planar silicon detectors for future HL-LHC High Energy Physics experiments.

On the Recoverable and Permanent Components of NBTI in p-Channel Power VDMOSFETs

This paper introduces a new experimental approach allowing to investigate the recoverable and permanent components in commercial p-channel power VDMOSFETs subjected to negative bias temperature (NBT) stressing. In many applications, devices can be used in multiple modes, which include application of static or pulsed gate voltages at different stages of device operation. Accordingly, we have investigated stress-induced degradation in the cases where the static stress was followed by the pulsed NBT stress conditions and vice versa. The results are discussed in terms of the mechanisms responsible for the buildup of oxide charge and interface traps. It has been shown that the differences in the permanent components of the oxide charge and interface traps between devices exposed to static stress followed by pulsed NBT stress and those exposed only to static NBT stress tend to decrease during the pulsed stress as the duty cycle increases but cannot be completely removed.

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET**Project supported by the Fund from the Ministry of Education, Science and Technological Development of the Republic of Serbia (Grant Nos. OI-171026 and TR-32026) and the Ei PCB Factory, Niš.

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

Experimental evidence and modeling of non-monotonic responses in MOS dosimeters

The evolution of the threshold voltage of MOS dosimeters during irradiation under switched bias is investigated with the aim of using the sensors with a new biasing technique. The devices response to a bias change does not only depend on the instant threshold voltage and bias, and may lead to non-monotonical behavior under fixed bias following the switch. This work shows experimental evidence for this effect and presents a simple model based on oxide charge buildup and neutralization. The proposed model reproduces the experimental data assuming the existence of two types of hole traps in the oxide. Physical interpretations of the results are discussed.

Effects of High–Energy Neutrons on Advanced SOI MOSFETs

This work discusses the degradations caused by high-energy neutrons in advanced MOSFETs and compares them with damages created by γ-rays reviewing the original researches performed in our laboratory during last years [1-6]. Fully–depleted (FD) Silicon-on-Insulator (SOI) MOSFETs and Multiple-Gate (MuG) FETs with different geometries (notably gate lengths down to 50 nm) have been considered. The impact of radiation on device behavior has been addressed through the variation of threshold voltage (VT), subthreshold slope (S), transconductance maximum (Gmmax) and drain-induced barrier lowering (DIBL). First, it is shown that degradations caused by high-energy neutrons in FD SOI and MuG MOSFETs are largely similar to that caused by γ-rays with similar doses [1,3]. Second, it is revealed that, contrarily to their generally-believed immunity to irradiation [7, 8], very short-channel MuGFETs with thin gate oxide can become extremely sensitive to the total dose effect [2,3]. The possible reason is proposed. Third, a comparative investigation of high-energy neutrons effects on strained and non-strained devices demonstrates a clear difference in their response to high-energy neutrons exposure [6]. Finally, based on simulations and modeling of partially –depleted (PD) SOI CMOS D Flip-Flop, we show how radiation-induced oxide charge and interface states build-up can affect well-known tolerance of SOI devices to transient effects [4,5].

Hot-carrier degradation caused interface state profile—Simulation versus experiment

Hot-carrier degradation is associated with the buildup of defects at or near the silicon/silicon dioxide interfaced of a metal-oxide-semiconductor transistor. However, the exact location of the defects, as well as their temporal buildup during stress, is rarely studied. In this work we directly compare the experimental interface state density profiles generated during hot-carrier stress with simulation results obtained by a hot-carrier degradation model. The developed model tries to capture the physical picture behind hot-carrier degradation in as much detail as feasible. The simulation framework includes a transport module, a module describing the microscopic mechanisms of defect generation, and a module responsible for the simulation of degraded devices. Due to the model complexity it is very important to perform a thorough check of the output data of each module before it is used as the input for the next module. In this context a comparison of the experimental interface state concentration observed by the charge-pumping technique with the simulated one is of great importance. Obtained results not only show a good agreement between experiment and theory but also allow us to draw some important conclusions. First, we demonstrate that the multiple-particle mechanism of Si–H bond breakage plays a significant role even in the case of a high-voltage device. Second, the absence of the lateral shift of the charge-pumping signal means that no bulk oxide charge buildup occurs. Finally, the peak of interface state density corresponds to the peak of the carrier acceleration integral and is markedly shifted from typical markers such as the maximum of the electric field or the carrier temperature. This is because the degradation is controlled by the carrier distribution function and simplified schemes of hot-carrier treatment (based on the mentioned quantities) fail to describe the matter.

Failure Analysis and Radiation-Enabled Circuit Simulation of a Dual Charge Pump Circuit

Dual charge pump data show a reduction of circuit output voltage with dose. Through testing of individual process monitors, the response is identified as parasitic interdevice leakage caused by trapped oxide charge buildup in the isolation oxide. A library of compact models is generated for the field oxide parasitic based on test structure data along with 2-D structure simulation results. The charge pump schematic is then back annotated with transistors representative of the parasitic at different dose levels. Inclusion of the parasitic devices in schematic allows for simulation of the entire circuit at a specific dose. The reduction of circuit output with dose is then re-created in simulation.

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO 2 and HfO 2/SiO 2 gate dielectric stacks

We compare charge carrier generation/trapping related degradation in control oxide (SiO 2) and HfO 2/SiO 2 stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained Si O Si bonds in either of the devices. We demonstrate that compared to SiO 2 devices, HfO 2 devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO 2 devices at a given operating voltage.

Extension of the Measurement Range of MOS Dosimeters Using Radiation Induced Charge Neutralization

This work proposes a new measurement technique to extend the dose range of MOS dosimeters. The technique consists on alternating stages of positive oxide charge buildup with stages of radiation induced charge neutralization, maintaining a uniform sensitivity along the whole measurement. The technique was applied with 70 nm MOS dosimeters, extending the dose measurement range from less than a kilogray to more than 675 kGy without showing wear effects. An initial saturation of interface traps creation ensures repeatability in the responses.

Research on total-dose hardening for H-gate PD NMOSFET/SIMOX by ion implanting into buried oxide

In this work, we investigate the back-gate I-V characteristics for two kinds of NMOSFET/ SIMOX transistors with H gate structure fabricated on two different SOI wafers. A transistors are made on the wafer implanted with Si+ and then annealed in N2, and B transistors are made on the wafer without implantation and annealing. It is demonstrated experimentally that A transistors have much less back-gate threshold voltage shift ΔVth than B transistors under X-ray total dose irradiation. Subthreshold charge separation technique is employed to estimate the build-up of oxide charge and interface traps during irradiation, showing that the reduced ΔVth for A transistors is mainly due to its less build-up of oxide charge than B transistors. Photoluminescence (PL) research indicates that Si implantation results in the formation of silicon nanocrystalline (nanocluster) whose size increases with the implant dose. This structure can trap electrons to compensate the positive charge build-up in the buried oxide during irradiation, and thus reduce the threshold voltage negative shift.

On the electrical stress-induced oxide-trapped charges in thin HfO2∕SiO2 gate dielectric stack

Oxide charge buildup and its generation kinetics during constant voltage stress in TaN∕HfO2∕SiO2∕p-Si structures have been experimentally investigated. From the oxide charge relaxation experiments, nature and energy location of the as-fabricated intrinsic hole traps in the gate stack have also been determined. Our measurement results indicate that the dispersive proton transport through the interfacial SiO2 contributes larger than hole trapping in positive charge buildup in the stack. From the bias temperature stress measurement results in both control oxide and HfO2∕SiO2 stacks, we have identified overcoordinated [Si2=OH]+ centers as the proton-induced defects located in the interfacial SiO2 layer of the stack. Finally, an empirical equation is proposed to explain the stress-induced oxide positive charge buildup.

Mechanism of Static and Dynamic Bias Temperature Instability in p- and n-MOSFETs

The BTI-induced degradation of device performance has been ascribed to interface trap generation (ΔNit) and oxide charge buildup (ΔNot) at or near the SiO2/Si interface. Moreover, it has been widely recognized that degradation under dynamic BTI stressing may differ from that under static stressing. In this paper, our recent studies on BTI are reviewed. First, a modified direct-current current-voltage (DCIV) method is proposed, which can monitor ΔNit and ΔNot separately, and is independent on the measurement temperature. Second, negative BTI in pMOSFETs with ultrathin plasma-nitrided SiON gate dielectrics is systematically studied, as well as the effect of nitrogen concentration, using the modified DCIV method. Third, dynamic BTI with is studied at various stressing configurations. A transient degradation enhancement is observed upon quick gate voltage reversal from the accumulation bias to the inversion bias. Finally, a modified reaction-diffusion model is proposed to consistently explain the observed static and dynamic BTI behavior.

Estimation and verification of radiation induced N/sub ot/ and N/sub it/ energy distribution using combined bipolar and MOS characterization methods in gated bipolar devices

Complementary bipolar and MOS characterization techniques, specifically the gate sweep (GS) and sub-threshold sweep (SS), are used to estimate the radiation induced oxide charge (N/sub ot/) and interface trap (N/sub it/) buildup in gated bipolar test devices. The gate sweep and sub-threshold sweep data from recent TID testing of gated lateral PNP devices suggests an asymmetric energy distribution of interface traps after ionizing radiation exposure. Charge pumping (CP) experiments were done on the test devices to estimate the energy distribution of interface traps induced by radiation. The CP results are used in this paper to confirm the analytical findings from the GS and SS techniques and solidify the use of the complementary method as a simple way of determining radiation induced interface trap distribution in gated bipolar devices.

Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics

The interface trap generation (ΔNit) and fixed oxide charge buildup (ΔNot) under negative bias temperature instability (NBTI) of p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with ultrathin (2 nm) plasma-nitrided SiON gate dielectrics were studied using a modified direct-current–current-voltage method and a conventional subthreshold characteristic measurement. Different stress time dependences were shown for ΔNit and ΔNot. At the earlier stress times, ΔNit dominates the threshold voltage shift (ΔVth) and ΔNot is negligible. With increasing stress time, the rate of increase of ΔNit decreases continuously, showing a saturating trend for longer stress times, while ΔNot still has a power-law dependence on stress time so that the relative contribution of ΔNot increases. The thermal activation energy of ΔNit and the NBTI lifetime of pMOSFETs, compared at a given stress voltage, are independent of the peak nitrogen concentration of the SiON film. This indicates that plasma nitridation is a more reliable method for incorporating nitrogen in the gate oxide.

Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details.

Quantitative study of charge trapping in SiO 2 during bipolar Fowler–Nordheim injection

This work deals with the programming window closure observed in electrically erasable programmable read only memories as the number of write/erase cycles increases. This aging phenomenon is attributed to the build-up of oxide charge in the tunnel area. Capacitance–voltage and current–voltage measurements on 8.5 nm thick oxide MOS capacitors performed after constant current Fowler–Nordheim (FN) stresses showed interface states generation at both the anode and the cathode. A linear build-up of ‘slow’ states with the total injected charge was also observed at the cathode. Bulk oxide trapped charge and normalized centroid were deduced from the DiMaria technique. The bulk oxide charge build-up after FN stress is shown to follow a power law as a function of injected electron density over several decades. The charging kinetics have been explained by two components: trapping by native and generated traps. We have determined the different trap parameters (densities, capture cross-sections, generation rates and locations). By varying the stress current (polarity and density), we have noticed that the change in generated trap parameters is linear with the stress bias. We take finally a particular interest in the cumulating effects of different stresses. To our knowledge, such a complete study is absent from the literature and has to be done to predict the charge trapping kinetics due to non-constant stress which occur during memory write and erase operations.