Buffered Oxide Etch Research Articles

Mechanism Governing Surface Roughening of Al Ion Implanted 4H-SiC during Annealing under a C-Cap

Encapsulating SiC with a carbon layer (C-cap) is a widely used technique to avoid step bunching during post implantation annealing. In this work we propose a mechanism that explains the roughening that the surface unavoidably undergoes during annealing under the C-cap. We investigated the reactions occurring at the interface between 4H-SiC and the C-cap by scanning electron microscopy, energy-dispersive X-ray spectroscopy, and atomic force microscopy carried out at different stages of the sample processing: just after annealing, after C-cap removal in dry Oxygen, and after cleaning in buffered oxide etch solution. Our observations show that, even though the C-cap roughens for increasing annealing temperature and time, it is not visibly damaged even after 1950 °C 30 min annealing. After the C-cap removal the 4H-SiC surface was covered by a network of clusters that are eventually removed by buffered oxide etch solution. This occurrence suggests that, during the post-implantation annealing, the 4H-SiC surface decomposes and the escaped Si and C atoms are trapped inside the C-cap or at the interface between 4H-SiC and the C-cap. While C clusters are etched off in the dry O2 atmosphere, the Si clusters oxidize and form SiO2 nanoparticles which are finally etched by buffered oxide etch.

Low-Temperature PECVD Growth of Germanium for Mode-Locking of Er-Doped Fiber Laser.

A low-temperature plasma-enhanced chemical vapor deposition grown germanium (Ge) thin-film is employed as a nonlinear saturable absorber (SA). This Ge SA can passively mode-lock the erbium-doped fiber laser (EDFL) for soliton generation at a central wavelength of 1600 nm. The lift-off and transfer of the Ge film synthesized upon the SiO2/Si substrate are performed by buffered oxide etching and direct imprinting. The Ge film with a thickness of 200 nm exhibits its Raman peak at 297 cm−1, which both the nanocrystalline and polycrystalline Ge phases contribute to. In addition, the Ge thin-film is somewhat oxidized but still provides two primary crystal phases at the (111) and (311) orientations with corresponding diffraction ring radii of 0.317 and 0.173 nm, respectively. The nanocrystalline structure at (111) orientation with a corresponding d-spacing of 0.319 nm is also observed. The linear and nonlinear transmittances of the Ge thin-film are measured to show its self-amplitude modulation coefficient of 0.016. This is better than nano-scale charcoal and carbon-black SA particles for initiating the mode-locking at the first stage. After the Ge-based saturable absorber into the L-band EDFL system without using any polarized components, the narrowest pulsewidth and broadest linewidth of the soliton pulse are determined as 654.4 fs and 4.2 nm, respectively, with a corresponding time–bandwidth product of 0.32 under high pumping conditions.

High-efficiency black silicon tunnel oxide passivating contact solar cells through modifying the nano-texture on micron-pyramid surface

Optical loss is a significant factor restricting the conversion efficiency of conventional bifacial tunnel oxide passivating contact (TOPCon) solar cells. Black silicon structure is commonly used to enhance the photogenerated current density ( J ph ) of crystalline solar cells due to its excellent light-trapping capability. However, the photogenerated current gain is cancelled by the increased emitter recombination current originated from the black silicon structure with a high enhanced surface area ratio. In this work, we used a buffered oxide etching solution to modify the surface morphology of nanopore/micron-pyramid composite (NPP) structure silicon. Further, we studied the effects of NPP structures with different enhanced surface area ratio on front-side reflection, boron atom doping, emitter passivation, and cell performance. By identifying the appropriate surface modification processing, we fabricated the large-scale (158.75 mm × 158.75 mm) bifacial TOPCon solar cells using industrial equipment and processes with an average short-circuit current density of 41.12 mA/cm 2 and average conversion efficiency of 23.08%. Through adequately widening nanostructure size and depositing high-quality Al 2 O 3 /SiN x stacked passivation films on NPP structure surface, we achieved lower carrier recombination while maintaining high J ph . • Conversion efficiency of 23.2% achieved by b-Si TOPCon solar cells. • Surface modification of b-Si improves emitter passivation using buffer etching. • Medium specific area of b-Si achieve a balance of light-trapping and electrical loss.

High-performance normally-off recessed tri-gate GaN MIS-FETs in micrometer scale

In this study, a normally-off AlGaN/GaN metal–insulator–semiconductor field-effect transistor (MIS-FET) based on the combination of tri-gate and recessed MIS gate is fabricated and characterized. The recessed tri-gate MIS-FET is manufactured by micro-level trenches, defining the fin-shaped channel and improving the gate control capability. The recessed surface is cleaned by a diluted buffered oxide etch, HCl solution, and tetramethylammonium hydroxide treatment before a 20 nm Al2O3 deposition by atomic layer deposition. After deposition, post-deposition annealing was carried out. Recessed tri-gate MIS-FET demonstrates a high threshold voltage of 3.1 V, a high drain current of 1121 mA mm−1, and an on/off current ratio of 2 × 108. A smaller on-resistance of 5.4 Ω mm compared with recessed planar MIS-FET of 12.7 Ω mm is achieved. Besides, the devices show a low I–V hysteresis. All experimental results confirm micro-level trenches realize the advantages of the recessed tri-gate structures, which supports a promising technique to pursue the normally-off operation of GaN high electron mobility transistors.

Dendritic Forest-Like Ag Nanostructures Prepared Using Fluoride-Assisted Galvanic Replacement Reaction for SERS Applications.

Dendritic forest-like Ag nanostructures were deposited on a silicon wafer through fluoride-assisted galvanic replacement reaction (FAGRR) in aqueous AgNO3 and buffered oxide etchant. The prepared nanostructures were characterized using scanning electron microscopy, energy-dispersive X-ray spectroscopy, inductively coupled plasma–optical emission spectroscopy, a surface profiler (alpha step), and X-ray diffraction. Additionally, the dendritic forest-like Ag nanostructures were characterized using surface-enhanced Raman scattering (SERS) when a 4-mercaptobenzoic acid (4-MBA) monolayer was adsorbed on the Ag surface. The Ag nanostructures exhibited intense SERS signal from 4-MBA because of their rough surface, and this intense signal led to an intense local electromagnetic field upon electromagnetic excitation. The enhancement factor for 4-MBA molecules adsorbed on the Ag nanostructures was calculated to be 9.18 × 108. Furthermore, common Raman reporters such as rhodamine 6G, 4-aminothiolphenol, 5,5′-dithiobis-2-nitrobenzoic acid, and carboxyfluorescein (FAM) were characterized on these dendritic forest-like Ag nanostructures, leading to the development of an ultrasensitive SERS-based DNA sensor with a limit of detection of 33.5 nM of 15-mer oligonucleotide.

The Effect of Doping on the Digital Etching of Silicon-Selective Silicon-Germanium Using Nitric Acids.

Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at the 3 nm technology node and beyond. Isotropic etching of silicon–germanium (SiGe) for the definition of nano-scale channels in vertical GAA CMOS and tunneling FETs has attracted more and more attention. In this work, the effect of doping on the digital etching of Si-selective SiGe with alternative nitric acids (HNO3) and buffered oxide etching (BOE) was investigated in detail. It was found that the HNO3 digital etching of SiGe was selective to n+-Si, p+-Si, and intrinsic Si. Extensive studies were performed. It turned out that the selectivity of SiGe/Si was dependent on the doped types of silicon and the HNO3 concentration. As a result, at 31.5% HNO3 concentration, the relative etched amount per cycle (REPC) and the etching selectivity of Si0.72Ge0.28 for n+-Si was identical to that for p+-Si. This is particularly important for applications of vertical GAA CMOS and tunneling FETs, which have to expose both the n+ and p+ sources/drains at the same time. In addition, the values of the REPC and selectivity were obtained. A controllable etching rate and atomically smooth surface could be achieved, which enhanced carrier mobility.

Selective Digital Etching of Silicon-Germanium Using Nitric and Hydrofluoric Acids.

A digital etching method was proposed to achieve excellent control of etching depth. The digital etching characteristics of p+-Si and Si0.7Ge0.3 using a combination of HNO3 oxidation and buffered oxide etching oxide removal processes were investigated. Experimental results showed that oxidation saturates as time goes on because of low activation energy and its diffusion-limited characteristic. An oxidation model was developed to describe the wet oxidation process with nitric acid. The model was calibrated with experimental data, and the oxidation saturation time, final oxide thickness, and selectivity between Si0.7Ge0.3 and p+-Si were obtained. In Si0.7Ge0.3/p+-Si stacks, the saturated relative etched depth per cycle was 0.5 nm (four monolayers), and variation between experiments was about 4% after saturation. A corrected selectivity calculation formula was also proposed, and the calculated selectivity was 3.7-7.7 for different oxidation times, which was the same as the selectivity obtained from our oxidation model. The proposed model can be used to analyze process variations and repeatability, and it can provide credible guidance for the design of other wet digital etching experiments.

Development of Catalytic-CVD SiNx Passivation Process for AlGaN/GaN-on-Si HEMTs

We optimized a silicon nitride (SiNx) passivation process using a catalytic-chemical vapor deposition (Cat-CVD) system to suppress the current collapse phenomenon of AlGaN/GaN-on-Si high electron mobility transistors (HEMTs). The optimized Cat-CVD SiNx film exhibited a high film density of 2.7 g/cm3 with a low wet etch rate (buffered oxide etchant (BOE) 10:1) of 2 nm/min and a breakdown field of 8.2 MV/cm. The AlGaN/GaN-on-Si HEMT fabricated by the optimized Cat-CVD SiNx passivation process, which had a gate length of 1.5 μm and a source-to-drain distance of 6 μm, exhibited the maximum drain current density of 670 mA/mm and the maximum transconductance of 162 mS/mm with negligible hysteresis. We found that the optimized SiNx film had positive charges, which were responsible for suppressing the current collapse phenomenon.

Buffered Oxide Etchant Post-Treatment of a Silicon Nanofilm for Low-Cost and Performance-Enhanced Chemical Sensors.

The high surface-to-volume ratio of nanostructured materials is the key factor for excellent performance when applied to chemical sensors. In order to achieve this by a facile and low-cost fabrication strategy, buffered oxide etchant (BOE) treatment of a silicon (Si)-based sensor was proposed. An n+-n--n+ Si nanofilm structure was treated with a BOE, and palladium nanoparticles (PdNPs) were coated on the n-type Si channel surface via short-time electron beam evaporation to enable a highly sensitive and selective sensing of hydrogen (H2) gas. The BOE treatment effect on lightly doped n-type Si was investigated, and the surface morphology of the etched Si was analyzed. Furthermore, the H2 sensing characterization of PdNP-decorated Si devices with various BOE treatment times was systematically evaluated at room temperature. The results revealed that the surface of n-type Si is roughened by BOE treatment, which can further enhance the H2-sensing performance of Pd-decorated Si. The elaborate study on the BOE-post-treated Si H2 sensor showed that the performance enhancement was stable. The BOE treatment strategy was also applied to the nanopatterned Si sensors, which induced a clear performance enhancement for the H2 sensing.

Study of Isotropic and Si-Selective Quasi Atomic Layer Etching of Si1−xGex

The lateral and vertical gate-all-around (GAA) field-effect transistors are considered the most promising candidates for next generation logic device at and beyond 3-nm technology node. SiGe plays an important role in these devices as the sacrificial layer or channel material and needs isotropic etching. In this paper, an advanced etching process termed quasi atomic layer etching (qALE) is developed with advantages of controllable etch rate and atomically smooth surfaces. The qALE of SiGe is based on wet chemical etching, in which H2O2 is applied to oxidate the surface with cyclic manner, and diluted buffered oxide etchant (dBOE) is applied to remove the oxide. The profiles of SiGe qALE for quasi-self-limited behavior, etch rate and the effect in concentration and temperature of H2O2 have been studied. The etch per cycle (EPC) of Si0.7Ge0.3 is 0.50 nm and the etching selectivity between Si0.7Ge0.3 and heavily p-type doped silicon is 4.99 in Si/SiGe/Si stacked layers with (110) sidewall. The etch rate and the selectivity are influenced by Ge fraction of SiGe and the boron doping in Si. The root mean square (RMS) roughness after 60 cycles qALE is 0.183 nm indicating atomically smooth surfaces. Finally, the application of qALE for vertical nanowire compared with wet continuous etching is discussed in this work.

Impact of Surface Treatments and Post-Deposition Annealing Upon Interfacial Property of ALD-Al₂O₃ on a-Plane GaN

Optimization of interface characteristics between dielectric and non-polar GaN surface is very important and urgent for vertical GaN MOS device whose channel is perpendicular to the conventional cplane. In this work, the effects of piranha cleaning and N2 post deposition annealing (PDA) to the interface between atomic-layer-deposited (ALD)-Al 2 O 3 and a-plane GaN samples were comprehensively investigated by X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM) and photo-assisted capacitance-voltage (C-V) measurements. The piranha cleaning and N2 annealing can improve interface characteristics through the reduction in surface roughness and Ga-O bonds, respectively. Therefore, the frequency dispersion and hysteresis are nearly suppressed with a low interface trap quantity (Qit) of 4.1 x 10 11 cm -2 and a low average interface state density (Dit) of 2.04 x 10 11 cm -2 ·eV -1 from photoassisted C-V measurements, showing the great promise of utilizing piranha pretreatment, buffered oxide etch (BOE) dip, and N 2 annealing as an effective route to improve the vertical GaN MOS interface properties.

Plated metal adhesion to picosecond laser-ablated silicon solar cells: Influence of surface chemistry and wettability

This study investigated the influence of UV picosecond laser fluence, used to ablate the SiNx antireflection coating for Ni/Cu/Ag plated p-type Si solar cells, on busbar and finger adhesion and cell electrical performance. Surface chemistry was characterised post-ablation and post-pre-treatment in 7:1 buffered oxide etch (BOE) using a combination of X-ray photoelectron spectroscopy and contact angle measurements. Although growth of laser-induced Si oxides increases with increasing laser fluence, these oxides are effectively removed in the BOE pre-treatment and therefore do not impact plated metal adhesion with busbar pull forces of 1.9 ± 0.7 N/mm being achieved when a laser fluence of 0.63 J/cm2 was used to ablate the busbar openings. It is also revealed that the use of high laser fluence leads to a more hydrophobic surface due to reduced residual SiNx, however the complete wetting of the ablated Si surface can be ensured by the use of surfactants in Ni plating electrolytes. Residual SiNx impacts Ni silicidation and reduces the busbar pull force to values of only 0.8 ± 0.5 N/mm when average laser fluences ≤0.45 J/cm2 are used. Finger dislodgement forces are interestingly shown not to be affected by laser fluence and presence of residual SiNx, providing an opportunity to optimise the laser ablation process separately for finger and busbar openings. Finally, it is demonstrated that the use of higher laser fluences does not impact the electrical performance of the Al back surface field cells, with open-circuit voltages of ≥637 mV and fill factors ≥80.4% being demonstrated for cells where the average laser fluence used was varied between 0.35 and 0.63 J/cm2.

Study of surface over-layer contribution to Dislocation Assisted Tunneling current: Strategy to improve Pt/n+–GaN Schottky characteristics

This paper reports the importance of surface over-layer contribution to the dislocation assisted tunnelling (DAT) current along with earlier reported bulk dislocations due to growth of GaN layers on highly lattice-mismatched substrates. This claim is substantiated by demonstrating an improved Pt/n+–GaN Schottky diode characteristics with the removal of surface over-layer. This is achieved by treating the n+–GaN layers with Buffered Oxide Etchant (BOE) before Pt deposition. The improvements are observed in three crucial aspects of Pt/n+–GaN Schottky diode namely turn-on voltage (Vt); dislocation assisted tunnelling (DAT) parameter (E0), and reverse bias current. These improvements are achieved by treating n+–GaN surface with 1:7 BOE before Pt deposition. The DAT model adequately explains the device characteristics. Further, the dislocation density used in DAT analysis is experimentally quantified using HR-XRD. The removal of Ga2O3 and significant blue shift of Ga 3d peaks by 0.6 eV post-treatment as observed in XPS measurements, results in improved conduction of electrons at the n+–GaN surface and Pt/n+–GaN device characteristics.

Combined method for the fabrication of high-power cladding light stripper using a buffered oxide etchant.

Cladding light strippers (CLSs) are vital and one of the critical components for high-power fiber laser applications. In this study, we show the first studies of the formation mechanisms and optimum conditions of a CLS device using a buffered oxide etchant by a combined method of stain (wet) etching and vapor-phase etching. This high-power CLS was shown to result in a stripping performance of ∼17.2 dB at the launched power of 333W (pump limited). The thermal imaging demonstrates that the maximum temperature reached when operating the device at maximum launched power was ∼75°C. The atomic force microscopy (AFM) results show that the combined method yields crystal-like structures with the height in microscales, whereas other conventional methods give only nanoscale roughness. The method also preserves the diameter of the CLS device close to the bare fiber with about 10μm tapering leads to a high surface area to strip unwanted light, which is good for heat dissipation. The combined method possesses the outcome of two methods, including both the crystal-like structures and nanosized hillocks, resulting in high-power stripping performance and robustness.

Atomic layer deposition growth of SnS2 films on diluted buffered oxide etchant solution-treated substrate

In this report, two types of substrates were prepared for deposition of few-layer tin disulfide (SnS2) via atomic layer deposition (ALD). The first substrate was prepared using a conventional cleaning method, while the second substrate was rinsed with buffered oxide etcher (BOE) solution after conventional cleaning. Changes in the substrate were confirmed by X-ray photoelectron spectroscopy, contact angle measurements, and electron spin resonance. Characteristics of the SnS2 thin films were determined by X-ray diffraction, Raman analysis, Fourier transform-infrared spectroscopy, atomic force microscopy, and X-ray photoelectron spectroscopy. To investigate growth rate, thickness was measured as a function of ALD cycle number by atomic force microscopy, and 2D layered structure was confirmed by transmission electron microscopy. Findings confirmed that surface treatment using BOE solution was related to an increased growth rate during the initial ALD process. Finally, back-gate field effect transistors based on ALD-grown SnS2 film prepared on substrate that received diluted-BOE surface treatment showed marginal improvement in current on/off ratio from 2.9 × 105 to 6.5 × 105 and mobility from 0.22 cm2/Vs to 0.31 cm2/Vs compared to ALD-grown SnS2 film prepared on bare substrate.

Clean Transfer of 2D Transition Metal Dichalcogenides Using Cellulose Acetate for Atomic Resolution Characterizations

Atomically thin two-dimensional (2D) transition metal dichalcogenides (TMDs) can be easily synthesized on SiO2/Si substrates by chemical vapor deposition (CVD). However, for practical applications, those 2D crystals usually need to be retrieved and placed onto target substrates. Hence, a robust and effective transfer process is required. Currently, the most widely used approach for transferring CVD-grown TMDs involves the spin-coating of a poly(methyl methacrylate) (PMMA) support layer, followed by the wet etching of the SiO2 layer in hot NaOH. This transfer process often causes substantial accumulation of polymer residues as well as severe structural damage of TMDs induced during the etching of substrates at elevated temperatures. In this work, we present an alternative approach for the transfer of CVD-grown TMDs that can address the issues mentioned above. In this process, we replaced PMMA with cellulose acetate (CA) as a support layer and used buffered oxide etch (BOE) as an effective room-temperature ...

The Hybrid Fabrication Process of Metal/Silicon Composite Structure for MEMS S&A Device.

The micro-electromechanical system (MEMS) safety-and-arming (S&A) device has the features of integration and miniaturization, which is one of the important directions of weapon development. Confined by the fabrication process, the silicon-based devices are too fragile, and the metal-based devices are low precision. In order to solve the contradiction between high precision and high structure strength, a metal/silicon composite structure is proposed in this paper, and a hybrid fabrication process is introduced. This new method mainly consists of metal sputtering, electroplating, and (inductively–coupled-plasma) ICP etching. As the resolution of the thick dry film is limited, the process of a femtosecond laser is applied to refine the structure, and the Ni plate (a block of 1 mm × 3 mm × 0.3 mm with a cavity of ϕ 0.85 mm × 0.3 mm in the center) is fabricated on the silicon-on-insulator (SOI) wafer successfully. After the double sides are etched by ICP, the SOI wafer is immersed in a buffered-oxide-etch (BOE) etchant to remove the buried layer. The cover plate acts as the encapsulation and is bonded with the SOI wafer by the epoxy glue. Then, the temporary support beam of the device is broken by the probe, and the suspended composite structure can be fully released. The hybrid process is the integration of the silicon-based process and the metal-based process, which can combine the advantages of both high precision and a high structure strength. The process proposed here is suitable for the application of weapon miniaturization.

A Triode Device with a Gate Controllable Schottky Barrier: Germanium Nanowire Transistors and Their Applications.

Electrical contacts often dominate charge transport properties at the nanoscale because of considerable differences in nanoelectronic device interfaces arising from unique geometric and electrostatic features. Transistors with a tunable Schottky barrier between the metal and semiconductor interface might simplify circuit design. Here, germanium nanowire (Ge NW) transistors with Cu3 Ge as source/drain contacts formed by both buffered oxide etching treatments and rapid thermal annealing are reported. The transistors based on this Cu3 Ge/Ge/Cu3 Ge heterostructure show ambipolar transistor behavior with a large on/off current ratio of more than 105 and 103 for the hole and electron regimes at room temperature, respectively. Investigations of temperature-dependent transport properties and low-frequency current fluctuations reveal that the tunable effective Schottky barriers of the Ge NW transistors accounted for the ambipolar behaviors. It is further shown that this ambipolarity can be used to realize binary-signal and data-storage functions, which greatly simplify circuit design compared with conventional technologies.

Functional Iron Oxide (Fe2O3) Nanoparticles Based Gas Sensor Operating at High Temperature

The highly responsive gas sensor based on a metal-oxide-semiconductor (MOS) configuration which is conformally coated with iron oxide (Fe2O3) nanoparticles is hereby designed, fabricated, and systematically characterized for this study. The iron oxide nanoparticles are prepared by mixing altogether the respective amounts of FeCl2-4H2O, FeCl3-6H2O, and NaOH in terms of different molar ratios. The iron oxide overcoated gas sensor thus fabricated has been electronically probed in an ecnclosed chamber under a high temperature condition during which the different gases are fed in individually and selectively. The presence of a perticular gas is duly sensed by monitoring the changing magnitude of the current extracted from the sensor. The enhanced sensitivity of the MOS-based sensor overlaid with the Fe2O3 nanoparticles is attributed to a large surface area typically associated with nanoscale particles. The fabrication of MOS-based sensor is entirely CMOS compatible and can be summarized as follows. First, the 400μm-thick silicon wafer is first RCA cleaned and then both sides of the wafer are coated with 800nm-thick oxide layer using high pressure oxidation furnace. Next, a series of photolithographic steps followed by electron-beam-evaporated titanium lift-off is implemented to realize the heater pattern. Afterward, the resultant heater pattern is overcoated with a 400nm-thick oxide layer using plasma-enhanced chemical vapor deposition (PECVD). In order to open up an area for the subsequent deposition of iron oxide nanoparticles-embedded material while leaving the titanium heater protected by the same oxide layer, necessary photolithographic and buffered oxide etching (BOE) steps are performed. Finally, the interdigitated electrodes are deposited followed by injecting the viscous Fe2O3 nanoparticles-embedded solution over the electrodes. Once the sensor is successfully fabricated, the very sensor is placed on a temperature-controlled sample platform maintained at a desired temperature within an enclosed chamber. The entire sensor characterization is performed at a temperature of 300 degree Celsius. The operating mechanism of the sensor is intimately dependent on the oxidation-reduction reaction between the injected gas and Fe2O3 nanoparticles-embedded sensing film. As can be shown in the follwoing figure, the ethanol (C2H5OH) gas vapor is functioned as a reducing agent, while nitrogen dioxide (NO2) gas, on the other hand, is behaved as a oxidizing agent instead. As ethanol gas vapor is injected, the oxygen ions of the ethanol produced at high temperature is converted back to the neutral oxygen atom while releasing the captured electrons back to to the iron oxide sensing film, thereby causing the detected current to go up. On the other hand, nitrogen dioxide is behaved as an oxidizing agent instead by oxidizing the Fe2O3 film and grabbing the electrons away, thereby causing the detected current to drop in response to the presence of the NO2 gas vapor. Consequently, the reversing current-versus-time patterns associated with C2H5OH and NO2, as shown in the follwing figure, are thus detected, which verify the different oxidation-reduction mechanisms associated with these two different gases. The optimization in the design of the iron oxide nanoparticles coated sensor in order to enhance the sensitivity and the response time in the detection of the different gases is currently being pursued and the subsequent experimental results obtained will be reported in the upcoming 235th ECS conference. Figure 1

High density GaAs nanowire arrays through substrate processing engineering

GaAs nanowires (NWs) vertically aligned were successfully fabricated through substrate processing engineering. High-density vertical GaAs NWs are grown on n-type Si (111) substrate by molecular beam epitaxy. Systematic experiments indicate that substrate pretreatment is crucial to vertical epitaxial growth of one-dimensional (1D) nanomaterials. The substrates etched using diluted buffered oxide etch (BOE) were explored to improve the NW density and vertical. We also find that the substrate processing engineering strongly affect the morphology of GaAs NWs. Finally, we demonstrate fabrication of GaAs NW arrays on Si surface by field-emission scanning electron microscopy (FE-SEM). This single-step process indeed offers a simple and cost-effective way to obtain a large area of GaAs NW arrays without using e-beam lithography (EBL) and/or nanoimprint lithography (NIL) processes. This work provided a new approach for hight density NW arrays.