Bucket-brigade Devices Research Articles

A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing

A low-power pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) using boosted bucket-brigade device (BBD) for residue charge processing is presented. Boosted BBDs have been used as low-power and high-precision residue charge transfers in multistage pipelined ADCs, with drawbacks of large nonlinearity and severe accumulated common-mode (CM) charge error, which requires power-hungry real-time calibration circuits to control the CM level in each stage. When used in a two-stage pipelined-SAR ADC, only one boosted BBD pair is needed and its input signal range is attenuated remarkably by the first-stage SAR. Thus, zero-power power-up correction circuit can be used to stabilize the output CM level, and the nonlinear error of the boosted BBD is negligible. In addition, with top-plate sampling in the first-stage SAR, two reference voltages for the conventional BBD are also eliminated. A proof-of-principle 10-bit two-stage pipelined-SAR ADC is implemented in a 0.18- $\mu \text{m}$ CMOS, showing an signal-to-noise-and-distortion ratio/spurious-free dynamic range of 57.1 dB/71.4 dB at 3.1-MHz input, while consuming 1.87 mW at 40 MS/s for a figure of merit of 78.9 fJ/step. The boosted BBD residue circuit consumes only 0.06 mW or 3% of the total power.

Low-order continuous-time robust repetitive control: Application in nanopositioning

A low-order repetitive control (RC) design in continuous-time for nanopositioning applications is presented. It focuses on achieving high performance and sufficient robustness to uncertainties. The design is mainly applicable to analog implementation, but due to the exceptionally low order, it also results in a fast and efficient digital implementation. Experimental results for an analog implementation using a bucket brigade device (BBD), as well as a digital implementation, is presented. RC can provide fast and accurate tracking of periodic reference signals, which is useful in many scanning probe microscopy and nanofabrication applications.

A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit**Project supported by the National Natural Science Foundation of China (No. 61106027).

A low power 10-bit 250 MSPS charge-domain (CD) pipelined analog-to-digital converter (ADC) is introduced. The ADC is implemented in MOS bucket-brigade devices (BBDs) based CD pipelined architecture. A replica controlled boosted charge transfer (BCT) circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process. The ADC achieves an SFDR of 64.4 dB, an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is +0.5/ −0.55 LSB and INL is +0.8/ −0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.

Analog Robust Repetitive Control for Nanopositioning Using Bucket Brigade Devices

In many applications of nanopositioning, such as scanning probe microscopy, tracking fast periodic reference trajectories with high accuracy is highly desirable. Repetitive control is a simple and effective control scheme to obtain good tracking of such reference trajectories. In order to implement repetitive control, a method for introducing time-delay is necessary. This can easily be implemented using a memory buffer with digital signal processing equipment. To achieve fast, high accuracy, and low noise performance, fast microcontrollers or field-programmable gate array hardware with fast high-resolution analog-to-digital and digital-to-analog converters are needed. As an inexpensive alternative to digital signal processing, the use of an analog bucket brigade device to implement the time-delay is investigated in this paper. Bucket brigade devices use switching to carry the input voltage over an array of capacitors, achieving a specified time-delay. Low-noise bucket brigade devices can achieve a signal-to-noise ratio around 80 dB, comparable to the actual performance when using 16-bit analog-to-digital converters. In this paper, the proposed control scheme utilizes a modified integral control law in conjunction with the repetitive control law. The overall control scheme ensures robustness towards plant uncertainty. Experimental results demonstrate the effectiveness of the overall control scheme and the analog implementation.

A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

A 10-bit 250-MSPS two-channel time-interleaved charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented. MOS bucket-brigade device (BBD) based CD pipelined architecture is used to achieve low power consumption. An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter. A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability. The ADC achieves a spurious free dynamic range (SFDR) of 67.1 dB, signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input, and SFDR of 61.6 dB, SNDR of 52.6 dB for a 355 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/−0.4 LSB and integral nonlinearity (INL) is +0.8/−0.75 LSB. Fabricated in a 0.18-μm 1P6M CMOS process, the prototype 10-bit pipelined ADC occupies 1.8 × 1.3 mm2 of active die area, and consumes only 68 mW at 1.8 V supply.

A 27-mW 10-bit 125-MSPS charge domain pipelined ADC with a PVT insensitive boosted charge transfer circuit

A low power 10-bit 125-MSPS charge-domain (CD) pipelined analog-to-digital converter (ADC) based on MOS bucket-brigade devices (BBDs) is presented. A PVT insensitive boosted charge transfer (BCT) that is able to reject the charge error induced by PVT variations is proposed. With the proposed BCT, the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably. The prototype ADC based on the proposed BCT is realized in a 0.18 μm CMOS process, with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm2. The prototype ADC achieves a spurious free dynamic range (SFDR) of 67.7 dB, a signal-to-noise ratio (SNDR) of 57.3 dB, and an effective number of bits (ENOB) of 9.0 for a 3.79 MHz input at full sampling rate. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.5/−0.3 LSB and +0.7/−0.55 LSB, respectively.

Development of BBD Adding-Delay Architecture for Ultrasonic Micro Array Sensor

Bucket Brigade Device (BBD) adding-delay architecture was proposed as the analog beamformer for piezoelectric micromachined ultrasonic sensor phased array. BBD adding-delay architecture were used both as delay and adding elements, and the input signals were distributed adding in the process of delay. This architecture was useful to reduce chip area, simplify system design, and realize on-chip integration. Combining piezoelectric micromachined ultrasonic array sensors and the analog delay-sum circuits successfully performed two-dimensional object detection.

Pipelined delay-sum architecture based on bucket-brigade devices for on-chip ultrasound beamforming

A pipelined delay-sum architecture based on bucket-brigade devices is proposed as an analog beamformer for integrated far-field steering scanning of a micromachined piezoelectric ultrasonic sensor phased array. The prototype beamformer, fabricated with an 8-/spl mu/m standard CMOS process, exhibits a total harmonic distortion of -45 dB, dynamic range of more than 65 dB, and beamforming imperfection of less than -50 dB using a 100-kHz input signal with peak voltage of 400 mV.

Front-end processor using BBD distributed delay-sum architecture for micromachined ultrasonic sensor array

Micromachined technology makes it possible to integrate the ultrasonic sensor with the front-end processing circuit together, and make an ultrasonic system smart, compact and low cost. An ultrasonic sensor array with resonant frequency of about 60 kHz is fabricated for airborne applications, using sol-gel derived Pb(Zr,Ti)O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> thin film and Si-based micromachining technique. The distributed delay-sum architecture based on a bucket brigade device (BBD) is employed for the beamforming of the sensor array in order to reduce chip area, simplify system design, improve power efficient and achieve monolithic integration. A charge attenuator is proposed to increase the dynamic range of the input signal and overcome the charge overflowing in bucket capacitors. A charge amplifier based preamplifier is used to interface the sensor array and beamformer. A prototype front-end processor shows good SNR with the dynamic range larger than 50 dB, and a beamforming performance consistent to the theoretical calculation very well.

Integrated analog beam former based on bucket brigade device for micromachined ultrasonic sensor array

Micromachined ultrasonic sensors are promising in the applications including medical imaging, non-destructive evaluation (NDE), ranging, and object detections. Bucket brigade device (BBD) was used as the analog beam former for piezoelectric micromachined ultrasonic sensor phased array. The works on the optimization of BBD, including improvement of the transfer efficiency and dynamic range, and simplification of system design were discussed in details. The parasitic insensitive approach was proposed to optimize the properties of BBD delay line, and measured results indicated that this approach achieved larger charge transfer efficiency, larger dynamic range, and higher frequency than the conventional BBD. Furthermore, the BBD distributed delay-sum architecture was proposed to reduce chip area, simplify system design, and achieve monolithic integration. The measured results indicated that BBD distributed delay-sum architecture showed the beam forming property that is consistent to the theoretical calculation very well.

Mixed-mode correlator for micropower acoustic transient classification

A mixed-mode very large scale integration (VLSI) processor for acoustic transient classification performs a running correlation between a time-frequency decomposed analog input signal and a corresponding template. Differential encoding of the inputs allows simplification of the multiply-and-accumulate operations, operating on binary templates and positive-valued inputs, implemented in current mode with eight MOS transistors per cell including SRAM template storage. The use of a bucket-brigade device (BED) instead of a charge-coupled device (CCD) for shift-and-accumulate operations allows long integration times necessary for acoustic transients spanning several hundred milliseconds. Correlated double sampling at the output compensates for dark current losses in the BED and other common-mode effects. The 64/spl times/16 time-frequency correlator measures 700 /spl mu/m/spl times/1170 /spl mu/m in a 1.2-/spl mu/m CMOS process and dissipates an average of 30 /spl mu/W in continuous operation.

Industrial CMOS technology for the integration of optical metrology systems (photo-ASICs)

With ‘photo-ASICs’ comprising light-sensitive structures, light-emitting devices and analog and digital circuits, complete optical metrology systems can be integrated on a single chip. We report the realization of key components of such photo-ASICs using an industrual IC CMOS process. We achieve photodiodes with an external quantum efficiency of 50–80% in the visible spectrum and position-sensitive devices (PSDs) with a spatial non-linearity of around 0.3%. We demonstrate surface-channel CCDs with a charge-transfer efficiency of 99.8% at room temperature, as well as bucket-brigade devices (BBDs) with a lower charge-transfer efficiency of 96%. Light-emitting diodes (LEDs) are realized, emitting infrared light at 1160 nm (forward biased) and broadband visible yellow light with a spectral maximum at 640 nm (reverse biased). We discuss simple applications of passive photo-ASICs, such as a centroid detector, a 3-D camera, a motion detector and a focus sensor, used to obtain a relative measure for the local focus of an optically imaged scene, for example, in a photographic camera.

Wire transfer of charge packets using a CCD-BBD structure for charge-domain signal processing

A structure for the virtual transfer of charge packets across metal wires is described theoretically and is experimentally verified. The structure is a hybrid of charge-coupled device (CCD) and bucket-brigade device (BBD) elements and permits the topological crossing of charge-domain signals in low power signal processing circuits. A test vehicle consisting of 8-, 32-, and 96-stage delay lines of various geometries implemented in a double-poly, double-metal foundry process is used to characterize the wire-transfer operation. Transfer efficiency ranging between 0.998 and 0.999 is obtained for surface n-channel devices with clock cycle times in the range from 40 ns to 0.3 ms. Transfer efficiency as high as 0.9999 is obtained for buried n-channel devices. Good agreement is found between experiment and simulation. >

Programmable transversal filter using BBD and dynamic amplifiers

A programmable transversal filter which is based on the combination of a bucket-brigade device (BBD) with a row of dynamic amplifiers is described. Since the dynamic amplifier operates around a virtual ground, negative signals can be handled without a decrease in dynamic range, and the DC output voltage is independent of the implemented filter function. The filter is a compact device requiring only low power.

Subthreshold current of dual-gate MOSFET's

The subthreshold conduction in dual-gate MOS transistors is investigated. The subthreshold current is calculated both in the long-channel case and the short-channel case by means of simple models. Good agreement is found between theory and experimental results obtained through measurements on overlapping-gate n-channel devices. As an application of the subthreshold current analysis, the low-frequency transfer inefficiency in bucket-brigade devices (BBD's) is evaluated. The theoretical result agrees well with measurements carried out on p-channel nonoverlapping-gate devices.

Stereo image separation and perimeter enhancement

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Directional response pattern simulator

Experiments designed to measure the directional response patterns of acoustic radiators and receivers have basically to be carried out in an anechoic room. If, however, a simulator capable of electrically imitating the real process of forming the directional response pattern is available, one can carry out a directional response determination whenever one wants to. The simulator described here uses a bucket brigade device (BBD) and other electronic components. A technique for describing the polar diagram of the directional response pattern is also discussed. Model experiments for obtaining the simple directional response patterns and for suppressing the side lobe can be successfully carried out with the aid of such a simulator.

An integrated real-time programmable transversal filter

Implementation, measurements, and characteristics of a fully integrated 32 tap real-time programmable transversal filter, which facilitates a number of filter applications, are discussed. It uses RAMs and 16 MDACs for tap weight programming and pipe organ structure to provide for a large variety of adaptive convolutional and correlative signal processing with optimum compromise among power dissipation, computational speed, size, and performance. The filter was constructed with the combined technology of bucket brigade devices and switched capacitors.

Wide dynamic range phase-comparator using an analogue shift register

A new phase-comparator using bucket brigade device (BBD) is proposed. It is composed of a conventional phase-comparator with a phase shifter using BBD in the feedback path. Its dynamic range is wider than that of the conventional phase-comparator. This phase-comparator will find many applications, such as a demodulator for the widely phase-modulated wave and a component for PLL.

Dual-gate bucket-brigade devices

The low charge-transfer efficiency of the basic bucket-brigade circuit and the speed limitation of the tetrode approach have so far prevented bucket-brigade devices (BBD's), in spite of their greater fabrication simplicity, from competing with charge-coupled devices, excepting for audio applications. A novel charge-transfer device is presented and experimentally evaluated. The "dual-gate BBD" is a two-step-transfer device (a CCD transfer followed by a BBD transfer), showing operational performances comparable to surface-channel CCD's and, at the same time, enjoying the fabrication simplicity proper to bucket-brigade circuits. The concept is implemented using conventional p-channel aluminum-gate technology combined with an additional shadowed-gap float-off process. The characteristic features and the performance capabilities of the device are discussed.