BT Stress Research Articles

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress.

This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors.

The effect of bias-temperature stress on Na+ incorporation into thin insulating films

The action of Na(+) incorporation into thin insulating films and transport therein under influence of a bias voltage and temperature (BT stress) is the subject of this work. Deposited onto highly n-doped Si wafers, the insulators get BT stressed and subsequently investigated by means of time-of-flight-secondary ion mass spectrometry (ToF-SIMS). A thin PMMA film, spin-coated onto the insulator, serves as host matrix for a defined amount of Na(+), provided via sodium triflate. Combining BT stress and ToF-SIMS depth profiling enables the unambiguous detection of Na(+), incorporated into the insulating material. The insulators of interest vary in their nitride content: SiO(2), SiO(x)N(y), and Si(3)N(4). For SiO(2), it is shown that once a threshold BT stress is exceeded, Na(+) gets quantitatively incorporated from PMMA into the underlying insulator, finally accumulating at the SiO(2)/Si interface. A quantitative assessment by combination of Butler-Volmer kinetics with hopping dynamics reveals activation energies of E(a) = 1.55 - 2.04 eV for Na(+) transport in SiO(2) with varying thickness. On the other hand, SiO(x)N(y) and Si(3)N(4) films show a different Na(+) incorporation characteristic in this type of experiment, which can be explained by the higher coordination of nitrogen and hence the reduced Na(+) permeability within these insulators.

Comparison of positive and negative bias-temperature instability on MOSFETs with HfO 2/LaO x and HfO 2/AlO x dielectric stacks

The modified charge-pumping (CP) techniques were applied to characterize the trap distribution as well as its related reliability problems for MOSFETs with HfO 2/LaO x and HfO 2/AlO x high-κ gate stacks. It is found that the positive bias temperature (PBT) and negative bias temperature (NBT) stresses would cause different kinds of traps generated at different locations. The negative bias causes even more damage than positive bias on nMOS devices. The generation of N it caused by BT stress is uniform through whole channel, no matter positive bias or negative bias. The generation of border trap ( N bt) caused by NBT stress is much more and deeper than that caused by PBT one.

Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks

We characterized how positive and negative bias temperature instabilities (PBTI and NBTI) occur in HfSiON gate stacks. The PBTI was confirmed to be suppressed by using amorphous (a-) HfSiON instead of crystallized (c-) HfSiON. The a-HfSiON reduced the capture cross-section and lowered the density of electron traps, which explains the suppression of the PBTI. The different trap parameters for a-HfSiON and c-HfSiON suggest that the electron traps of these structures have different origins. The PBTI of a-HfSiON gates occurred through electron trapping without generation of interface traps, while the NBTI of a-HfSiON gates occurred through generation of interface traps and positive oxide charges. Furthermore, it was found that the NBTI of a-HfSiON gates also involves electron trapping. Additionally, the subthreshold slope decreased under positive BT stress. We attribute these characteristic BTI behaviors of HfSiON gates to the influence of charge traps that are present within the HfSiON bulk.

An analytical method of evaluating variation of the threshold voltage shift caused by the negative-bias temperature stress in poly-Si TFTs

The variation of the threshold voltage shift (V/sub th/ shift) caused by negative-bias temperature stress (-BT stress) in poly-crystalline silicon thin-film transistors (poly-Si TFTs) was investigated. Based on the chemical reaction caused by -BT stress at the poly-Si/SiO/sub 2/ interface and the poly-Si grain boundary, an analytical method of evaluating the variation of both the V/sub th/ shift and the initial V/sub th/ was proposed. It was shown from this analysis that the enlargement of the poly-Si grain, using Si/sub 2/H/sub 6/ gas could be a solution for efficient reduction of the easily hydrogenated dangling bonds which resulted in the V/sub th/ shift and suppression of the V/sub th/ shift and its variation. Moreover, it was suggested that there are two kinds of the dangling bonds; one is hydrogenated by hydrogenation and can be dehydrogenated by -BT stress; the other is not hydrogenated and the variation of its density is much smaller than the former.

Performance and reliability improvements in poly-Si TFT's by fluorine implantation into gate poly-Si

High-performance and high-reliability TFT's have been obtained using a fluorine ion implantation technique. The fluorine implantation into the gate poly-Si of TFT caused a positive Vth shift, increased the ON current, and decreased the leakage current significantly. Our investigation indicates that the Vth shift originates from negative charges generated in the gate oxide by the fluorine implantation. The improvement of drain current is attributed to fluorine passivation of trap states in the poly-Si and to a modulation of offset potential due to the same negative charges under the offset region. Furthermore, high immunity against the -BT stress and TDDB of the gate oxide was achieved by the fluorine implantation. It is considered that the strong Si-F bonds created by the fluorine implantation raise the stress immunity.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Long-term bias temperature reliability of P/sup +/ polysilicon gated FET devices

An instability was found to be associated with +BT stress for P/sup +/ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N/sup +/ poly-gated devices (NNMOS and NPMOS). The instability with the P/sup +/ poly-gated devices, which is a decrease in threshold voltage (V/sub t/) and an increase in interface state density (D/sub it/), was significantly reduced following N/sub 2/ annealing at 400/spl deg/C. It is shown that adequate reliability for P/sup +/ poly-gated devices can be achieved for VLSI technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Mechanism of negative-bias temperature instability in polycrystalline-silicon thin film transistors

It is found that 0.1 V-order threshold voltage shift (Vth shift) takes place in polycrystalline-silicon thin film transistors during negative-bias temperature stress (−BT stress), while the Vth shift in the case of positive-bias temperature stress is negligibly small. The Vth shift caused by −BT stress has an exponential dependence on the stress gate bias and reciprocal of temperature. Moreover, it also has a close relation with the grain size of poly-Si films and the hydrogenation process. However, it is independent of the gate insulator materials. Some models previously proposed for amorphous silicon TFTs could not explain these results. A new model is proposed based on a reaction between hydrogen and the SiO2 network at and near the poly-Si/SiO2 interface to clarify the mechanism and for consistent interpretation of the experimental results. Furthermore, the model has been verified qualitatively.

Anomalous Leakage Current of MOSFET's under BT Stress

It is observed that the leakage current caused by BT stress decreases under further BT stress for both the n- and p-channel Si-gate MOSFET's without channel stoppers. This anomalous effect is explained by a new surface conduction model with a different boundary condition resulting from a thin SiO2 film on the gate electrode. For +BT stress of n-channel devices, for instance, a positive charge spreads at the PSG-SiO2 interface by ionic conduction, but negative ions accumulate on the SiO2 film on the gate electrode. The electrostatic potential in the vicinity of the gate electrode is not constant but decreases with BT stress, in contradiction to the conventional surface conduction model.