Abstract
The modified charge-pumping (CP) techniques were applied to characterize the trap distribution as well as its related reliability problems for MOSFETs with HfO 2/LaO x and HfO 2/AlO x high-κ gate stacks. It is found that the positive bias temperature (PBT) and negative bias temperature (NBT) stresses would cause different kinds of traps generated at different locations. The negative bias causes even more damage than positive bias on nMOS devices. The generation of N it caused by BT stress is uniform through whole channel, no matter positive bias or negative bias. The generation of border trap ( N bt) caused by NBT stress is much more and deeper than that caused by PBT one.
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