BSIM4 Model Research Articles

Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes

With rapid technology scaling, the leakage dissipation that begins to replace dynamitic dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold leakage current in nanometer CMOS processes. This paper introduces a MTCMOS power-gating technique, which is used for an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) to reduce leakage dissipation in sleep mode. A 32 X 32 single-phase adiabatic register file are verified using HSPICE in different processes, threshold voltage, and active ratios, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are greatly reduced.

An Adiabatic Register Based on Dual Threshold Leakage Reduction Technique

This paper introduces a leakage reduction technique using dual threshold CMOS in CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The leakage current source of the CPAL circuits is analyzed under nanometer CMOS processes. A 32 X 32 CPAL register file is demonstrated using the proposed dual threshold technique. In the proposed register file, the logic gates on critical path use low threshold transistors, while the other logic gates use dual threshold technique to reduce their leakage dissipations. All circuits are verified using HSPICE in different processes, threshold voltages, and operation frequencies, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are obviously reduced both in active mode and idle mode.

Compact and Distributed Modeling of Cryogenic Bulk MOSFET Operation

We have developed compact and physics-based distributed numerical models for cryogenic bulk MOSFET operation down to 20 K to advance simulation and first-pass design of device and circuit operation at low temperatures. To achieve this, we measured and simulated temperature-dependent current-voltage characteristics of 0.16- and 0.18- bulk MOSFETs. Our measurements indicate that these MOSFETs supply approximately 40% more current in the saturation and linear regions of operation when they are cooled from room temperature to 20 K. The threshold voltage monotonically increases as the temperature is lowered, but it saturates below 40 K. The subthreshold slope decreases with the temperature lowering but at a rate that is less than theoretically predicted. The extrapolation of the subthreshold slope indicates a finite value at near absolute zero. We show that the measured behavior can be well corroborated with distributed numerical simulations using the drift-diffusion transport model. In addition, to obtain a compact model for use in low-temperature circuit design, SPICE-type compact models need to be modified to incorporate the subtle temperature effects that are not part of the standard models. To this end, we use the analog behavioral language Verilog-A and the BSIM3 model equation set to include additional temperature dependences into the standard compact models to accurately reproduce measured characteristics.

8-Bit Sub Threshold Ripple Carry Adders in 32nm CMOS Technology for Wireless Sensor nodes.

Subthreshold design has been proposed in the literature as an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. The full adder cell forms the basic building block of majority of these signal processing circuits. In this paper, 8-Bit subthreshold Ripple Carry Adders (RCAs) for wireless sensor nodes optimized for ultra low power operation are proposed. Major contribution of this work is conversion of BSIM4, Predictive Technology Model (32nm) to EKV model ( charge based model). The 8-bit RCAs are simulated with HSPICE (Level =55) using the 32nm CMOS technology at supply voltages ranging from 0.25V to 0.4V. Various metrics such as delay, average power and power delay product (PDP) are simulated and reported for effective twelve different topologies. The circuit designers can choose the full adder topology and the supply voltage that is suitable for their applications. Usage of EKV models results in 11% reduction in power than that of using BSIM models for the adder cell CB with supply voltage of 0.2V.

Logical effort based dynamic power estimation and optimization of static CMOS circuits

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates, sizes and processes, the developed model shows a good agreement with Hspice simulations using BSIM3v3 and BSIM4 models for UMC 0.13 μm and Predictive high- k 45 nm processes, respectively. The average error introduced by the model for the considered scenarios is about 3.1%. Depending on the normalized switching power model, two power optimization techniques have been proposed in this paper. The first deals with transistor sizing problem and presents a scheme to size transistors according to a specific design goal. The second technique relies on the joint transistor sizing and supply voltage scaling for reducing the switching power dissipation under specific delay requirements. This technique exhibits superiority over the first for the considered technology processes: UMC 0.13 μm and the Predictive high- k 45 nm.

New Delay-Time Measurements on a 64-kb Josephson–CMOS Hybrid Memory With a 600-ps Access Time

A 64-kb subnanosecond Josephson-CMOS hybrid random-access memory (RAM) has been developed with ultrafast hybrid interface circuits. The hybrid memory is designed and fabricated using a commercial 0.18-?m CMOS process and NEC-SRL's 2.5- kA/cm2 Nb process for Josephson circuits. The millivolt-level Josephson signals are amplified to volt-level CMOS digital signals by a hybrid interface amplifier, which is the most challenging part of the memory system. The performance of this amplifier is optimized by minimizing its parasitic capacitance loading. The 4-K operation of short-channel CMOS devices and circuits is reviewed, and a complete 4-K CMOS BSIM3 model, which has been verified by experiments, is discussed. The memory bit-line output currents are detected by ultralow-power high-speed Josephson devices. Here, we report the first high-frequency access-time measurements on the full critical path showing 600 ps for a single bit. We discuss future designs made to reduce the crosstalk and improve margins, as well as plans to reduce power dissipation and latency.

Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors

In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102dB DC gain, and a 37.6MHz unity gain bandwidth while driving a 2nF heavy capacitive load at a single 1.8V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3V supply to generate a 1.8V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1µS for a 50mA or 100mA step, while a 1% settling time of 0.36µS for a maximum 735mA step under a capacitive load of 10µF with a 1Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8V/3.3V 0.18µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.

A Novel Approach to Link Process Parameters to BSIM Model Parameters

In this paper, we demonstrate a methodology to link process parameters to BSIM model parameters. Here, we have combined well-known statistical methods like principal component analysis (PCA), design of experiments (DOE), and response surface methodology (RSM) to bridge the missing link between process parameters and model parameters. The proposed methodology uses the concept of a correlation matrix, which transforms the process level information to the device and circuit level information through the BSIM model parameters. The proposed methodology has been successfully implemented on an advanced CMOS process. Our results show a strong linear correlation for the data obtained from two techniques namely TCAD technique and the standard HSPICE simulation technique. In both cases the process conditions were kept identical for comparison.

Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation

In this paper, a new approach of transistor modeling is developed for fast statistical circuit simulation in the presence of variations. For both the I-V and C-V characteristics of a transistor, finite data points are identified based on their physical meanings and their importance in circuit operation. The impact of process and design variations is embedded into these key points using analytical expressions. During the simulation, the entire I -V and C -V curves are interpolated from these points with simple polynomial formulas. This novel approach significantly enhances the simulation speed with sufficient accuracy. The model is implemented in Verilog-A to support generic circuit simulators. The accuracy and convergence of the proposed model are comprehensively evaluated through a set of benchmark circuits, including nand, a pass-gate, latches, AOI, ring oscillators, and an adder. Compared to SPICE simulations with the BSIM models, the simulation time can be reduced by 7 times in transient analysis and more than 9 times in Monte-Carlo simulations.

Preferred Transmission Frequency for Size-Constrained Ultralow-Power Short-Range CMOS Oscillator Transmitters

A method is presented for minimizing the power consumption of size-constrained oscillator transmitters by selecting the preferred carrier frequency from among the standard ISM bands. The method has been applied to CMOS oscillator transmitters in which a single-turn loop antenna doubles as the inductor in the frequency-defining LC tank. A detailed model of the transmitter circuit, including the antenna, is combined with standard assumptions about the link and receiver to determine the minimum transmitter bias current for successful demodulation as a function of antenna size and transmission frequency. From this, the optimal operating frequency in terms of transmitter power budget, and the minimum transmitter power consumption at that optimal frequency, are determined for a given antenna size constraint. Two common oscillator topologies are studied, both implemented in 0.18 mum CMOS: the Colpitts oscillator and the complimentary cross-coupled oscillator. A combination of the EKV and BSIM models is used for MOS transistor modelling, while a novel energy conservation method is used to determine the oscillator bias current as a function of transmit power. The results show that, with the correct choice of operating frequency, transmitter power budgets of the order of 10 muW should be achievable for very short-range (ca 1 m) radio links with data rates up to 1 Mb/s and antenna sizes down to several mm radius.

Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.

Accuracy of PSP and BSIM4 models in determination of IP3 compression point

A comparative benchmark of the linearity properties of two of the most popular compact transistor models (BSIM4 and PSP) for nanometre process technologies (45 nm) is presented. The determination of the IP3 compression point for a particular network configuration, which is often encountered in RF mixers, is used as a comparison vehicle. Parameters of both the PSP and BSIM4 models adopted in the comparison have been fitted to a leading-edge 45 nm RF technology. The benchmarks show that the BSIM4 model is unable to capture the IP3 compression point whereas the PSP model yields the expected behaviour, thus enabling the determination of the correct value of IIP3.

Design of Chopper-Stabilized Amplifiers With Reduced Offset for Sensor Applications

Offset error mechanisms in a single-ended chopper-stabilized amplifier are investigated. The error models and their prediction equations are given. This work also presents a new analytical approach for estimating the switch error in a four-transistor chopping network. A new resistance balancing circuit technique is also introduced, which permits further reduction of DC offsets in conventional chopping operational amplifier (op-amp) or chopping differential difference amplifier (DDA). The HSPICE simulation results have validated the proposed technique and identified dominant error sources using Level-49 BSIM3 model in a standard 0.6-mum CMOS technology. Applying the technique to the fabricated DDA chips at a noninverting gain of ten and a single 3-V supply, the measured results have shown that 40% of the ten samples display no more than 3- and 5-muV offsets at the chopping frequency of 10 and 64 kHz, respectively. The proposed technique offers a potential advantage for improving the yield of low-offset amplifiers in sensory systems.

Compact modeling of amorphous‐silicon thin‐film transistors with BSIM3

Abstract— A novel approach of modeling a‐Si:H TFTs with the industry‐standard BSIM3 compact model is presented. The described approach defines the a‐Si:H TFT drain current and terminal charges as explicit functions of terminal voltages using a minimum set of BSIM3 parameters. The set of BSIM3 parameters is chosen based on the electrical and physical characteristics of the a‐Si:H TFT and their values extracted from measured data. By using the selected BSIM3 model parameters, the a‐Si:H TFT is simulated inside SPICE to fit the simulated I‐V and C‐V curves with the measured results. Finally, the extracted BSIM3 model is validated by simulating the kickback voltage effect in an AMLCD pixel array.

UDSM subthreshold leakage model for NMOS transistor stacks

In this paper, a new, analytical model for subthreshold leakage estimation in the ultra deep submicron (UDSM) realm is proposed. Most previous attempts at subthreshold leakage estimation in transistor stacks are not tailored for the UDSM realm and are based on either a look up table approach, and/or assume that all the transistors in the stack have a fixed width. The analytical estimation model proposed in this paper is capable of estimating subthreshold leakage in UDSM NMOS transistor stacks with different transistor widths. The model achieves this by estimating the stack nodal voltages. In this paper, transistor stacks of two, three and four transistors are considered.Compared to SPICE simulations using PTM's BSIM4 models, our analytical model achieved an average error of 8.1% for the one, two, three and four transistor stacks for 65, 45 and 32nm CMOS process technologies. The model also exhibits significant runtime savings when compared with SPICE.

A methodology for the implementation of MOSFETs with a high-k dielectric gate material on the design of 90 nm technology circuits

Up to date, MOSFETs have been made through well established techniques that use SiO2 as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO2 as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO2 is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO2 devices. A cell layout is provided and the DRAM circuit characteristics are also presented.

Analysis and optimization of leakage current characteristics in sub-65 nm dual Vt footed domino circuits

The inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual Vt footed domino circuits. Simulations based on 65 and 45nm BSIM4 models show that the conventional CHIL state (the clock signal is high and inputs are all low) is ineffective for lowering the leakage current and the conventional CHIH state (the clock signal and inputs are all high) is only effective to suppress the leakage current at high temperature other than the high fan-in domino circuits. For the high fan-in footed domino circuits at high temperature and most of footed domino circuits at room temperature, the CLIL (the clock signal and inputs are all low) state is preferable to reduce the leakage current. Further, the influence of the process variations on the leakage current characteristics of the dual Vt footed domino circuits is also evaluated. It is observed that the average leakage current is universally higher than the date reported in the normal corner and the CLIL state is the optimum choice considering the leakage current reduction and the robustness to the process variations simultaneously.

An Optimized Scalable BSIM Macromodel for HV Double-Diffused Drain MOSFET ${I}$–${V}$ Characteristics

This letter presents a scalable macromodel dedicated to the I-V characteristics of the high-voltage double diffused drain metal oxide semiconductor field effect transistor (MOSFET), which can be widely used in SPICE simulators and electronic design automation tools. The scalable model has been validated for different device geometries: large dimension (L = 20 mum, W = 20 mum), narrow dimension (L =20 mum, W = 1.8 mum/2 mum/5 mum), and short dimension (L = 1.2 mum/1.5 mum/2 mum/3 mum/5 mum, W = 20 mum). The variable-resistance feature of the lightly-doped drain has been simulated by metal semiconductor FET and diode, instead of by variable resistance which the Berkeley short channel insulated gate field effect transistor model (BSIM) does not support. This approach not only improves the utility value of the macromodel, but also considers the physical effects of the high-voltage MOSFET. Furthermore, this scalable macromodel can be applied to the modeling software tools based on the SPICE BSIM model.

Investigation into effects of device variability on CMOS layout motifs

Sub-circuit motifs are proposed as a methodology for simulating the performance of sub-45 nm circuits exhibiting atomistic device fluctuations. Motifs allow the reduction of the problem space and create a standard motif library as a step in the design hierarchy for logic circuits. Device variability information from 3D simulation results is used that is incorporated into families of BSIM4 models. It is demonstrated how a thorough understanding of circuit behaviour can be obtained and the impact on current drive is illustrated by examining the effect of additional parasitic resistances.

Contributions of the gate current and channel current variation to the post-breakdown MOSFET performance

A new approach to the modelling of the post-breakdown (BD) performance of MOSFETs for circuit simulation is presented, which separately considers the additional post-BD gate current and the variation of the MOSFET channel current. The post-BD gate current is modelled using an improved equivalent circuit whereas the BSIM4 model is used to describe the MOSFET channel current. This approach has allowed to analyse the contributions of both currents on the post-BD I D– V D characteristics. The results show that the gate current increase and the variation of the channel current are determining factors of the MOSFET performance degradation after BD.