Broadband Low-noise Amplifier Research Articles

A broadband single-ended active-feedforward -noise-canceling LNA with IP2 enhancement in stacked n/pMOS configurations

In this paper, we present a broadband low-noise amplifier (LNA), using active-feedforward noise-cancellation and complementary n/pMOS configurations. Based on traditional common-gate (CG) and common-source (CS) noise canceling topology, the applied active feedforward stage reduces the CG's dc current and alleviates its resistive load tradeoff between noise and headroom. Meanwhile, the active feedforward stage follows the same noise cancellation (NC) principle as the CG transistors. A low noise figure is thus obtained. In addition, the complementary n/pMOS configuration is used to cancel second-order distortions and double current efficiency. Two π-type matching networks are utilized to broaden the bandwidth of S11 and gain. After applying these techniques, an LNA prototype was designed in standard 65 nm CMOS technology. Simulation results display a gain of 14–17 dB and a noise figure (NF) of 2.45–3.45 dB within a bandwidth of 1–12 GHz. The linearity of IIP3 and IIP2 are −2.4 and 23 dBm at 5 GHz. The presented circuit consumes only 7.8 mW of dc power while occupying an area of 0.21 mm2.

A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature.

A Ku band low-voltage and low-power CMOS low-noise amplifier with bulk isolation techniques

Abstract In this paper, a broadband(12-18G) low-noise amplifier (LNA) using 65-nm CMOS technology for satellite communication is presented. This LNA was designed in a cascode common source with inductive degeneration topology. In addition, the bulk isolation technique is employed to make the proposed LNA have a higher gain. Furthermore, a two-stage cascaded configuration combined with inductive parallel peaking technology is utilized to make the LNA achieve a wide operating band. For validation, we design this LNA in a 65nm CMOS technology. The simulated results show that S21 of 17.7dB ± 0.5dB, the input/output return loss of -10dB to -33dB and -12dB to -23dB, respectively. It offers the minimum noise figure (NF) performance of 3.33dB, reverse isolation(S12) better than 60dB, and third-order input point (IIP3) of -22.8 dBm obtained over the band of interest. Excluding the output buffer stage, the LNA is consuming 5.1 mW at a supply voltage of 0.8V and its layout area occupies 0.205 mm2.

A 27.5–46.2-GHz Broadband Low Noise Amplifier With IP3 Enhancement

This letter presents a 27.5–46.2-GHz broadband low-noise amplifier (LNA) featuring IP3 enhancement. The LNA bandwidth (BW) is extended by implementing dual-resonant input matching and a broadband output network. The LNA IP3 is enhanced by incorporating parallel PMOS and NMOS paths in the second stage, with their output currents combined through a three-winding transformer. Implemented using the GlobalFoundries 45-nm CMOS silicon-on-insulator (SOI) process, the LNA demonstrates 27.5–46.2 GHz effective BW, 2.1 dB minimum noise figure (NF), and 19.8 dB peak gain. The measured IIP3 is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3.6 dBm at 34 GHz under 25.5 mW DC power consumption. Compared to recently reported broadband LNAs with a similar frequency range, this design achieves the state-of-the-art NF, IIP3, and figure-of-merit (FoM).

Calibration-Free Blocker Rejection Broadband CMOS Low Noise Amplifier for Advanced Cellular Applications

This study presents a broadband complementary metal-oxide semiconductor (CMOS) low noise amplifier (LNA), containing out-of-band (OB) blocker rejection capability without an additional calibration process. In the proposed design, separate all-pass and band-stop filter stages are provided in parallel as main and auxiliary paths, respectively, whose amplitude and phase variations are identically tracked by each other over a process, voltage, and temperature dependency. By appropriately combining an in-band signal and OB blockers passed through those filter blocks, robust OB blocker rejection can be realized in the wide frequency range. The designed LNA incorporates a pre-amplifier stage for broad input matching and low-noise characteristics, an N-path filter-based frequency selective stage, and a combiner stage to suppress undesired OB blockers. The designed calibration-free OB blocker rejection broadband LNA is fabricated in a 65 nm CMOS technology and mainly characterized in long-term evolution frequency division duplexing bands, ranging from 0.7 to 2.7 GHz. The demonstrated design consistently attains transmitter leakage and other OB blocker rejection of more than 22.8 dB and 16 dB in low-band (LB) (0.7–1 GHz) and mid- and high-band (MB and HB) (1.7–2.7 GHz) frequency range from several samples without extra gain or phase adjustment, respectively. The implemented LNA also achieves gains of 10.5–11.0 dB and 8.0–10.0 dB, noise figures of 3.7–4.1 dB and 3.8–4.9 dB, OB third-order intercept points greater than 8.2 dBm and 9.8 dBm, and OB 1-dB compression points greater than −5.2 dBm and −5.5 dBm, for LB and MB/HB, respectively. The implemented design consumes a total bias current of 23.9 mA with a nominal supply of 1.2 V and occupies an active area of 0.53 mm2, excluding bonding pads.

Analysis and Design of a 2-40.5 GHz Low Noise Amplifier With Multiple Bandwidth Expansion Techniques

This paper analyzes the main factors limiting the bandwidth expansion of low-noise amplifiers (LNA) and designs a broadband LNA with a bandwidth of 2-40.5 GHz. The LNA is designed using multiple bandwidth expansion methods, including cascode, resistance feedback, and cascode Darlington amplifier. The amplitude-frequency characteristics and bandwidth expansion principle of the three structures are studied theoretically based on the small-signal equivalent circuit model. Thanks to these techniques, a three-stage LNA is designed in a 0.15-μm GaAs pseudomorphic high-electron-mobility (pHEMT) process. The measured results show that the designed LNA achieves an average gain of 21.6 dB in 2-40.5 GHz while maintaining a noise figure (NF) below 3.6 dB. The measured output 1-dB gain compression point (OP1 dB) is from 4.5 to 12.8 dBm and the input/output return loss are better than 5 dB. The chip area is only 1.57 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including input and output test pads.

Data acquisition system for a neutron spectrometer with a remote diamond detector

The article presents the design and first test results of the neutron spectrometer with count rate up to 7 × 106 events per second with remote detector based on artificial diamond, intended for use on burning plasma experiments. The spectrometer consists of the broadband low-noise amplifier and the data acquisition and processing unit. The design of the amplifier with characteristic impedance matching of the cable line by the dynamic resistance of the transistor base-emitter junction is considered. The data acquisition and processing unit is realized using a real-time event-processing algorithm based on harmonic data analysis. This algorithm includes effective techniques for detecting and excluding overlaps and suppression of fluctuations in the baseline level corresponding to zero signal.

Design a Broad-band High flatness Gain Low Noise Amplifier for radar Applications

Design a Broad-band High flatness Gain Low Noise Amplifier for radar Applications

W-Band 광대역 저잡음 증폭기 설계

This paper presents a W-band broadband low noise amplifier (LNA). The proposed LNA was designed and verified using a 100 nm GaAs pHEMT. To achieve broadband low noise and gain characteristics, peak gain distribution was employed. The LNA comprised four gain stages and a shunt inductor at the input stage to prevent the device damage. The LNA achieved a 16.2 dB gain and 5.5 dB noise figure in an area of 1.78×0.743 mm2

CNTFET Based Grounded Active Inductor for Broadband Applications

A new carbon nanotube field effect transistor (CNTFET) based grounded active inductor (GAI) circuit is presented in this work. The suggested GAI offers a tunable inductance with a very wide inductive bandwidth, high quality factor (QF) and low power dissipation. The tunability of the realized circuit is achieved through CNTFET based varactor. The proposed topology shows inductive behavior in the frequency range of 0.1–101 GHz and achieves to a maximum QF of 9125. The GAI operates at 0.7 V with 0.337 mW of power consumption. To demonstrate the performance of GAI, a broadband low noise amplifier (LNA) circuit is designed by utilizing the GAI based input matching-network. The realized LNA provides high frequency bandwidth (17.5–57 GHz), low noise figure (

A New Approach for Designing and Analysis of High Flat Gain Broadband Low Noise Amplifier Using Real Frequency Technique

This paper introduces a high flat gain broadband Low Noise Amplifier (LNA) design approach, which is based on using a new methodology of Real Frequency Technique (RFT). To get this done, the optimum matching network has been designed with second-order LC lumped elements to minimize the Noise Figure (NF) and maximize the Transducer Gain (GT) based on selecting the optimum (ZS, ZL) LNA terminations that have been used over a 2.1-4.2 GHz. The design has demonstrated a high stable gain in the range of 19.19 –18.73 dB with ± 0.2 dB gain flatness over the specified band. Moreover, the NF has been obtained at 0.68 – 0.82 dB and a stable operation throughout a broad bandwidth. Furthermore, the proposed method results have been compared with an analytical methodology which is based on computing equivalent input and output circuits for the transistor model using its scattering parameters. For the verification purpose, the performances of the synthesized amplifier are compared using MATLAB platform and ADS simulation software. The output results have a good agreement with the proposed method outcomes, which makes this method a new promising technique for the high flat gain broadband LNA design.

Design and implementation of a broad-band high gain low noise amplifier for 3G/4G applications

The main aim of the paper is designing and implementing a broadband low-noise-amplifier (LNA) based on compensated matching network techniquein order to get high stable gain, low noise figure, low cost and smaller sizefor 3G/4G communication system applications at 2 GHz with bandwidth 600MHz. The Advanced Design System simulates the proposed circuit (ADS).The implementation was done with a class A bias circuit and a low noise transistor BFU 730F with a lower Noise Figure (NFmin) 0.62 dB. Collectorcurrent is measured to be 5.8mA and base current is 19.1μA with a supply voltage of 2.25V. The new design proposed a (NFmin) of 0.62 dB with a 17.8dB high stable amplifier gain. The microstrip lines (MSL) and compensated matching network techniques were used to improve the LNA’s stability and achieve a good result. The LNA board is implemented and assembled on the FR4 botton layer material. The results are virtually non existence equivalent between the simulated and the measured results.

6.7–15.3 GHz, High-Performance Broadband Low-Noise Amplifier With Large Transistor and Two-Stage Broadband Noise Matching

This letter presents a fully integrated wideband, ultralow average noise figure (NF), low power consumption, compact, and electrostatic discharge protected 6.7-15.3-GHz low-noise amplifier (LNA). A peak-gain distribution technique with a large transistor and two-stage broadband noise matching technique are proposed. For verification, a two-stage common source LNA is implemented in a 65-nm bulk complementary metal-oxide-semiconductor technology. The fabricated LNA achieved an average NF of 2.08 dB and an average gain of 19.1 dB with in-band gain ripple of ±0.75 dB in the frequency range of 7.6-14.7 GHz. It has a 3-dB fractional bandwidth of 78% and the third-order input intercept point is -9.0 dBm at 10 GHz. It consumes a 16 mA at a 0.8-V supply and has an area of 0.144 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Cryogenic Broadband Sub-1-dB NF CMOS Low Noise Amplifier for Quantum Applications

A cryogenic broadband low noise amplifier (LNA) for quantum applications based on a standard 40-nm CMOS technology is reported. The LNA specifications are derived from the readout of semiconductor quantum bits at 4.2 K, whose quantum information signals are characterized as phase-modulated signals. To achieve broadband input matching impedance and low noise figure, the gate-to-drain capacitance of the input transistor is exploited. The goal is to involve a resistive and capacitive load into the input impedance match of a common-source stage with source inductive degeneration. The capacitive load is created by an LC parallel tank whose resonant frequency is lower than the operating frequency. The achieved non-constant in-band equivalent capacitance is proven to be beneficial to input impedance matching. The resistive part of the load is provided by the transconductance of the cascode stage implicitly. An inductor is added to the gate of the cascode transistor to suppress its noise, and a transformer-based resonator with two resonant frequencies serves as the load of the first stage, thus extending the operating bandwidth. Design considerations for the cryogenic temperature operation of the LNA are proposed and analyzed. The LNA achieves a measured gain ( $S_{21}$ ) of 35 ± 0.5 dB, return loss > 12 dB, and NF of 0.75–1.3 dB across the band (4.1–7.9 GHz), with 51.1-mW power consumption at room temperature, while it shows a measured gain of 42 ± 3.3 dB, and NF of 0.23–0.65 dB with 39-mW power consumption at 4.2 K between 4.6 and 8 GHz. To the best of our knowledge, this is the first report of a cryogenic LNA based on a bulk CMOS process working above 4 GHz showing sub-1-dB NF both at room and cryogenic temperatures.

Design of Ka-band broadband low-noise amplifier using 100nm gate-length GaN on silicon technology

Due to the high breakdown voltage and better linearity of gallium nitride (GaN) high electron mobility transistor (HEMT), GaN based RF front-end is widely researched and studied. In this paper, a Ka-band cascode low-noise amplifier (LNA) designed with 100nm gate-length GaN-on-silicon technology is presented. With novel methods such as the introduction of high-pass filters and standing wave filtering capacitors, the LNA achieves a stable gain of 21-22.8dB and a noise figure (NF) of 0.9-1.3dB from 22GHz to 38GHz. The input and output return loss are better than-10dB in band of concern. This LNA occupies an area of 2.3mm × 0.9mm and consumes 265-mW DC power. Compared with silicon-on-insulator (SOI), indium phosphide (InP) and gallium arsenide (GaAs) LNAs, the proposed GaN LNA exhibits better performance of linearity, as well as competitive gain and NF.

Analysis and Design of a Broadband Receiver Front End for 0.1-to-40-GHz Application

In this paper, a broadband receiver front end for 0.1 to 40 GHz application, fabricated using 0.15-μm GaAs E-mode pHEMT process, is reported. The receiver front end consists of a broadband low-noise amplifier (LNA) and a broadband mixer. To achieve low noise and significant bandwidth extension, a three-stage LNA, cascading one stage cascode amplifier with feedback and bandwidth extension techniques, to two stage cascode Darlington amplifiers with feedback, is proposed. The bandwidth extension principles of LNA are analyzed theoretically and verified experimentally. Measurement results show that the proposed LNA exhibits an average gain of 23.7 dB with ± 1.5-dB variation, a typical noise figure of 3.8 dB, maximum OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of 8.7 dBm in the frequency range from 0.1 to 40 GHz. A symmetric distributed drain mixer (SDDM) is proposed to provide broad bandwidth while ensuring an IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of up to 5.8 dBm. The design procedure of SDDM is presented in detail. Experimental results indicate that the SDDM features a less than 7-dB conversion loss, an IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of up to 5.8 dBm with zero dc dissipation and better than 15-dB isolation of LO-to-RF and IF-to-RF ports from 0.1 to 40 GHz. Finally, the LNA and SDDM are integrated as a 0.1 to 40-GHz receiver front end. Measurements illustrate that the receiver front end shows good matching with better than 10-dB return loss at RF and LO ports, and larger than 15-dB conversion gain in 0.1 to 40-GHz frequency range. The receiver occupies only 1.89-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area including test pads. To the best of the authors' knowledge, the designed receiver front end has the widest bandwidth among reported receivers fabricated by using GaAs process.

Собственные параметры идеального четырехполюсника для согласования малошумящих усилителей

The problem of broadband matching of active elements in terms of noise figure is inevitably encountered in the design of broadband low-noise microwave amplifiers. Despite the fact that this problem differs from the classical problem of broadband matching of signal source and load, it can be reduced to a form suitable for applying methods for solving the classical problem. For this purpose, in this work, the own parameters of a reactive two-port network are derived that match active elements in terms of noise figure in the entire frequency band, where the data for calculating this coefficient are determined. The own parameters of such a two-port network, on the one hand, make it possible to construct methods for the synthesis of input matching circuits of low-noise amplifiers and other devices where low noise matching is required. On the other hand, the own parameters allow one to construct estimates of the maximum achievable bandwidth for a matching circuit of a given complexity.

Аdaptive broadband low-noise RF amplifier

Adaptive broadband low-noise radio frequency amplifiers (ABLNRFA) are widely used in the construction of systems for protecting radio receiving paths from nonlinear damage in a non-stationary electromagnetic environment (EME). One of the promising focus areas on the creation of ABLNRFA is the development of devices in the class of circuits with switched networks. The creation of such devices has certain features, since, along with the need to ensure a low noise figure and digital control of the regulation characteristic, it is required to provide high linearity and a large dynamic range (DR) of the device. This paper presents the results of the logical-heuristic synthesis of ABLNRFA with an adaptively adjustable transducer gain, which changes due to switching of transformer feedback circuits. In order to check the functional and technical characteristics of the synthesized ABLNRFA and optimize its parameters, a model was developed and studied in the ADS environment. The proposed ABLNRFA technical solution provides a discrete (23, 14, 10 and 5 dB) wideband change in the transmission coefficient, while the DR for third-order intermodulation in terms of a 1 MHz band is 83, 92, 98 and 104 dB, respectively. A step change in the transducer gain in the circuit of the lossless feedback circuit developed by ABLNRFA avoids the accumulation of additional noise in the structure and provides a low-noise figure that does not exceed 1 dB. The technical characteristics of ABLNRFA allow one to adaptively increase the overload capacity of the radio receiving path with a proportional expansion of its DR in the conditions of non-stationary EME, and thus increase the efficiency of the level protection system against nonlinear damage to the receiving paths of radio communication, radar and radio navigation.

A 0.02–4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse

In this article, a new noise reduction/cancellation technique is proposed to improve noise figure (NF) of a broadband low-noise transconductance amplifier (LNTA) for 5G receivers. The LNTA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage for canceling the noise and distortion of the CG stage. Yet, another noise reduction is applied to reduce the channel thermal noise of the noise cancellation stage itself. The technique further exploits current reuse and increases transconductance of the CS transistor while keeping its power consumption low. Fabricated in 28-nm CMOS, the proposed LNTA is capable of driving an external 50-Ω load and achieves a NF of 2.09-3.2 dB and input return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) better than -10 dB over the 3-dB bandwidth of 20 MHz-4.5 GHz while consuming 4.5 mW from a single 1-V power supply. The achieved gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) and IIP3 are 15.2 dB and -4.6 dBm, respectively.

W-band system-on-chip electron cyclotron emission imaging system on DIII-D.

Monolithic, millimeter-wave "system-on-chip" (SoC) technology has been employed in heterodyne receiver integrated circuit radiometers in a newly developed Electron Cyclotron Emission Imaging (ECEI) system on the DIII-D tokamak for 2D electron temperature profile and fluctuation evolution diagnostics. A prototype module operating in the E-band (72 GHz-80 GHz) was first employed in a 2 × 10 element array that demonstrated significant improvements over the previous quasi-optical Schottky diode mixer arrays during the 2018 operational campaign of the DIII-D tokamak. For compatibility with International Thermonuclear Experimental Reactor relevant scenarios on DIII-D, the SoC ECEI system was upgraded with 20 horn-waveguide receiver modules. Each individual module contains a University of California Davis designed W-band (75 GHz-110 GHz) receiver die that integrates a broadband low noise amplifier, a double balanced down-converting mixer, and a ×4 multiplier on the local oscillator (LO) chain. A ×2 multiplier and two IF amplifiers are packaged and selected to further boost the signal strength and downconvert the signal frequency. The upgraded W-band array exhibits >30 dB additional gain and 20× improvement in noise temperature compared with the previous Schottky diode radio frequency mixer input systems; an internal 8 times multiplier chain is used to bring down the LO frequency below 12 GHz, thereby obviating the need for a large aperture for quasi-optical LO coupling and replacing it with coaxial connectors. Horn-waveguide shielding housing avoids out-of-band noise interference on each individual module. The upgraded ECEI system plays an important role for absolute electron temperature evolution and fluctuation measurements for edge and core region transport physics studies.