Detection Of Bridging Faults Research Articles

Input Bridging Fault and Non Feedback Bridging Fault Detection and Test Vector Generation by Boolean Satisfiability Method

Input Bridging Fault and Non Feedback Bridging Fault Detection and Test Vector Generation by Boolean Satisfiability Method

Bridging fault detection in cluster based FPGA by using Muller C element

In this work, we propose a testing technique for detecting single stuck-at and bridging faults in the interconnects of the cluster based FPGA. The presence of the feedback-bridging fault, race and glitch poses major challenges to the detection of the fault. The feedback bridging fault has a high ingredient of delay dependent properties due to the variation of the feedback path delay. So we have exploited the concept of asynchronous logic in order to detect the fault. We configure the block under test (BUT) with a pseudo delay independent asynchronous element known as Muller C element. The novelty of this scheme lies in the fact that, it can detect the stuck-at and bridging fault including the feedback bridging fault by a single test configuration. The Xilinx Jbits 3.0 API (Application Program Interface) is used to implement the BISTER (Built-in-self-tester) structure in the FPGA. In comparison to the traditional FPGA development tool (ISE), ‘Jbits’ gives more controllability for which the partial run time reconfiguration of the FPGA is easily achieved.

Testable design of AND–EXOR logic networks with universal test sets

This paper presents a testability enhancement technique suited for AND–EXOR based logic networks that facilitates easy detection of stuck-at and bridging faults by a universal test set. Both cascaded and tree implementations of the EXOR-part are considered. The AND–EXOR based circuit implemented with a cascaded EXOR-part requires a universal test set of size (2 n + 6) for an n-variable function implementation. For Generalized Reed–Muller (GRM) implementation, this test set detects all single stuck-at and bridging faults (both OR-type and AND-type) and also large number of multiple bridging faults. For an Exclusive-OR Sum-of-Products (ESOP) implementation, a few single bridging faults may remain untested under this test set, occurrence of which can be minimized by employing an appropriate design and layout technique. Next, it is shown that an AND–EXOR network with a tree-based EXOR-part can be tested for similar faults by a universal test set of size (2 n + 8). This paper also solves an open problem of designing a universal test for a tree-based AND–EXOR circuit. Since the EXOR-tree has depth of ( ⌈ log 2 s ⌉ + 1 ), where s is the number of product terms in the given AND–EXOR expression, this tree-based design reduces the circuit delay significantly compared to cascaded EXOR implementation. In both the cases, the test set can be stored in a ROM on-chip for built-in self-test (BIST) purposes. For several benchmark circuits, the universal test set is found to be much smaller in size than the ATPG-generated test sets.

How Many Test Vectors We Need to Detect a Bridging Fault?

The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances and logic thresholds which play a main role in bridging fault detection. In this evolving context, the quality of fault simulation and test generation tools making use of nominal parameters should be verified. To analyze this problem we have studied bridging fault detection in combinational ICs in the presence of growing variations of IC's parameters. Results show that a single test is not sufficient to ensure acceptable escape probabilities. Conversely, the minimal number of test vectors required to provide a null escape probability is upper bounded with respect to variations in the standard deviation of IC's parameters. This result has been verified by means of Monte Carlo electrical level simulation. We propose a method to derive these minimal test sets in the case of low frequency tests. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability. These tools have been applied to a set of combinational benchmarks.

Application-independent testing of FPGA interconnects

We present a new automatic test-configuration-generation technique for application-independent manufacturing testing of the interconnection network of static-random-access-memory-based field programmable gate arrays (FPGAs). This technique targets detection of open and bridging faults in the wiring channels and programmable switches in the interconnects. Experimental results on Xilinx Virtex FPGAs show that very few test configurations are required to cover stuck-open, stuck-closed, open, and bridging faults in the interconnects.

Testing and diagnosis of interconnect faults in cluster-based FPGA architectures

As IC densities are increasing, cluster-based field programmable gate arrays (FPGA) architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-base architecture is one in which several logic blocks are grouped together into a coarse-grained logic block. While the high-density local interconnect often found within clusters serves to improve FPGA utilization, it also greatly complicates the FPGA interconnect testing problem. To address this issue, we have developed a hierarchical approach to define a set of FPGA configurations which enable interconnect fault detection and diagnosis. This technique enables the detection of bridging faults involving intracluster interconnect and extracluster interconnect. The hierarchical structure of a cluster-based tile is exploited to define intracluster configurations separately from extracluster configurations, thereby improving the efficiency of the configuration definition process. The cornerstone of this work is the concise expression of the detectability conditions of each fault and the distinguishability conditions of each fault pair. By guaranteeing that both intracluster and extracluster configurations have several test transparency properties, hierarchical fault detectability is ensured.

Bridging Faults in Pipelined Circuits

This paper analyzes the detectability of resistive bridging faults in CMOS (micro)-pipelined circuits. Logic and electrical level detection conditions are provided for functional and Iddq testing techniques. The kind of operations and the sensitivity to dynamic fault effects of pipelined circuits make such conditions more complex than in the combinational case. In particular, it is shown that the kind of used latches has a relevant impact on fault coverage, and should be carefully accounted in test generation and fault simulation. Finally, guidelines are drawn for the extension of combinational test generation and fault simulation algorithms to the considered case.

Defect-oriented testability for asynchronous ICs

For a CMOS manufacturing process, asynchronous ICs are similar to synchronous ICs. The defect density distributions are similar, and hence, so are the fault models and fault-detection methods. So, what makes us think that asynchronous circuits are much harder to test than synchronous circuits? Because the effectiveness of best known test methods for synchronous circuits drops when applied to asynchronous circuits? They may very well be a temporal hurdle. Many test methods have already been reevaluated and successfully adapted from the synchronous to the asynchronous test domain. The paper addresses one of the final hurdles: I/sub DDQ/ testing. This type of test method, based on measuring the quiescent power supply current, is very effective for detecting (resistive) bridging faults in CMOS circuits. Detection of bridging faults is crucial, because they model the majority of today's manufacturing defects. I/sub DDQ/ fault effects are sensitized in a particular state or set of states and can only be detected if we stop the circuit operation right there. This is a problem for asynchronous circuits, because their operation is self-timed. In the paper, we quantify the impact of self timing on the effectiveness of I/sub DDQ/-based test methods for bridging faults, and propose a Design-for-Test (DfT) approach to develop a low-cost DfT solution. For comparison, we do the same for logic voltage testing and stuck-at faults. The approach is illustrated on circuits from Tangram, the asynchronous design-style employed at Philips Research, but it is applicable to asynchronous circuits in general.

IDDQ testing: state of the art and future trends

Quality assurance in electronic components and systems requires effective test strategies to be applied to ICs of increasing complexity and size. The traditional voltage techniques based on logic observation of the outputs have been found insufficient to guaranty the low defect escape requirements of growing sectors of IC users. This fact has motivated the search for complementary testing techniques which try to detect defects escaping logic testing. This paper attempts to explore the state of the art and the perspective of the test based on the observation of the quiescent current consumption of the IC, generally known as I DDQ testing. After introducing the basic principle of the technique and the components of the quiescent current in CMOS technologies, the physical defects which cause an increase of the I DDQ are presented. The state of the art of the detection of circuits with sensor(s) located on-chip (BICS) and off-chip is explored. A literature review of the circuits to sense the quiescent current permits their classification according to their function and structure. The different techniques to generate the input vectors to force the increase in quiescent current consumption are presented and, as an example, an ATPG to detect bridging faults is presented in detail. Finally the future trends of I DDQ testing are discussed taking into account the implications of scaling in CMOS. As the power supply voltage is reduced to maintain the electric fields in the MOS transistors and the global power consumption, the threshold voltages of the devices need to be lowered to maintain or increase the speed of the logic. As a consequence, the quiescent current consumption, I DDQ, increases exponentially. This fact decreases the discriminability of nondefective in front of defective quiescent currents. On the other hand, techniques to reduce the leakage currents are becoming available thanks to an active research effort directed mainly to decrease the quiescent power consumption in submicron ICs.

I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays

This paper presents an I/sub DDQ/-based test strategy for detecting bridging faults in the logic resources of reprogrammable field programmable gate arrays (FPGAs). The proposed approach utilizes the programmability of the configurable logic blocks (CLBs) to achieve 100 percent coverage of I/sub DDQ/ testable bridging faults. We use a hierarchical approach for generating tests and configurations. At the chip level, the CLBs are viewed as a homogeneous two-dimensional array. Two configuration strategies are suggested to simultaneously test each CLB. Within each CLB, we test for external bridging faults between the combinational and sequential logic modules (e.g., flip-flops, multiplexers, lookup tables), Finally, we test for internal bridging faults within each module based on their implementation. Since reconfiguration programming time dominates total test time, even with slow I/sub DDQ/ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first and, then, to minimize the number of test vectors. The Xilinx XC4000 family of SRAM-based FPGAs is used as an example application of the proposed approach. One hundred percent coverage for I/sub DDQ/-testable bridging faults is achieved in five programming phases and 16 I/sub DDQ/ vectors. Since the lookup tables in the CLB can be configured as RAM, the RAM modes are also tested. This requires a further phase, using 48 test vectors and 38 I/sub DDQ/ measurements.

On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits

This paper investigates the detection of parametric bridging and delay faults affecting the functional block of CMOS self-checking circuits (SCCs). As far as these faults are concerned, classical definitions are shown to become ambiguous because they are entirely based on logic considerations. Thus, new definitions are proposed here to consider the analog and dynamic effects of such faults, and to ensure that they do not produce any problem at the system level. Moreover, electrical level design rules aimed at satisfying these conditions are proposed for self-checking circuits with combinational functional blocks. The problem of their practicability and effectiveness is analyzed in detail, and is shown by means of significant examples.

VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing

In this paper, we examine the effectiveness of combined logic and IDDQ testing to detect stuck-at and bridging faults. The stuck-at faults are detected by the logic test and IDDQ testing detects bridging faults.Near minimal stuck-at test sets are used for this combined logic and IDQQ test environment. These near minimal stuck-at test sets are generated using standard test programs, while using collapsed fault lists. We examined ISCAS '85 and ISCAS '89 benchmark circuits under this combined test environment. A comparison is given for the fault coverage obtained under this combined test environment with other studies based on pure logic test and IDDQ test. Also, the results of IDDQ based test sets (vectors generated specifically for IDDQ testing) are compared with that of stuck-at test sets. Finally, we present a case study on a microprogrammed processor using a functional test set to detect bridging faults in IDDQ testing.

Algorithms to select I DDQ measurement points to detect bridging faults

IDDQ measurement is a time consuming process. Thus, reducing the number of IDDQ measurements have a great impact on the test time. Carefully selecting a few IDDQ measurement points is therefore an important problem. This problem has been studied for detecting leakage faults but not for bridging faults. We present novel algorithms to select IDDQ measurement points to detect bridging faults. Experimental results obtained are very encouraging. The method can also be used: by test generators to compress IDDQ test sets; and to maximize the fault coverage when a fixed number of measurement points are given.

Testing defects in scan chains

Applying scan-based DFT, I/sub DDQ/ testing, or both to sequential circuits does not ensure bridging-fault detection, which depends on the resistance of the fault and circuit level parameters. With a "transparent" scan chain, however, the tester can use both methods to detect manufacturing process defects effectively-including difficult-to-detect shorts in the scan chain. The author presents a strategy for making the scan chain transparent. The test complexity of such a chain is very small, regardless of the number of flip-flops it contains.

Analysis of resistive bridging fault detection in BiCMOS digital IC's

Analysis of resistive bridging fault detection in BiCMOS digital IC's

Design of CMOS self-checking sequential circuits with improved detectability of bridging faults

Problems due to the presence of resistive bridging faults within sequential functional blocks of self-checking circuits are studied, and design criteria aimed at reducing their effects are proposed. >

Special applications of the voting model for bridging faults

A transistor-level examination of bridging faults and the resulting logic-level bridging fault model is described. Experiments with simulations and silicon demonstrate its accuracy. Previous work has demonstrated the accuracy and efficiency of the voting model for bridging faults. This paper presents a complete formal description of the voting model. In addition, simple solutions to special applications of the voting model which generalize its applicability are presented. These applications include the Byzantine General's Problem, complex gate designs, and nonuniform transistor sizes. How to use Binary Decision Diagrams to compare the voting model to other fault models is also presented. Finally, delay tests are shown to be a poor means for detecting bridging faults. This work was done to show that the voting model, a logic-level model for bridging faults, accurately describes the behavior of real faults in real circuits. >

Analysis of resistive bridging fault detection in BiCMOS digital ICs

This paper presents a study of the effects on the electrical behavior of BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the static and dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering different testing techniques (current monitoring, functional, and delay testing). Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection of bridging faults in BiCMOS circuits is more difficult than in the CMOS case when functional or delay testing is used whereas it becomes more effective when adopting current monitoring. >

Dynamic effects in the detection of bridging faults in CMOS ICs

Dynamic effects in the detection of bridging faults in CMOS circuits are taken into account showing that a test vector designed to detect a bridging may be invalidated because of the increased propagation delay of the faulty signal. To overcome this problem, it is shown that a sequence of two test vectors , in which the second can detect a bridging fault as a steady error, can detect the fault independently of additional propagation delays if T0 initializes the faulty signal to a logic value different from the fault-free one produced by T1. This technique can be conveniently used both in test generation and fault simulation. In addition, it is shown how any fault simulator able to deal with FCMOS circuits can be modified to evaluate the impact of test invalidation on the fault coverage of bridging faults. For any test vector, this can be done by checking the state of the circuit produced by the previous test vector.

Detection of bridging faults in programmable logic arrays

A test set and a testable design for MOS PLAs are proposed. The new design, which modifies a PLA by adding one extra line in the AND plane and one extra line in the OR plane, can detect bridging faults. Furthermore, the design modification requires very low area overhead and is independent of the personality of the PLA under test.