Bridge Chip Research Articles

Fabrication and performances of AI/CuO nano composite films for ignition application

In an effort to explore the application possibility of composite films in ignition field, Al/CuO was fabricated on semiconductor bridge (SCB) chip by ion beam sputtering technique. Surface morphology and elemental composition of the composite films were analysed by scanning electron microscope (SEM) and energy dispersive spectrometer (EDS). Spatial size and duration of the products was detected with the open-air combustion experiment. The results showed that the prepared composite films surface is smooth, flat, and uniform. Element weight ratio meets the design requirements. And the chemical reaction of the Al/CuO nCFs improves output performances of ignition chip.

Microring-based multi-chip WDM photonic module.

We report on a packaged prototype of a WDM photonic transceiver. It is an all-solid state hybrid assembly based on 130nm SOI photonic circuitry integrated with a 40nm CMOS VLSI driver. Our prototype supports eight tunable WDM channels operating at 10Gb/s, each capable of both transmitting and receiving data on the same chip. We discuss two options to close the link using the optical fiber or a waveguide bridge chip. We provide integration details and supporting link measurement data to describe packaged photonic module and its power efficient functionality with its on-chip power per channel averaging 1.3pJ/bit, excluding off-chip laser electrical power.

NFC 브릿지 칩 설계 및 구현

최근 NFC(Near Field Communication)기능을 내장한 스마트폰의 급속한 보급과 더불어 다양한 응용분야와 서비스들이 생겨나고 있다. 기존 비접촉식 스마트카드의 주요 기능이었던 전자식 잠금장치(DDL; Digital Door Lock)와 전자결제를 휴대폰으로 대체할 수 있을 뿐 아니라, Bluetooth 나 Wifi 등의 통신기술에서 초기 setup 과정의 번거로움을 덜어주는 페어링(Pairing) 기능, 가전제품들을 휴대폰으로 모니터링하고 컨트롤하는 기능, 최근 수요가 급격히 증가하고 있는 다양한 센서들의 데이터를 휴대폰으로 수집하여 통신망으로 연결시켜 주는 기능 등 수요가 급격히 증가하고 있다. 이 다양한 센서들과 NFC가 접목됨으로써 한동안 국가적으로 추진해 왔던 USN(Ubiquitous Sensor Network)을 한층 활성화 할 것으로 기대된다. 또한 이는 최근에 큰 화두가 되고 있는 사물인터넷(IoT; Internet of Things) 기술의 핵심이라고 할 수 있는데, IoT 의 최종단에서 중요한 역할을 담당하고 있다. 이러한 기능들을 수행하기 위해서는 NFC 브릿지라고 하는 즉, 각종 디바이스와 휴대폰의 NFC 컨트롤러칩을 연결시켜 주는 기능을 하는 칩이 필요하게 된다. 기존의 Passive 태그 칩 기능에 다양한 디바이스들과의 인터페이스 기능을 추가함으로써 간단하면서도 저렴한 NFC 브릿지 기능을 수행할 수 있도록 하는 칩이다. 본 연구에서는 NFC Forum에서 만든 NFC 표준을 기반으로 하여 NFC 브릿지 칩을 설계하고 구현하였다. 이 칩은 크게 디지털 파트와 아날로그 파트로 구성이 되어 있어서, RF 신호 처리와 이를 디지털 신호로 변환하여 디바이스와 인터페이스가 가능하도록 하였다. 특히 RF 감지를 통하여 디바이스의 호스트 프로세서를 깨우는 기능을 추가함으로써 디바이스의 전력손실을 최소화 할 수 있다. 이 기능은 무전원 혹은 저전력 디바이스에 주로 사용되기 때문에 아주 중요한 기능이라고 할 수 있다. 캐리어 주파수는 13.56㎒를 사용하고 있고, 데이터 전송속도는 212kbps 및 424kbps를 지원하고 있으며, SMIC 180㎚ mixed-mode 공정을 사용하여 제작되어졌다. 제작된 칩의 기능과 성능을 검증하기 위하여 혈당측정기에 적용을 하여 NFC 혈당측정기 시스템을 구현하였는데, 이 구현된 시스템도 본 논문에 기술하였다.

Fully integrated circuit chip of microelectronic neural bridge

Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-μm CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is ±2.5 V, and the chip area is 1.21 × 1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved.

Electromagnetic Motion Device Based on LPC2131 of PID Control

Design of a ARM7 LPC2131 as the control core, through the H bridge chip LN298 driver power through the coil produces a changing magnetic field, the magnetic deflection force start swinging of the swing rod, the angle sensor (model MPU6050) feedback magnet swing angle signal, control coil magnetic field by using PID technology, so as to the electromagnetic force to precisely control the pendulum swing angle of the objective, by the TFT liquid crystal display pendulum swing angle, cycle, response time, stop time.

Thermal and Flow Fields In Single Board Computer Cabin Systems Using CFD Analysis

A detailed computational fluid dynamics (CFD) analysis of the cooling of a single board computer (SBC) cabin system is performed using the CFD software FLO EFD 9.0. Air-cooling and water-cooling are used for all major heat generating components with the attached heat sinks in it. North bridge chip, SODIMM memory module and south bridge chip are cooled by airflow. A liquid-cooling system with the microchannel heat sink is used to enhance heat transfer from the CPU. The simulation results show that all the heat generating components by this liquid-cooling system can meet their thermal design requirements. 36W CPU with H-shaped fractal-like microchannel heat sink can be maintained below 42°C at the inlet flow rate of 1.0 ml/s and pumping power of 0.06 W. Also it is decreased by 56% relative to forced air-cooling only.

The Study of the PCI Bus Expansion Based on PCI Bridge Chip

PCI (Peripheral Component Interconnect) bus is a high-performance local bus, is put forward to meet the high-speed data transmission between peripherals and host. The CPCI technology is adapted from PCI-based, it conforms to the PCI bus standard and mature European card mechanical standards , supports hot-swap capability, has advantage of the more stronger, more reliable, use and maintenance simply. Can break through the limitations of the PCI card via the PCI bridge technology to achieve PCI to CPCI conversion, the paper introduces the principle of the PCI-PCI bridge technology and in-depth analysis of a typical bridge chip PCI2050, based on a PCI card circuit design example, and provide a reference for the type of system design and verification.

800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V unidirectional byte-wide point-to-point source-synchronous double data-rate (DDR) interface for low power 800 MB/s operation in a ring topology. Interface power is reduced by shutting down the phase-locked loop in every second MCP and alternating between edge aligned DDR clock and center aligned DDR clock for source-synchronous data transfer from MCP to MCP.

Design and Realization of Hand-Held Smart Electrothermal Umbrella Applied New Materials

In this paper, a new type of hand-held smart eletrothermal umbrella has been designed and realized. Bionic lotus leaf polymer film, which is hydrophobic, is applied as umbrella fabric. Based on micro controller unit STC12C5A60S2, the system starts work with temperature sampling of outdoor environment by temperature sensor chip DS18B20, when the temperature is lower than 10°C, high current half bridge chip BTS7970 drives the carbon- nanofiber- electrothermal -heating- film to work. Also, the system is equipped with manual -heating module. A LED light of caution stands on the top of the umbrella that can flicker following a regular pattern controlled by MCU. A LED highlight is mounted at the bottom of the hand handle in order to illuminate the ground at night. Additionally, a USB interface, which can provide 5V output, is reserved to charge exterior electric device. The whole system is powered by eight 18650 lithium batteries, when fully charged, they can support the system working 8 hours constantly. With a synthesis of aesthetic, pragmatic function which can be expanded, and high performance, this new type of umbrella enjoys broad market and perspective.

A Technology Realization of Train Control BTM Communication Based on PROFIBUS

Communications technology between BTM equipment has been monopolized by foreign companies, it is necessary to design and produce the BTM communication system of china’s independent intellectual property rights, and the application of the Bus technology is the main issue in communication. In this paper, we proposed a BTM communication technology of train control equipment based on PROFIBUS technology, and research the key issues of the implementation of the technology. In the schematic design, SPC3 bus bridge chip is used to set PROFIBUS-DP sub-station. The communication network of ROFIBUS-DP field bus between BTM of train control equipment and top MASTER is constructed. Also the implementation of the communication system is analyzed. The result proves that the technology does not only achieve the effective communication between multi-BTM and multi-MASTER but also improves the performance of the BTM system.

Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication

We report a new method that precisely self-aligns face-to-face semiconductor chips or wafers to enable communication between the chips using electromagnetic waves. Our alignment mechanism takes advantage of miniaturized versions of two of nature's idealized shapes: an inverse pyramidal shape defined by a self-terminating wet-etch process in silicon and micro-spheres with radii accurate to submicron accuracy. This approach allows chips to be packaged using passive alignment that is self locating and reaches nearly one micron level of chip misalignment tolerance. Packages for applications to capacitive and optical connections are presented. Additionally, we describe a physical architecture for a multi-chip array packages with ?bridge? and ?island? chips where the function of the bridge is to transfer electromagnetic signals between island chips using either capacitive or optical proximity communication. The bridge chip can provide a predetermined amount of compliance to help maintain alignment and thereby accommodate topology variants in first level package or in chip thickness when required. Experimental packages providing precise alignment between 1-D arrays and 2-D arrays of chips are presented. We show that our precision alignment mechanism enables high fidelity 10 Gb/s optical-proximity-communication with reflecting mirrors micro-machined into Silicon and co-integrated to low loss silicon-on-insulator waveguides for chip-to-chip communication. The alignment mechanism was also applied to a demonstration of chip-to-chip capacitive proximity communication in a linear array of six chips. Alignment measurements on a 4 × 4 array of chips are reported.

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Proximity Communication (PxC) facilitates the integration of VLSI chips in a package using near-field capacitive coupling between chips, eliminating the need for solder or wires for I/O at the chip-to-chip interface. PxC provides chip-to-chip interconnect with bandwidth density and energy per bit similar to on-chip I/O, enabling system on a chip performance within a package. We have built early packages to explore assembly concepts and developed test methods for verification of the PxC design space. This package started with an adhesively-bonded three-chip subassembly of two Island chips and one Bridge chip. The two outer Island chips were reflowed to an alumina ceramic substrate. In the resulting package, communication between chips was achieved using PxC from Island to Bridge and then from the Bridge to the other Island. We demonstrated the ability to detect the X, Y, and Z chip-to-chip relative location and the ability to steer PxC data to optimize signal integrity within the package. This paper describes the first demonstration of active monitoring of chip-to-chip alignment during thermal cycling, in a PxC-enabled package. Leveraging this work, future packages will better exploit PxC benefits such as free-space electrical interconnect and re-workability of multi-chip modules.

A novel bridge chip between an ATM and ethernet for ADSL in home networks

This study presents a novel bridge chip between an asynchronous transfer mode (ATM) and Ethernet for an asymmetric digital subscriber line (ADSL) in home network which fabricated in a standard 0.18-mum 1P6M CMOS process. The proposed bridge chip is an ASIC designed with hardware description language (HDL) and fabricated using a cell-based digital IC design flow. The proposed chip merges two independent chips; transmitter-end and receiver-end chips, into a single chip, and eliminate the RISC processor to reduce production cost. Moreover, system stability and transmission capacity are enhanced due to the small chip area. Chip specifications are a power supply of 1.8 V and system operating frequency of 50 MHz.

PCI card with DMA capabilities for digital imaging detectors

A readout card based on the standard PCI 32-bit/33 MHz bus has been developed for the fast readout of digital systems. The PCI card exploits a PCI bridge chip with Direct Memory Access (DMA) capabilities which permits to obtain a measured throughput up to 90 Mbytes/s. The PCI card has two high-density 80-pin connectors for data I/O; an external system acquisition card can be connected through two flat cables. A powerful programmable logic FPGA provides the management of the I/O lines; by default, 32 input and 32 output single-ended lines (CMOS) plus six LVDS lines are provided, but the FPGA allows several different I/O configurations depending on the specific application requirements. Another programmable device manages the control and status signals of the local bus and the Synchronous Static RAM available for data storage. Due to its main features like the configurable I/O patterns and the high throughput, this PCI card is suitable for applications like the fast readout of imaging acquisition systems.

Hierarchical indexing data structure method for verifying the functionality of the STI-to-PCI bridge chips of the IBM eServer z900

The IBM eServer z900 has an overall system I/O bandwidth which is three times that of IBM S/390® G5/G6 servers, necessitating the use of Self-Timed-Interface (STI)-to-Peripheral-Component-Interface (PCI) bridge chips to exploit this bandwidth. The chips are used to form a layer between the networking attachments of the z900 and its main storage complex. The layer adapts the high-speed point-to-point packet-oriented STI interface of the z900 to its multi-drop PCI bus structure. This paper describes a method for verifying the functionality of the STI-to-PCI bridge chips by implementing a hierarchical indexing method to support all address dispatching, data management, and data integrity checking. The method is at the core of the random-element-level verification methodology to support all data movement mainline testing of the z900. Monitors, checkers, and drivers were developed and integrated as part of the overall methodology to verify all external interfaces.

GMR and SDT sensor applications

Giant Magnetoresistance (GMR) and Spin Dependent Tunneling (SDT) material structures are highly sensitive to magnetic fields and can be miniaturized and integrated with silicon circuits. These characteristics lend themselves to several applications including magnetic field sensing, galvanic isolators, and array sensing. Designs of highly miniaturized digital magnetic sensors using both a GMR bridge chip and a signal conditioning chip in a single small package are being used in cylinder position applications. Isolators using integrated coils and GMR sensors with on-chip electronics offer speed enhancements over established opto-isolator technology, and may improve system performance where ground noise is a limiting factor. Arrays of GMR or SDT sensors could have applications in nondestructive evaluation, vehicle detection, and bio-assay applications, and with the on-chip intelligence available in these sensors, could lead to "brilliant" sensing.

Designing the MPC105 PCI bridge/memory controller

The MPC105 peripheral component interconnection bridge/memory controller provides a platform-specification-compliant bridge between Power PC microprocessors and the PCI bus. With it, designers can create systems using peripherals already designed for a variety of standard PC interfaces. This bridge chip also integrates a secondary cache controller and high-performance memory controller that supports DRAM or synchronous DRAM and ROM or flash ROM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>