Branch Currents Research Articles

An 8-nW Resistor-Less Bandgap Reference Based on a Single-Branch Floating PTAT Voltage

This letter presents an ultra low-power resistor-less bandgap reference circuit, which is based on the topology of a single-branch floating proportional-to-absolute-temperature (PTAT) voltage. By using a cascode high impedance current bias technique, the single-branch PTAT voltage can be directly floating on the complementary-to-absolute-temperature (CTAT) voltage generated by the $V_{EB}$ of the bipolar transistor. Ultra low power consumption is realized by the simple topology in the proposed method, which only needs a few current branches. Fabricated in 0.13- $\mu \text{m}$ CMOS process, this letter generates a 1.252-V bandgap reference voltage. The total power consumption is 8.26 nW with a 1.4-V supply voltage. Without a resistor, this letter can achieve a small active area of 0.017 mm2. The average value of the temperature coefficient is 68 ppm/°C from −20 °C to 110 °C, and the line regulation is 0.019 %/V.

An Auxiliary Fault Identification Strategy of Flexible HVDC Grid Based on Convolutional Neural Network With Branch Structures

Lightning disturbance may be misjudged as dc fault by the primary protection in the flexible high voltage dc (HVDC) grid. To solve this problem, an auxiliary fault identification strategy based on convolutional neural network with branch structures (BR-CNN) is proposed in this paper. In the proposed scheme, the voltage and current characteristic matrix is constructed as the input matrix of BR-CNN model and the output categories include positive pole-to-ground (PTG) fault and lightning disturbance. Voltage and current branches are constructed to extract high-level local features of input data layer by layer, and main branch is designed to realize the comprehensive utilization of voltage and current information. Through autonomous learning of the model, the nonlinear mapping relationship between input and output is constructed. The method only uses the single-terminal quantities, and can be used as an auxiliary criterion to improve the reliability of the primary protection. The test results verify the effectiveness of the method, and the recognition accuracy is better than the traditional classification models.

A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS

A fully integrated K-band dual down-conversion receiver for phased array radar applications in 90 nm CMOS is presented. The receiver utilizes the dual down-conversion architecture to achieve superior performance. The integrated 1.15 GHz image-rejection filter (IRF) provides enough wideband (22 MHz) image rejection ratio at 140 MHz offset before the second down-conversion by utilizing the Q-enhancing and frequency staggering techniques to compensate the component loss. The low noise amplifier realizes the single-to-differential-ended conversion at the input with a transformer and achieves good common-mode rejection. The 70 MHz intermediate frequency baseband consists of two cascaded 3rd-order band-pass active RC filters (BPFs) and one automatic gain control (AGC) loop, with the integrator frequency compensation technique to lower down the requirements on the embedded Op-Amps. Two phase-locked loop (PLL) frequency synthesizers are integrated to provide the local oscillation (LO) signals for the down-conversions, where the matching of the charge-pump is improved by adding one extra current compensation branch. The measurements of the prototype show that the receiver converts the targeted mm-wave signal to 70 MHz intermediate frequency while achieving 8.3 dB noise figure (NF), 51-95 dB variable gain range and >45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth. The receiver draws 74 mA current (excluding 2 PLLs) from the 1.2 V power supplies and occupies a core area of 4.58 × 0.53mm 2 (excluding 2 PLLs).

Short Circuit Fault Discrimination Using SiC JFET Based Self-Powered Solid State Circuit Breakers in a Residential DC Community Microgrid

This article identifies and validates the use of ultrafast silicon carbide (SiC) junction field effect transistor (JFET)-based self-powered solid-state circuit breakers (SSCBs) as the enabling protective device for a 340 Vdc residential dc community microgrid. These SSCBs will be incorporated into a radial distribution system in order to enhance fault discrimination through autonomous operation. Because of the nature and characteristics of short-circuit fault inception in dc microgrids, the time–current trip characteristics of protective devices must be several orders of magnitude faster than conventional circuit breakers. The proposed SSCBs detect short-circuit faults by sensing the sudden voltage rise between its two power terminals and draw power from the fault condition itself to turn off SiC JFETs and then, coordinate with no-load contacts that can isolate the fault. Depending upon the location of the SSCBs in the microgrid, either unidirectional or bidirectional implementations are incorporated. Cascaded SSCBs are tuned using a simple resistor change to enable fault discrimination between upstream high-current feeds and downstream lower current branches. Operation of one of the SSCBs and three in cascaded arrangements are validated both in simulation and with a hardware test platform. Thermal impact on the SSCB is discussed as well. The target application is a residential dc microgrid that will be installed as part of a revitalization effort of an inner city Milwaukee neighborhood.

Technique for Measuring Magnitudes and Phases of Voltage and Current in the Band-Selective Parallel LCR Circuit

The current in the parallel LCR (inductor, capacitor and resistor) circuit depends not only on the magnitude of the applied electromotive force (emf) but also on its frequency. The circuit current in the parallel LCR circuit becomes very small in the resonating region, but at the same time, the potential difference across the LC tank becomes very large. These results are justified if there is a large induced current in the LC tank in such a way that the inductive and capacitive branch currents are nearly out of phase so that the vector sum of the currents be minimal. This theory can be verified by inserting a small series resistor in each branch. Finally, calculated magnitudes and phases of the potential differences across the newly connected resistors which are directly related to the magnitudes and phases of corresponding branch currents verify the theory.

Optimal Siting and Sizing of Distributed Generation Based on Improved Nondominated Sorting Genetic Algorithm II

With the development of distributed generation technology, the problem of distributed generation (DG) planning become one of the important subjects. This paper proposes an Improved non-dominated sorting genetic algorithm-II (INSGA-II) for solving the optimal siting and sizing of DG units. Firstly, the multi-objective optimization model is established by considering the energy-saving benefit, line loss, and voltage deviation values. In addition, relay protection constraints are introduced on the basis of node voltage, branch current, and capacity constraints. Secondly, the violation constrained index and improved mutation operator are proposed to increase the population diversity of non-dominated sorting genetic algorithm-II (NSGA-II), and the uniformity of the solution set of the potential crowding distance improvement algorithm is introduced. In order to verify the performance of the proposed INSGA-II algorithm, NSGA-II and multiple objective particle swarm optimization algorithms are used to perform various examples in IEEE 33-, 69-, and 118-bus systems. The convergence metric and spacing metric are used as the performance evaluation criteria. Finally, static and dynamic distribution network planning with the integrated DG are performed separately. The results of the various experiments show the proposed algorithm is effective for the siting and sizing of DG units in a distribution network. Most importantly, it also can achieve desirable economic efficiency and safer voltage level.

A Low-Power Tunable Square-Wave Generator for Instrumentation Applications

In this article, a low-power fully on-chip tunable amplitude and frequency waveform generator (WFG) is proposed. In the proposed architecture, frequency and amplitude are tuned by varying the currents in the respective branches. The waveform generator is designed and fabricated in the United Microelectronics Corporation (UMC) 180-nm CMOS process technology with a 1.8-V supply. It generates a square wave of 50% duty cycle, and the output is symmetric with respect to the common-mode voltage. The measured results show tuning of amplitude from 500 mVpp to 1.15 Vpp and frequency from 50 to 650 kHz approximately. It consumes $620~\mu \text {W}$ of power while occupying 0.03-mm2 silicon area only, making it suitable for low-power integrated system applications.

Improved Current Control for a Quasi-Two-Level PWM-Operated Modular Multilevel Converter

Quasi-Two-Level PWM Operation of modular multilevel converters enables a significantly smaller amount of installed module capacitance, even with low output frequencies required for machine drives. This article presents an implementation of this operation mode with an improved current control that leads to fast and precise current transitions. The proposed current control combines a deadbeat controller with a simple hysteresis controller that uses a predictive estimation of branch currents, which are both implemented using an FPGA. The enhanced performance of the proposed control is demonstrated by a comparison to the original one. Experimental results on a laboratory prototype prove the feasibility of Quasi-Two-Level PWM Operation as a machine drive and validate the advantage of reduced overvoltages with long machine cables in comparison to those of conventional two-level inverters.

Technical Feasibility of Arch Branched Endograft Repair in Type A Aortic Dissection with Prior Ascending Aortic Replacement

Introduction - Ascending aortic replacement is a common emergency procedure for treatment of acute type A dissection. Secondary open or endovascular intervention for residual arch pathologies is however difficult due to adhesions, short prosthetic grafts, and distorted anatomy. Aortic arch branched stent graft has emerged as a potential solution for these patients. The aim of this study is to evaluate the technical feasibility of two current aortic arch branch stent grafts in patients who had prior ascending aortic replacement. Methods - All patients who had a prosthetic ascending aortic replacement for acute type A dissection in a single institution between January 2013 and December 2017 were included. Contrast CT images on follow up were analyzed on a 3D workstation. Morphologic parameters were measured individually including: (i) Ascending aorta: diameter, greater and lesser curvature length from the coronary origin, angulation of residual ascending aorta and prosthetic graft. (ii) aortic arch: width and height of the arch, tortuosity index. (iii) supra-aortic branches: diameter, separation, sealing length, dissection, and take-off clock positions. Each patient’s CT scan was individually evaluated for anatomical suitability for the Zenith arch branched device (Cook Medical) and Relay double-branch device (Bolton Medical) according to set selection criteria. Adverse anatomical factors were further identified including prosthetic aortic valve replacement, insufficient proximal landing length, incompatible landing zone diameter, severe angulation of prosthetic ascending aorta, hostile arch branches sealing zone, and insufficient innominate artery (IA) sealing zone. Results - CT images from 56 subjects (45 males, mean age 57±10.8 years) were reviewed. 45 patients had ascending aortic replacement alone, 7 had a Bentall procedure, and 4 underwent David procedure. Based on our evaluation results, 23 patients (41.1%) were good candidates for an endovascular arch branched device. It should be mentioned that two patients were suitable for Relay double-branch device but not for Zenith branched device because the former displays more accommodating for larger proximal landing diameter (<43mm) than the latter (<38mm). Eleven patients (19.6%) were deemed feasible, but prudent pre-operative planning is required due to complicated anatomy. The other 22 patients (39.3%) were unsuitable due to one or more exclusive criteria. Short prosthetic grafts (8), extreme graft angulations (11) and dissected supra-aortic branches (15) were the main reasons for exclusion. Conclusion - Endovascular repair is technically feasible in patients with prior ascending aortic replacement for type A dissection. Incompatible prosthetic ascending aorta and dissecting arch branches are the most common exclusive risk factors.

Implementation and Experimental Verification of a Novel Control Strategy for a UPFC-Based Interphase Power Controller

Replacing the phase shifting transformers of interphase power controller with a reduced rating dual unified power flow controller (UPFC) results in a unified interphase power controller (UIPC) with potential for enhanced performance. However, in most cases, the UPFC is controlled as a static phase shifter (SPS), producing marginal improvements. A control approach that allows the minimization of the power ratings of the series voltage source converters (VSCs) of the UIPC was recently proposed. For that, one has to define four control parameters, as opposed to only two in the SPS-based UIPC. This can be done off-line, by means of an optimization procedure that splits the desired transmission line current among the capacitive and inductive branches of the UIPC. In this paper, a control scheme is presented for the implementation of the novel technique. The current sharing factors obtained from the optimization are stored in a lookup table. The gating signals for the VSCs are generated using Park's transformation so as to synthesize the optimal UIPC inductive and capacitive branch currents with proportional resonant controllers and sinusoidal pulse width modulation. The transmission line angle, as well as the magnitude and phase of the desired transmission line current with respect to the voltage at the receiving end voltage, is assumed to be provided by a transmission system operator. Experimental results that include steady state and transient conditions are provided to prove its feasibility.

Design of CNTFET-Based CCII Using gm/ID Technique for Low-Voltage and Low-Power Applications

This paper introduces for the first time all the steps required in the optimal design of carbon nanotube field-effect transistor (CNTFET)-based second generation current conveyor (CCII) using transconductance-to-drain current ratio ([Formula: see text]) technique for low-voltage (LV) and low-power (LP) applications. The [Formula: see text] technique is a well-established methodology for CMOS analog IC design. However, the difference between CMOS and CNTFET is that CMOS has continuous width while the width of CNTFET is discrete and depends on different parameters like the number of tubes, pitch and diameter ([Formula: see text]) of the carbon nanotube (CNT). Therefore, there is a need for a design technique by which one can easily design analog circuits using CNTFETs. The CCII is based on two-stage op-amp and two inverters used as class AB amplifiers. The performance of CCII has been extensively examined in terms of DC, AC and transient responses of node voltages, branch currents and node impedances using HSPICE simulations. The CCII operates at [Formula: see text]0.5[Formula: see text]V and has 172[Formula: see text][Formula: see text]W of power consumption. The designed CCII provides very high 3-dB bandwidth (BW) for current gain ([Formula: see text][Formula: see text]GHz as well as voltage gain ([Formula: see text][Formula: see text]GHz.

A Direct Approach Method for Distribution System Load Flow Solutions

Load flow or power flow studies are plays vital role in power system operation and control. These load flows are used to find voltage profile, power flow and losses etc. at each and every buses and branches. Traditional LU decomposition and forward-backward methods are consuming more time to run load flows due to Jacobian matrix. The proposed solution A direct approach method for distribution load flow solutions does not required any Jacobian matrix to load flow solution, hence this solution is time efficient and robust. Using special properties of distribution networks two simple matrices are formed. One is bus injection to branch current and other branch current to bus voltage matrix, by multiplying these two matrices to obtain required load flow solution.Test results gives the clear picture about this method. This method having grate capacity touse in unbalanced multiphase distribution automation applications, mostly on very large distribution systems. This project tested with the input data of 15 bus and 33 bus radial distribution system and also a 9 bus system data which includes Distribution Generation.

When distributed switch-and-stay combining meets buffer in IoT relaying networks

This paper studies the IoT relaying networks, where one decode-and-forward (DF) relay equipped with a buffer helps determine whether to receive the data from the source or send the data to the destination. Moderate shadowing environments are considered and the source can also communicate with the destination through the direct link. Although the opportunistic selection (OS) technique can select one better branch among the direct and buffer-aided relay branches, it requires to estimate the channel parameters of two branches, and the branch switching may occur frequently. To deal with these disadvantages, we employ the distributed switch-and-stay combining (DSSC) technique for the buffer-aided relay network, in which the same branch goes on being employed until the current branch cannot support the data transmission no longer. In this protocol, the branch switching depends on the buffer state and the state transition in the buffer is also affected by the branch switching. For this communication scenario where the buffer meets the DSSC, we study the system performance by deriving the analytical outage probability and the asymptotic expression with high regime of transmit power. From the asymptotic expression, we find that DSSC can effectively exploit the system spatio-temporal resources and it obtains the same performance of the OS with ease of implementation. Moreover, the system performance improves with the buffer size. We finally provide some simulation and numerical results to demonstrate the merits of the DSSC-based buffer-aided IoT relaying networks.

Non‐pilot protection scheme for multi‐terminal VSC–HVDC transmission systems

High-voltage direct current (HVDC) transmission systems are nowadays ideal candidates for interconnecting renewable energy resources to the electrical grids. This study presents a communication-less protection scheme for HVDC transmission systems with a multi-terminal voltage source converter (VSC). The existence of a tie-busbar is also considered, which represents a challenge for protection selectivity functions without the aid of a communication channel. The proposed scheme identifies the faulted segment on either a DC busbar or a line segment based on monitoring the calculated rate of change of the current-to-voltage ratio. This criterion is sensitive to detect the faults as the current increases rapidly in a few milliseconds, while the voltage decreases in the same time frame remarkably. Once the fault detection criterion is satisfied, the faulted section can be identified by checking the summation and direction of all branch currents at each busbar individually without utilising communication links. For investigation purposes, the proposed scheme is tested via a four-terminal HVDC system with two tie-busbars. Different simulation cases are evaluated with a variety of fault conditions using MATLAB/SIMULINK. The results corroborate the reliability, security, and efficacy of the proposed protection scheme for multi-terminal HVDC transmission systems.

Charger/discharger DC/DC converter with interleaved configuration for DC‐bus regulation and battery protection

AbstractRegulation of DC‐bus voltages is important for the stable operation of different applications, like microgrids and electric vehicles, and it is usually performed by charging/discharging (C/D) batteries. Such C/D system is formed by a power converter and a control system, and it is aimed at guaranteeing the system stability and extending the battery life. To extend the battery life, it is important to reduce the battery current ripples, which is usually performed with interleaved converters and nonlinear controllers; however, most of those controllers do not provide the design procedure nor guarantee the system stability. This paper proposes a nonlinear control strategy to regulate the voltage in a DC‐bus by C/D a battery through a two‐branch interleaved Boost converter. The proposed control strategy is formed by two sliding mode controllers (SMCs), where the first one regulates the DC‐bus voltage by acting on the first converter branch and the second SMC controls the current in the second branch. The reference of the second SMC is generated from the delayed current of the first branch, in order to coordinate the controllers and to reduce the ripples in the battery current. The paper includes a procedure to design the two SMCs as well as simulation and experimental results to validate the proposed solution and to illustrate its performance. The results prove the system stability and its dynamic performance according to the design.

Optimal Sizing and Siting of DG in Electrical Networks based on Systematic method

In this paper a simple and an efficient technique for determining the size(s) and site(s) for Distributed Generation systems in electrical distribution systems is presented for power loss saving and voltage profile improvement, giving suitable weighing factors to each one of the considered objectives. For this purpose a method of analytic has been developed and used, which is based on change in real and reactive parts in the branch currents caused by the DG located, and is tested on a 69-bus electrical network. Obtained results shows best loss reduction as well as voltage profile enhancement of the network under consideration. Among various power factors assumed, the operation of Distributed Generation corresponding to load power factor can enhances the system performance greatly, compared to that at unity power factor.

Optimal sizing and location of multiple distributed generation for power loss minimization using genetic algorithm

This paper presents a Genetic Algorithm (GA) for optimal location and sizing of multiple distributed generation (DG) for loss minimization. The study is implemented on a 33-bus radial distribution system to optimally allocate different numbers of DGs through the minimization of total active power losses and voltage deviation at power constraints of 0 – 2 MW and 0 – 3 MW respectively. The study proposed a PQ model of DG and Direct Load Flow (DLF) technique that uses Bus Incidence to Branch current (BIBC) and Branch Current to Bus Voltage (BCBV) matrices. The result obtained a minimum base case voltage level of 0.9898 p.u at bus 18 with variations of voltage improvements at other buses after single and multiple DG allocations in the system. Besides, the total power loss before DG allocation is observed as 0.2243 MW, and total power loss after DG allocation was determined based on the power constraints. Various optimal locations were seen depending on the power limits of different DG sizes. The results have shown that the impact of optimal allocation and sizing of three DG is more advantageous concerning voltage improvement, reduction of the voltage deviation and also total power loss in the distribution system. The results obtained in the 0 – 2 MW power limit is consistent to the 0 – 3 MW power limits regarding the influence of allocating DG to the network and minimization of total power losses.

A Robust Optimal Coordinated Droop Control Method for Multiple VSCs in AC–DC Distribution Network

AC–DC hybrid distribution network is viewed as a featured system to efficiently connect to all kinds of power sources and loads. In order to improve the system robustness, adapting to random fluctuations of renewable energy sources, this paper proposed a robust optimal coordinated control method for multiple voltage source converters (VSCs) in AC–DC distribution network. A robust optimization model was established to co-optimize the slopes of active and reactive power droop control of VSCs with the aim to minimize the total network loss, while ensuring the system security. VSC capacity coupling and power flow constraints were both considered. Then, to enhance the computational tractability of the problem, based on the column-and-constraint generation algorithm, ${V^2} - P$ and ${V^2} - Q$ were implemented in the droop control schemes holding the linear feedback characteristic so that the non-convex max–min sub-problem can be transformed into a mixed integer second-order cone (SOC) programming problem. Furthermore, to increase the accuracy of SOC relaxation in the sub-problem, a current limit strategy was designed where the maximum possible network loss was pre-identified to restrain the feasible range of branch current. Numerical experiments suggest that the proposed coordinated control method can improve the system security with little extra economic cost, and the reliability of the results is enhanced by the proposed current limit strategy.

Accurate and Efficient Estimation of Short-Circuit Current for MTDC Grids Considering MMC Control

DC short-circuit current calculation for the modular multilevel converter based multi-terminal direct current (MMC-MTDC) grid is critical and fundamental in equipment selection and protection setting. The existing MTDC grid short-circuit current calculation methods suffer from low efficiency, poor adaptability, and inflexibility. To address these issues, this paper proposes an efficient and general companion circuit-based method to estimate the short-circuit currents of asymmetric bipolar MTDC grids. First, an MMC is equivalent to an RLC series circuit in parallel with a time-dependent controlled current source. The equivalent model considers not only the discharge currents of the sub-module capacitors but also the ac in-feed current determined by MMC controllers. Then, the equivalent model for a bipolar MTDC grid with the dedicated metallic return is established by combing the equivalent MMC model with the lumped model of the dc transmission lines. Next, the companion circuit method is employed to efficiently and readily solve the equivalent model of the dc grid to obtain post-fault branch currents and node voltages. Both theoretical analyses and intensive tests on the CIGRE benchmark MTDC grid and Zhangbei bipolar MTDC grid verify the improved accuracy, efficiency, adaptability, and flexibility of the presented method.

Discussing issues of health promotion and research in the context of primary care during the ongoing austerity period: an exploratory analysis from two regions in Greece.

BackgroundIn Greece, both Primary Health Care (PHC) system and National Health System (NHS) in general, were plagued by several inefficiencies even prior to the financial crisis; the imposed austerity measures dramatically worsened the level of health provision and access, especially for vulnerable social groups, resulting in an exacerbation of existing disparities and access gaps.Aim and methodsThe current branch study was conducted in two regions of Greece, namely Crete and Epirus, with the main aim of eliciting responses to gather baseline information regarding crucial PHC-related aspects, using questionnaires with dichotomous questions. Directors or managers (physicians who have been assigned administrative/governance duties), of the Primary Health Care Centres (PHCCs) in two Greek geographic and administrative regions of Crete and Epirus, were invited to participate and to contribute to the investigation of issues on the provision of prevention and health promotion services, e-health topics and primary care research. Thirty directors/managers were approached and twenty-eight agreed to participate. Data processing and analysis of the responses was performed for the completed questionnaires.ResultsData analysis did not demonstrate a surprisingly substantial deviation in the average score of positive responses of directors/managers in the PHCCs of Crete in comparison to those of directors/managers in the PHCCs of Epirus. The findings show that several gaps exist in terms of prevention and health promotion resources and activities in both regions, while e-health, electronic health record (EHR) and telemedicine services are poorly developed.ConclusionThe study confirms that the Greek PHC is characterized by several inefficiencies, which may affect the quality of the services provided. An overall deficit has been emerged for PHCCs in both regions, a fact that indicates crucial points lacking in terms of overall PHC provision, thus adversely impacting upon living conditions, health quality and prevention.