Bottom-gate Thin-film Transistors Research Articles

Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta).

A ternary gate-connected threshold switching thin-film transistor

Multi-valued logic has been a significant focus of research in various fields with the advancement of information technology. One approach to realizing ternary logic is integrating of a threshold switching (TS) device with a transistor, but this method often entails a complex fabrication process. This work suggests a ternary gate-connected threshold switching thin-film transistor (TS-TFT) by serially connecting the TS device with a bottom-gate thin-film transistor (TFT). The fabrication process is simplified with a structure that shares electrodes and insulators. Different threshold voltages from TS and TFT devices produce stable multiple states. The Pt/HfO2/TiN TS device has an electronic trapping/detrapping switching mechanism that exhibits low power consumption and high reliability. With the superior electrical performance of an amorphous indium gallium zinc oxide TFT, the TS-TFT has stable endurance. Furthermore, pulse switching and ternary inverter are demonstrated from the practical point of view.

Intense pulsed light annealing of solution-based indium–gallium–zinc–oxide semiconductors with printed Ag source and drain electrodes for bottom gate thin film transistors

In this study, an intense pulsed light (IPL) annealing process for a printed multi-layered indium–gallium–zinc–oxide (IGZO) and silver (Ag) electrode structure was developed for a high performance all-printed inorganic thin film transistor (TFT). Through a solution process using IGZO precursor and Ag ink, the bottom gate structure TFT was fabricated. The spin coating method was used to form the IGZO semiconductor layer on a heavily-doped silicon wafer covered with thermally grown silicon dioxide. The annealing process of the IGZO layer utilized an optimized IPL irradiation process. The Ag inks were printed on the IGZO layer by screen printing to form the source and drain (S/D) pattern. This S/D pattern was dried by near infrared radiation (NIR) and the dried S/D pattern was sintered with intense pulsed light by varying the irradiation energy. The performances of the all-printed TFT such as the field effect mobility and on–off ratio electrical transfer properties were measured by a parameter analyzer. The interfacial analysis including the contact resistance and cross-sectional microstructure analysis is essential because diffusion phenomenon can occur during the annealing and sintering process. Consequently, this TFT device showed noteworthy performance (field effect mobility: 7.96 cm2/V s, on/off ratio: 107). This is similar performance compared to a conventional TFT, which is expected to open a new path in the printed metal oxide-based TFT field.

355 nm Nanosecond Ultraviolet Pulsed Laser Annealing Effects on Amorphous In-Ga-ZnO Thin Film Transistors.

Bottom-gate thin-film transistors (TFTs) with n-type amorphous indium-gallium-zinc oxide (a-IGZO) active channels and indium-tin oxide (ITO) source/drain electrodes were fabricated. Then, an ultraviolet (UV) nanosecond pulsed laser with a wavelength of 355 nm was scanned to locally anneal the active channel at various laser powers. After laser annealing, negative shifts in the threshold voltages and enhanced on-currents were observed at laser powers ranging from 54 to 120 mW. The energy band gap and work function of a-IGZO extracted from the transmittance and ultraviolet photoelectron spectroscopy (UPS) measurement data confirm that different energy band structures for the ITO electrode/a-IGZO channel were established depending on the laser annealing conditions. Based on these observations, the electron injection mechanism from ITO electrodes to a-IGZO channels was analyzed. The results show that the selective laser annealing process can improve the electrical performance of the a-IGZO TFTs without any thermal damage to the substrate.

Improved reliability of a-IGZO thin-film transistor under positive gate bias stress by utilizing NH3 plasma treatment

In this paper, the degradation mechanisms of the bottom-gate amorphous InGaZnO thin film transistors (a-IGZO TFTs) under positive gate bias stress (PBS) are investigated. The PBS-induced degradation can be attributed to the electron capture at the interface of the gate insulator and a-IGZO and the generation of oxygen interstitial defects (Oi) in a-IGZO. The oxygen interstitial defect density (NOi) can be calculated by the degradation of SS during recovery after PBS. It is found that the proportion of degradation caused by Oi increases with the increased a-IGZO thickness. By utilizing NH3 plasma treatment, the threshold voltage shift was reduced by >40 % under PBS (@VG = 5 V, t = 1000s). Further analysis shows that NH3 plasma treatment can effectively suppress the electron capture at the interface and the generation of Oi during PBS. Thus, PBS reliability of a-IGZO TFTs is improved by the proposed method.

High performance IZO:P/IZO:Ni thin film transistor with double active layers

Staggered bottom-gate thin film transistor (TFT) with double active layers was successfully fabricated. IZO:P/IZO:Ni thin films were deposited on SiO2/p-Si substrate by radio frequency (RF) magnetron sputtering, IZO:P/IZO:Ni acted as double active layers. The optical transmittance of IZO: P and IZO:Ni thin films were over 80% in the wavelength of 400–800 nm. X-ray diffraction (XRD) patterns exhibited that the IZO:P and IZO:Ni films were amorphous under the annealing temperature of 265 ℃. Atomic force microscopy (AFM) images showed that IZO:P and IZO:Ni thin films had a low root-mean-square (RMS) roughness of 0.44 nm and 0.45 nm, respectively. The annealing temperature was 265 ℃, the obtained TFT with IZO:P/IZO:Ni double active layers structure showed excellent electrical properties, including a saturation mobility of 44.5 cm2 v−1 s−1, a threshold voltage of 1.3 V, a subthreshold swing of 0.35 V/dec, and an on/off current ratio of 3.8 × 108.

Study of Al/a-Si:H/SiO2/n-Si/Al based bottom gate thin film transistor using RPCVD SiO2 and PECVD a-Si:H thin films: probably needed focus for bio-sensing application

In the present study Al/a-Si:H/SiO2/n-Si/Al based bottom gate thin film transistor (BGTFT) was fabricated using remote plasma enhanced chemical vapor deposited (RPCVD) SiO2 and PECVD a-Si:H. The Al/a-Si:H/SiO2/n-Si/Al based bottom gate thin film transistor was studied with an intension to apply it for bio-sensing application. The transfer characteristics of BGTFT were studied. The values of Gdd are 3.14 × 10−7 S, 1.38 × 10−7 S, 3.34 × 10−8 S, 4.84 × 10−9 S & 1.57 × 10−10 S for gate voltage Vg = −2, −1, 0, 1 & 2 V respectively. The Gdd values are found to decrease with the increase of gate voltage (Vg). The values of Gdg are 5.36 × 10−8 S, 5.98 × 10−9 S, 7.28 × 10−7 S, 2.40 × 10−7 & 5.00 × 10−9 respectively for Vd = −2, −1, 0, 1 & 2 V. The present current level and the conductance of BGTFT is so large that it is not possible to detect the proteins and antibody as these bio-molecules have charge of the order of nano amps. Therefore it requires a needed focus to study the ferroelectric or high k material as the active material instead of a-Si:H for BGTFT for bio-sensing application as the ferroelectric materials have low conductance and channel current. This will be our future work to use ferroelectric or high k materials as the active materials of BGTFT.

Subthreshold Conduction of Disordered ZnO-Based Thin-Film Transistors.

This study presents the disorderedness effects on the subthreshold characteristics of atomically deposited ZnO thin-film transistors (TFTs). Bottom-gate ZnO TFTs show n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, degradable subthreshold swing. The charge-transport characteristics of the disordered semiconductor TFTs are severely affected by the localized trap states. Thus, we posit that the disorderedness factors, which are the interface trap capacitance and the diffusion coefficient of electrons, would result in the degradation. Considering the factors as gate-dependent power laws, we derive the subthreshold current-voltage relationship for disordered semiconductors. Notably, the gate-dependent disorderedness parameters are successfully deduced and consistent with those obtained by the gm/Ids method, which was for the FinFETs. In addition, temperature-dependent current-voltage analyses reveal that the gate-dependent interface traps limit the subthreshold conduction, leading to the diffusion current. Thus, we conclude that the disorderedness factors of the ZnO films lead to the indefinable subthreshold swing of the ZnO TFTs.

High-Speed Current Switching of Inverted-Staggered Bottom-Gate a-IGZO-Based Thin-Film Transistors with Highly Stable Logic Circuit Operations

High-speed electronic (HSE) systems are an emerging technology with potential applications in various fields, including biomedical imaging devices, display systems, ultrasound detectors, and object recognition. This report presents a study on low-temperature processed inverted-staggered bottom-gate a-IGZO thin-film transistors (TFTs) for measuring fast current switching at higher frequencies. The IGZO TFT exhibits an excellent mobility of 10.51 cm2/(V·s) and a higher on/off ratio of 3.2 × 105. Additionally, it displays highly stable and reliable gate-pulse switching at different frequencies ranging from 1 kHz to 0.2 MHz. Furthermore, logic operations such as inverter, NAND, and NOR gates were successfully performed using the enhancement-type device configuration. The results show stable and reliable voltage transfer responses with respect to the device configurations. Thus, this study not only enables the development of the applicability of the IGZO material in logic operations but also in HSE systems.

P-type nickel oxide deposited by reactive hollow cathode gas flow sputtering for the potential usage in thin-film transistors

Thin Nickel Oxide film were deposited by reactive pulsed-direct current hollow cathode gas flow sputtering. This unique technique allows for sputtering magnetic target materials with very high rates without magnetron. Deposition was carried out from a nickel target at room temperature. The influence of process parameters on optical, electrical, and structural film properties are investigated. High deposition rates of 6 nm/s and 2 nm/s are achieved for both direct current and pulsed-direct current power supply. All films are highly resistive and show p-type conduction that is tunable with oxygen flow. The films exhibit optical band gap around 3,8 eV depending on process parameters like oxygen flow and pulsing parameter. Secondary electron microscopy shows pillar-like growth perpendicular to the surface, while grazing incidence X-ray diffraction reveals smaller, randomly oriented crystals. Electrical properties of the films were tested by Hall measurements, revealing mobilities in the range of 1 cm2Vs. The nano crystalline thin films were tested in staggered bottom gate Thin-Film Transistor structures for potential use as channel layer.

Fabrication and characterization of ultra-thin ZnO based bottom gate thin film transistor for UV detection

An RF sputtered ZnO thin film was utilized in a thin film transistor (TFT) fabrication. The film was fabricated on SiO2 gate oxide that was thermally grown on Si Substrate. Few lithography steps were used to fabricate the device and device structure was proved to be a bottom gate TFT. The grown film was ultra thin of 25 nm thickness and the Si wafer was n-type. The structural and optical properties of ZnO films were investigated by Field Emission Scanning Electron Microscopy (FESEM), X-Ray Diffraction (XRD) and Photo luminance (PL) spectroscopy. The photo luminance study confirmed a high-quality absorbance in UV spectra and relatively good transmittance in the visible region. The electrical performance of the transistor was studied using Proxima B1500 and the on/off current ratio was measured to be ∼107. The ZnO bottom gate TFT is simulated using the commercial TCAD tool Silvaco ATLAS™. Later the simulated I–V characteristic of the device is compared with the experimental one and both are in fairly good agreement. Further the UV detection capability of the fabricated device was studied by using UV LED light of 365 nm wavelength. The measured value of threshold voltage was found to be 9V under dark light and 10V under UV light.

The impact of multi-layered dielectrics on the electrical performance of ZnO thin-film transistors

The electrical performance of ZnO thin film transistors (TFTs) fabricated on three different dielectric layers is investigated using an inverted staggered bottom gate thin film transistor structure. This work demonstrated the potential of integrating high-k dielectrics in ZnO TFTs in a dielectric multi-layered stack using SiO2 as the support layer for all the hero-dielectrics layers. In order to achieve this, ZnO thin film semiconducting layers were deposited at room temperature by radio frequency (RF) sputtering method and with no post deposition heat treatment, making them suitable candidates for low cost large area electronics on low temperature substrates (such as plastics). The dielectric films investigated were aluminium nitride (AlN), silicon nitride (SiN) and silicon dioxide (SiO2). The effective mobility of SiN devices was about half that observed in AlN devices. However, the dielectric layers exhibited hysteresis of approximately 0 V, 2 V and 7 V for the SiO2, AlN and SiN respectively. In addition, SiO2 TFTs have lowest threshold voltage (VT) and turn-on voltage (Von). The capacitance-voltage measurement for these device show that the flatband and threshold voltage of SiN and AlN MOS capacitors shifted towards more negative voltages instead when compared with the single layer SiO2 devices.

Serially connected tantalum and amorphous indium tin oxide for sensing the temperature increase in IGZO thin-film transistor backplanes

A temperature sensor embedded in an In-Ga-Zn oxide (IGZO) TFT was evaluated after fabrication to facilitate monitoring of the temperature distribution on a thin-film transistor (TFT) array. Because the proposed temperature sensor uses the same material as the TFT, no additional process or material is required. Moreover, it can be used as a light shield layer because the temperature sensor is located on a TFT. The temperature sensor used in this study was serially connected to indium tin oxide and a metal. As the temperature increased to 120 °C, the output voltage of the temperature sensor increased to 176.6 mV. The sensitivity, hysteresis, and repeatability were 0.85 mV/°C, 3.56 %, and 0.04 %, respectively. The temperature sensor was integrated into an amorphous IGZO bottom-gate TFT. The TFT exhibited a field-effect mobility of 8.2 cm2V−1·s−1 and threshold voltage of 5.2 V. As the drain current increased from 300 µA to 1.1 mA, the temperature increased from 26 to 32.9 °C, and the output voltages of the temperature sensor augmented from 66 to 76 mV. The integrated temperature sensors enable us to measure the temperature distribution in a display panel and compensate for image deterioration due to increased temperature.

Physical model of a local threshold voltage shift in InGaZnO thin-film transistors under current stress for instability-aware circuit design

In this study, the degradation mechanism of bottom-gate InGaZnO thin-film transistors (IGZO TFTs) under current stress (CS) was analyzed. The threshold voltage shift (ΔVT) caused by different oxygen flow rates (OFR) and various VGS and VDS combinations was measured and analyzed. In addition, the CS-induced ΔVT was modeled and quantified using the parameters of the multiple stretched exponential functions (MSEF). The quantitative parameters for the lateral field-induced degradation mechanisms were analyzed for each source and drain region. Also, the activation energy (EA) for each mechanism was extracted, and it was confirmed that the donor creation near the drain was caused by oxygen vacancy ionization. Finally, the parameters of subgap density-of-states were extracted using the monochromatic photonic capacitance-voltage (MPCV) method. The proposed physical ΔVT model of IGZO TFT under CS should be helpful in the design of instability-aware circuits.

Bottom-Gated ZnO TFT Pressure Sensor with 1D Nanorods.

In this study, a bottom-gated ZnO thin film transistor (TFT) pressure sensor with nanorods (NRs) is suggested. The NRs are formed on a planar channel of the TFT by hydrothermal synthesis for the mediators of pressure amplification. The fabricated devices show enhanced sensitivity by 16~20 times better than that of the thin film structure because NRs have a small pressure transmission area and causes more strain in the underlayered piezoelectric channel material. When making a sensor with a three-terminal structure, the leakage current in stand-by mode and optimal conductance state for pressure sensor is expected to be controlled by the gate voltage. A scanning electron microscope (SEM) was used to identify the nanorods grown by hydrothermal synthesis. X-ray diffraction (XRD) was used to compare ZnO crystallinity according to device structure and process conditions. To investigate the effect of NRs, channel mobility is also extracted experimentally and the lateral flow of current density is analyzed with simulation (COMSOL) showing that when the piezopotential due to polarization is formed vertically in the channel, the effective mobility is degraded.

High-performance Atomic-Layer-Deposited SnO thin film transistors fabricated by intense pulsed light annealing

In this study, SnO films were grown by atomic layer deposition using Sn(dmamp)2 and H2O as the Sn-precursor and reactant, respectively, at a low temperature of 120 °C. Intense pulsed light (IPL) annealing was employed to obtain high-quality polycrystalline SnO films with excellent hole transport characteristics. The amorphous SnO film could be crystallized by IPL annealing, particularly at a light pulse number between 200 and 300, and the degree of crystallinity increased with increasing IPL treatment. The Sn2+ oxidation state of the SnO film was almost maintained after IPL annealing, with no apparent phase transformation from SnO to SnO2 or Sn. In addition, the IPL-annealed SnO films exhibited a smooth surface morphology with a root-mean-squared roughness of 0.22–0.50 nm. Finally, bottom-gated staggered-structured thin-film transistors (TFTs) were fabricated with 6–30 nm-thick IPL-annealed SnO channel layers. Excellent p-type SnO-based TFT performance was achieved with a field-effect hole mobility of 4.31 cm2/V·s and an on-to-off current ratio of 8.2 × 104.

Blue laser diode annealing-enhanced bottom-gate low-temperature Poly-Si thin-film transistors

The low-temperature poly-Si (LTPS) thin-film transistor (TFT) with bottom-gate architecture was successfully developed using the blue laser diode annealing (BLDA) technology. The amorphous silicon (a-Si) was successfully recrystallized by BLDA into LTPS with grain sizes ranging from 0.1 μm to 0.3 μm. With the proper pre-dehydration treatment of a-Si and optimized BLDA conditions, the bottom-gate LTPS TFTs achieved superior performance than a-Si TFTs, including a mobility up to 15.87 cm2/Vs. Moreover, such BLDA-enabled bottom-gate LTPS TFT is fully compatible with the incumbent a-Si production line, thus providing a new cost-efficient technology for large-area electronics.

Improvement of deposition characteristics of silicon oxide layers using argon-based atmospheric-pressure very high-frequency plasma

We have investigated the deposition characteristics of silicon oxide (SiOx) layers in atmospheric pressure (AP) argon (Ar)-based plasma at a substrate temperature of 120 °C. A 150 MHz, very high-frequency (VHF) power is effectively used for exciting stable and uniform hexamethyldisiloxane (HMDSO)-oxygen (O2) fed plasma under AP. The microstructure of the SiOx layers is discussed in comparison with that by using helium (He)-based plasma. In the case of depositions with He/HMDSO/O2 plasma, SiO2-like films with uniform thickness, which have sufficient compactness to be used as the gate dielectrics of bottom-gate thin film transistors, can be obtained by moving substrate at a constant speed during the plasma operation. However, the decrease in the total gas flow rate (increase in the gas residence time in the plasma) causes the increase in the participation of nanoparticles to the film growth, which might result in the deterioration of film quality. Shortening the electrode length is effective for avoiding the incorporation of nanoparticles into the growing SiOx films. On the other hand, when Ar/HMDSO/O2 plasma is used, no deterioration of film compactness is observed irrespective of the gas flow rate. The results obtained in this study demonstrate the effectiveness of the VHF excitation of AP plasma on the generation of stable and uniform glow discharge without using He, which will lead to the development of a highly efficient and reduced cost formation process of good-quality SiOx films.

Bottom gate single crystal Si thin-film transistors fabricated by all sputtering processes

Single-crystal Si (c-Si) bottom-gate thin-film transistors (BG-TFTs) were fabricated using all sputtering processes. Laser doping from sputter-deposited Sb-doped amorphous Si film was proposed, by which n+ c-Si with resistivity and contact resistivities of 1.5 × 10−3 Ωcm and 2.1 × 10−5 Ωcm2, respectively, were fabricated. In addition, thin (50 nm) and low-heat conductive titanium was proposed for BG to realize continuous lateral crystal growth in Si film above the edge of BG. The fabricated n-channel c-Si BG-TFTs exhibited a field-effect mobility of 75 ± 21 cm2 V−1s−1, subthreshold swing of 0.612 ± 0.110 Vdec−1, and threshold voltage of 4.9 ± 1.38 V. Lack of bottom Si/SiO2 interface quality was indicated to be the origin of insufficient mobility.

Solution processed low-voltage metal-oxide transistor by using TiO2/Li–Al2O3 stacked gate dielectric

A solution processed top-contact bottom-gated SnO2 thin-film transistor (TFT) has been fabricated using a TiO2/Li–Al2O3 bilayer stacked gate dielectric that show operating voltage of this TFT within 2.0 V. It is observed that the bilayer dielectric has much higher areal capacitance with lower leakage current density that significantly improve the overall device performance of TFT. The TFT with bilayer gate dielectric shows an effective carrier mobility (μsat) of 9.2 cm2 V−1 s−1 with an on/off ratio of 7.1 × 103 which are significantly higher with respect to the TFT with a single layer Li–Al2O3 gate dielectric. The origin of this improvement is due to the Schottky junction between the highly doped silicon (p++-Si) and TiO2 of bilayer stacked dielectric that induced electrons to the channel which reduces the dielectric/semiconductor interface trap-state. This investigation opens a new path to develop TFT device performance using a suitable bilayer stack of gate dielectric.