Boolean Circuits Research Articles

Boolean Circuits, Tensor Ranks, and Communication Complexity

We investigate two methods for proving lower bounds on the size of small-depth circuits, namely the approaches based on multiparty communication games and algebraic characterizations extending the concepts of the tensor rank and rigidity of matrices. Our methods are combinatorial, but we think that our main contribution concerns the algebraic concepts used in this area (tensor ranks and rigidity). Our main results are following. (i) An $o(n)$-bit protocol for a communication game for computing shifts, which also gives an upper bound of $o(n^2)$ on the contact rank of the tensor of multiplication of polynomials; this disproves some earlier conjectures. A related probabilistic construction gives an $o(n)$ upper bound for computing all permutations and an $O(n\log\log n)$ upper bound on the communication complexity of pointer jumping with permutations. (ii) A lower bound on certain restricted circuits of depth 2 which are related to the problem of proving a superlinear lower bound on the size of logarithmic-depth circuits; this bound has interpretations both as a lower bound on the rigidity of the tensor of multiplication of polynomials and as a lower bound on the communication needed to compute the shift function in a restricted model. (iii) An upper bound on Boolean circuits of depth 2 for computing shifts and, more generally, all permutations; this shows that such circuits are more efficient than the model based on sending bits along vertex-disjoint paths.

Nanoelectronic architecture for Boolean logic

A nanoelectronic implementation of Boolean logic circuits is described where logic functionality is realized through charge interactions between metallic dots self-assembled on the surface of a double-barrier resonant tunneling diode (RTD) structure. The primitive computational cell in this architecture consists of a number of dots with nearest neighbor (resistive) interconnections. Specific logic functionality is provided by appropriate rectifying connections between cells. We show how basic logic gates, leading to combinational and sequential circuits, can be realized in this architecture. Additionally, architectural issues including directionality, fault tolerance, and power dissipation are discussed. Estimates based on the current-voltage characteristics of RTD's and the capacitance and resistance values of the interdot connections indicate that static power dissipation as small as 0.1 nW/gate and switching delay as small as a few picoseconds can be expected. We also present a strategy for fabricating/synthesizing such systems using chemical self-organizing/self-assembly phenomena. The proposed synthesis procedure utilizes several chemical self-assembly techniques which have been demonstrated recently, including self-assembly of uniform arrays of close-packed metallic dots with nanometer diameters, controlled resistive linking of nearest neighbor dots with conjugated organic molecules and organic rectifiers.

Monotone real circuits are more powerful than monotone boolean circuits

Recently Pavel Pudlak (1995) and independently Armin Haken and Steve Cook (1995) gave exponential lower bounds for the size of monotone real circuits computing clique type functions. In both cases, the lower bound was established in the monotone boolean case and then extended to the real case. This left open the question of whether monotone boolean circuits are in general polynomially equivalent to monotone real circuits for boolean functions. By a simple construction, we show that monotone real circuits are exponentially more powerful than general boolean circuits by proving that linear-size log-depth fan in 2 monotone real circuits can compute any slice function.

Zero-Knowledge Proofs for Finite Field Arithmetic or: Can Zero-Knowledge be for Free?

We present zero-knowledge proofs and arguments for arithmetic circuits over finite prime fields, namely given a circuit, show in zero-knowledge that inputs can be selected leading to a given output. For a field GF(q), where q is an n-bit prime, a<br />circuit of size O(n), and error probability 2^−n, our protocols require communication of O(n^2) bits. This is the same worst-cast complexity as the trivial (non zero-knowledge)<br />interactive proof where the prover just reveals the input values. If the circuit involves n multiplications, the best previously known methods would in general require communication<br />of Omega(n^3 log n) bits.<br />Variations of the technique behind these protocols lead to other interesting applications.<br />We first look at the Boolean Circuit Satisfiability problem and give zero-knowledge proofs and arguments for a circuit of size n and error probability 2^−n in which there is an interactive preprocessing phase requiring communication of O(n^2)<br />bits. In this phase, the statement to be proved later need not be known. Later the prover can non-interactively prove any circuit he wants, i.e. by sending only one message, of size O(n) bits.<br />As a second application, we show that Shamirs (Shens) interactive proof system for the (IP-complete) QBF problem can be transformed to a zero-knowledge proof<br />system with the same asymptotic communication complexity and number of rounds. The security of our protocols can be based on any one-way group homomorphism with a particular set of properties. We give examples of special assumptions sufficient for this, including: the RSA assumption, hardness of discrete log in a prime order group, and polynomial security of Die-Hellman encryption. We note that the constants involved in our asymptotic complexities are small enough for our protocols to be practical with realistic choices of parameters.

Majority-Vote Cellular Automata, Ising Dynamics, and P-Completeness

We study cellular automata where the state at each site is decided by a majority vote of the sites in its neighborhood. These are equivalent, for a restricted set of initial conditions, to nonzero probability transitions in single spin-flip dynamics of the Ising model at zero temperature. We show that in three or more dimensions these systems can simulate Boolean circuits of AND and OR gates, and are therefore P-complete. That is, predicting their state t time-steps in the future is at least as hard as any other problem that takes polynomial time on a serial computer. Therefore, unless a widely believed conjecture in computer science is false, it is impossible even with parallel computation to predict majority-vote cellular automata, or zero-temperature single spin-flip Ising dynamics, qualitatively faster than by explicit simulation.

Error Correcting Codes, Perfect Hashing Circuits, and Deterministic Dynamic Dictionaries

We consider dictionaries of size n over the finite universe U ={0, 1}^w and introduce a new technique for their implementation: error correcting codes. The use of such codes makes it possible to replace the use of strong forms of hashing, such as universal hashing, with much weaker forms, such as clustering.<br />We use our approach to construct, for any epsilon > 0, a deterministic solution to the dynamic dictionary problem using linear space, with worst case time O(n) for insertions and deletions, and worst case time O(1) for lookups. This is the first deterministic solution to the dynamic dictionary problem with linear space, constant query time, and non-trivial update time. In particular, we get a solution to the static dictionary problem with O(n) space, worst case query time O(1), and deterministic initialization time O(n^(1+epsilon)). The best previous deterministic initialization time for such dictionaries, due to Andersson, is O(n^(2+epsilon)). The model of computation for these bounds is a unit cost RAM with word size w (i.e. matching the universe), and a standard instruction set. The constants in the big-O's are independent upon w. The solutions are weakly non-uniform in w, i.e. the code of the algorithm contains word sized constants, depending on w, which must be computed at compile-time, rather than at run-time, for the stated run-time bounds to hold. <br />An ingredient of our proofs, which may be interesting in its own right, is the following observation: A good error correcting code for a bit vector fitting into a word can be computed in O(1) time on a RAM with unit cost multiplication. <br />As another application of our technique in a different model of computation, we give a new construction of perfect hashing circuits, improving a construction by Goldreich and Wigderson. In particular, we show that for any subset S of {0;1}w of size n, there is a Boolean circuit C of size O(w log w) with w inputs and 2 log n outputs so that the function defined by C is 1-1 on S. The best previous bound on the size of such a circuit was O(w log w log log w).

Algebraic Methods and Bounded Formulas

We present some algebraic tools useful to the study of the expressive power of bounded formulas in second-order arithmetic (alternatively, second-order formulas in finite models). The techniques presented here come from Boolean circuit complexity and are adapted to the context of arithmetic. The purpose of this article is to expose them to a public with interests ranging from arithmetic to finite model theory. Our exposition is self-contained.

Feasible Time-Optimal Algorithms for Boolean Functions on Exclusive-Write Parallel Random-Access Machines

It was shown some years ago that the computation time for many important Boolean functions of n arguments on concurrent-read exclusive-write parallel random-access machines (CREW PRAMs) of unlimited size is at least $\varphi (n) \approx 0.72\log _2 n$. On the other hand, it is known that every Boolean function of n arguments can be computed in $\varphi (n) + 1$ steps on a CREW PRAM with $n \cdot 2^{n - 1} $ processors and memory cells. In the case of the OR of n bits, n processors and cells are sufficient. In this paper, it is shown that for many important functions, there are CREW PRAM algorithms that almost meet the lower bound in that they take $\varphi (n) + o(\log n)$ steps but use only a small number of processors and memory cells (in most cases, n). In addition, the cells only have to store binary words of bounded length (in most cases, length 1). We call such algorithms “feasible.” The functions concerned include the following: the PARITY function and, more generally, all symmetric functions; a large class of Boolean formulas; some functions over non-Boolean domains $\{ 0, \ldots ,k - 1\} $ for small k, in particular, parallel-prefix sums; addition of n-bit numbers; and sorting ${n / l}$ binary numbers of length l. Further, it is shown that Boolean circuits with fan-in 2, depth d, and size s can be evaluated by CREW PRAMs with fewer than s processors in ,$\varphi (2^d ) + o(d) \approx 0.72d + o(d)$ steps. For the exclusive-read exclusive-write (EREW) PRAM model, a feasible algorithm is described that computes PARITY of n bits in $0.86\log _2 n$ steps.

On the computational power of DNA

We show how DNA-based computers can be used to solve the satisfiability problem for boolean circuits. Furthermore, we show how DNA computers can solve optimization problems directly without first solving several decision problems. Our methods also enable random sampling of satisfying assignments.

On the Circuit Complexity of Sigmoid Feedforward Neural Networks

This paper aims to examine the circuit complexity of sigmoid activation feedforward artificial neural networks by placing them amongst several classic Boolean and threshold gate circuit complexity classes. The starting point is the class NNk defined by Shawe-Taylor et al. (1992) Classes of feedforward neural nets and their circuit complexity. Neural Networks 5(6), 971–977. For a better characterisation, we introduce two additional classes NNkΔ and NNkΔ,ϵ having less restrictive conditions than NNk concerning fan-in and accuracy, and proceed to prove relations amongst these three classes and well established circuit complexity classes. For doing that, a particular class of Boolean functions FΔ is first introduced and we show how a threshold gate circuit can be recursively built for any fΔ belonging to FΔ. As the G-functions (computing the carries) are fΔ functions, a class of solutions is obtained for threshold gate adders. We then constructively prove the inclusions amongst circuit complexity classes. This is done by converting the sigmoid feedforward artificial neural network into an equivalent threshold gate circuit Shawe-Taylor et al. (1992). Each threshold gate is then replaced by a multiple input adder having a binary tree structure, relaxing the logarithmic fan-in condition from (Shawe-Taylor et al. 1992) to (almost) polynomial. This means that larger classes of sigmoid activation feedforward neural networks can be implemented in polynomial size Boolean circuits with a small constant fan-in at the expense of a logarithmic factor increase in the number of layers. Similar results are obtained for threshold circuits, and are liked with the previous ones. The main conclusion is that there are interesting fan-in dependent depth-size tradeoffs when trying to digitally implement sigmoid activation feedforward neural networks. Copyright © 1996 Elsevier Science Ltd

Binary Representations of Finite Fields and Their Application to Complexity Theory

Binary representations of finite fields are defined as an injective mapping from a finite field tol-tuples with components in {0, 1} where 0 and 1 are elements of the field itself. This permits one to study the algebraic complexity of a particular binary representation, i.e., the minimum number of additions and multiplications in the field needed to compute the binary representation. The two-way complexity of a binary representation is defined as the sum of the algebraic complexities of the binary representation and of its inverse mapping. Two particular binary representations are studied: the standard representation and the logarithmic representation. A method of surrogate computation is developed and used to deduce relationships between the algebraic complexities of certain functions. The standard representation of a finite field is shown to be among the two-way easiest representations of this field. In particular, the standard representation of a finite field with characteristicpis two-way easy wheneverp− 1 has only small prime factors. For any finite field having a two-way easy binary representation, the algebraic complexity in this field is shown to be essentially equivalent to Boolean circuit complexity. For any finite field, the Boolean circuit complexity of Zech's (or Jacobi's) logarithm is shown to be closely related to the Boolean circuit complexity of the discrete logarithm problem that is used in public-key cryptography.

Joint encryption and message-efficient secure computation

This paper addresses the message complexity of secure computation in the (passive adversary) privacy setting. We show that O(nC) encrypted bits of communication suffice for n parties to evaluate any boolean circuit of size C privately, under a specific cryptographic assumption. This work establishes a connection between secure distributed computation and group-oriented cryptography, i.e., cryptographic methods in which subsets of individuals can act jointly as single agents. Our secure computation protocol relies on a new group-oriented probablistic public-key encryption scheme with useful algebraic properties.

Boolean complexity classes vs. their arithmetic analogs

This paper provides logspace and small circuit depth analogs of the result of Valiant and Vazirani, which is a randomized (or nonuniform) reduction from NP to its arithmetic analog ⊕ P. We show a similar randomized reduction between the Boolean classes NL and semiunbounded fan-in Boolean circuits and their arithmetic counterparts. These reductions are based on the Isolation Lemma of Mulmuley, Vazirani, and Vazirani. Combinatorially our results can be viewed as simple (logspace) transformations of existential quantifiers into counting quantifiers in graphs and shallow circuits. © 1996 John Wiley & Sons, Inc.

Boolean complexity classes vs. their arithmetic analogs

This paper provides logspace and small circuit depth analogs of the result of Valiant and Vazirani, which is a randomized (or nonuniform) reduction from $NP$ to its arithmetic analog $\plusminus P$. We show a similar randomized reduction between the Boolean classes $NL$ and semiunbounded fan-in Boolean circuits and their arithmetic counterparts. These reductions are based on the Isolation Lemma of Mulmuley, Vazirani and Vazirani. Combinatorically our results can be viewed as simple (logspace) transformations of existential quantifiers into counting quantifiers in graphs and shallow circuits.

On the Fourier spectrum of monotone functions

In this paper, monotone Boolean functions are studied using harmonic analysis on the cube. The main result is that any monotone Boolean function has most of its power spectrum on its Fourier coefficients of degree at most O(√n) under any product distribution. This is similar to a result of Linial et al. [1993], which showed that AC 0 functions have almost all of their power spectrum on the coefficients of degree, at most (log n) O(1) , under the uniform distribution. As a consequence of the main result, the following two corollaries are obtained : -For any e > 0, monotone Boolean functions are PAC learnable with error e under product distributions in time 2 O((1/e) √ n) . -Any monotone Boolean function can be approximated within error e under product distributions by a non-monotone Boolean circuit of size 2 O(1/e √ n) and depth O(1/e √n). The learning algorithm runs in time subexponential as long as the required error is Ω(1/(√n log n)). It is shown that this is tight in the sense that for any subexponential time algorithm there is a monotone Boolean function for which this algorithm cannot approximate with error better than O(1/√n). The main result is also applied to other problems in learning and complexity theory. In learning theory, several polynomial-time algorithms for learning some classes of monotone Boolean functions, such as Boolean functions with O(log 2 n/log log n) relevant variables, are presented. In complexity theory, some questions regarding monotone NP-complete problems are addressed.

On the language of primitive words

A word is primitive if it is not a proper power of a shorter word. We prove that the set Q of primitive words over an alphabet is not an unambiguous context-free language. This strengthens the previous result that Q cannot be deterministic context-free. Further we show that the same holds for the set L of Lyndon words. We investigate the complexity of Q and L. We show that there are families of constant-depth, polynomial-size, unbounded fan-in boolean circuits and two-way deterministic pushdown automata recognizing both languages. The latter result implies efficient decidability on the RAM model of computation and we analyze the number of comparisons required for deciding Q. Finally we give a new proof showing a related language not to be context-free, which only relies on properties of semi-linear and regular sets.

On the number of ANDs versus the number of ORs in monotone Boolean circuits

Alon and Boppana showed that if a monotone Boolean function f of n variables can be computed by a monotone circuit containing k AND gates, where k ⪢ 1, then it can also be computed using a monotone circuit containing k AND gates and O(k(n + k)) OR gates. They note that their result is tight up to a logarithmic factor. Here we show that under the same assumption the function f can be computed using a monotone circuit containing k AND gates and O(k(n + k)log k) OR gates. This result is tight up to a constant factor. By duality the same result holds when the roles of the AND and OR gates are interchanged.

An Efficient Parallel Algorithm for the General Planar Monotone Circuit Value Problem

A planar monotone circuit (PMC) is a Boolean circuit that can be embedded in the plane and that contains only AND and OR gates. Goldschlager, Dymond, Cook, and others have developed $NC^2$ algorithms to evaluate a special layered form of a PMC. These algorithms require a large number of processors ($\Omega(n^6)$, where $n$ is the size of the input circuit). Yang and, more recently, Delcher and Kosaraju have given NC algorithms for the general planar monotone circuit value problem. These algorithms use at least as many processors as the algorithms for the layered case. This paper gives an efficient parallel algorithm that evaluates a general PMC of size $n$ in polylog time using only a linear number of processors on an exclusive read exclusive write parameter random-access machine (EREW PRAM). This parallel algorithm is the best possible to within a polylog factor and is a substantial improvement over the earlier algorithms for the problem. The algorithm uses several novel techniques to perform the evaluation, including the use of the dual of the plane embedding of the circuit to determine the propagation of values within the circuit.

Comparison of two's complement numbers

The problem of comparing n-bit two's complement numbers is closely related to the problem of detecting whether a carry is generated from the sum of two numbers. A faster solution to the carry generation problem immediately yields a faster solution to the comparison problem. We use a variation of the boolean circuit model to present a new upper bound to the solution of both problems. The new solution uses half-adders and a parallel prefix-and circuit to find the unique significant carry bit, and tristate buffers to pass the value of the significant bit to the output. Two implementations are presented: the bit prefix-and method, which is suitable for small n, and the group prefix-and method, which is just as fast but uses less hardware for moderate to large n. Both methods have simple and regular layouts, and are faster and require less area than existing methods.

A note on the monotone complexity of 2-REF

Sharpening an argument in (Cook and Luby, 1988), we show that the problem of recognizing refutable propositional logic formulas in conjunctive normal form with two disjuncts is monotonic p-projection equivalent to the problem st-DCON of directed connectivity between two distinguished vertices s, t of a directed graph. It follows by (Karchmer and Wigderson, 1990) that the monotonic depth of bounded fan-in boolean circuits for 2- ref is Θ(log 2( n)).