Boolean Circuit Of Size Research Articles

Circuit Lower Bounds for MCSP from Local Pseudorandom Generators

The Minimum Circuit Size Problem (MCSP) asks if a given truth table of a Boolean function f can be computed by a Boolean circuit of size at most θ, for a given parameter θ. We improve several circuit lower bounds for MCSP, using pseudorandom generators (PRGs) that are local; a PRG is called local if its output bit strings, when viewed as the truth table of a Boolean function, can be computed by a Boolean circuit of small size. We get new and improved lower bounds for MCSP that almost match the best-known lower bounds against several circuit models. Specifically, we show that computing MCSP, on functions with a truth table of length N , requires • N 3− o (1) -size de Morgan formulas, improving the recent N 2− o (1) lower bound by Hirahara and Santhanam (CCC, 2017), • N 2− o (1) -size formulas over an arbitrary basis or general branching programs (no non-trivial lower bound was known for MCSP against these models), and • 2 Ω( N 1/( d +1.01)) -size depth- d AC 0 circuits, improving the (implicit, in their work) exponential size lower bound by Allender et al. (SICOMP, 2006). The AC 0 lower bound stated above matches the best-known AC 0 lower bound (for PARITY) up to a small additive constant in the depth. Also, for the special case of depth-2 circuits (i.e., CNFs or DNFs), we get an optimal lower bound of 2 Ω( N ) for MCSP.

On the complexity of detecting hazards

Detecting and eliminating logic hazards in Boolean circuits is a fundamental problem in logic circuit design. We show that there is no O(3(1−ϵ)npoly(s)) time algorithm, for any ϵ>0, that detects logic hazards in Boolean circuits of size s on n variables under the assumption that the strong exponential time hypothesis is true. This lower bound holds even when the input circuits are restricted to be formulas of depth four. We also present a polynomial time algorithm for detecting 1-hazards in Dnf (or, 0-hazards in Cnf) formulas. Since 0-hazards in Dnf (or, 1-hazards in Cnf) formulas are easy to eliminate, this algorithm can be used to detect whether a given Dnf or Cnf formula has a hazard in practice.

A generalization of Spira's theorem and circuits with small segregators or separators

Spira showed that any Boolean formula of size s can be simulated in depth O(log⁡s). We generalize Spira's theorem and show that any Boolean circuit of size s with segregators (or separators) of size f(s) can be simulated in depth O(f(s)log⁡s). This improves and generalizes a simulation of polynomial-size Boolean circuits of constant treewidth k in depth O(k2log⁡n) by Jansen and Sarma. Our results imply that the class of languages computed by non-uniform families of polynomial-size circuits with constant size segregators equals non-uniform NC1.As a corollary, we show that the Boolean Circuit Value problem for circuits with constant size segregators is in deterministic SPACE(log2⁡n). Our results also imply that the Planar Circuit Value problem, which is known to be P-Complete, is in SPACE(nlog⁡n); and that the Layered Circuit Value and Synchronous Circuit Value problems, which are both P-complete, are in SPACE(n).

Isomorphism testing of Boolean functions computable by constant-depth circuits

Given two n-variable Boolean functions f and g, we study the problem of computing an ε-approximate isomorphism between them. An ε-approximate isomorphism is a permutation π of the n Boolean variables such that f(x1,x2,…,xn) and g(xπ(1),xπ(2),…,xπ(n)) differ on at most an ε fraction of all Boolean inputs {0,1}n. We give a randomized 2O(nlog⁡(n/ε)O(d)) time algorithm that computes an ε-approximate isomorphism between two isomorphic Boolean functions f and g that are given by depth d circuits of poly(n) size, where d is a constant independent of n, for any positive ε. In contrast, the best known algorithm for computing an exact isomorphism between n-ary Boolean functions has running time 2O(n)[12] even for functions computed by poly(n) size DNF formulas. Our algorithm is based on a result for hypergraph isomorphism with bounded edge size [4] and the classical Linial–Mansour–Nisan result on approximating small depth and size Boolean circuits by small degree polynomials using Fourier analysis [11].

Competing-provers protocols for circuit evaluation

Let C be a (fan-in 2) Boolean circuit of size s and depth d, and let x be an input for C. Assume that a verifier that knows C but doesn't know x can access the low degree extension of x at one random point. Two competing provers try to convince the verifier that C(x)=0 and C(x)=1, respectively, and assume that one of the provers is honest.For any r≥1, we give an r rounds protocol with communication complexity d1/r poly log(s) that convinces the verifier in the correct value of C(x) (with small probability of error). In particular, when we allow only one round, the protocol exchanges d ⋅ poly log(s) bits, and when we allow r=O(log(d)/log log(s)) rounds, the protocol exchanges only poly log(s) bits.Moreover, the complexity of the verifier and honest provers in this protocol is poly(s), and if in addition the circuit is log(s)-space uniform, the complexity of the verifier is d1/r poly log(s).The protocol is obtained by combining the delegation protocol of Goldwasser, Kalai and Rothblum [5] and the competing provers protocols of Feige and Kilian [3] and some new techniques. We suggest two applications of these results:Delegating computation to competing clouds: The main motivation behind the protocol of [5] was delegating computation to a cloud. Using our new protocol, a verifier can delegate computation to two (or more) competing clouds. If at least one of the clouds is reliable the verifier can trust that the computation is correct (with high probability). The advantage over the protocol of [5] is that the communication complexity and the number of rounds in our protocol are significantly lower.Communication complexity with competing provers, and circuit lower bounds: Aaronson and Wigderson [1] suggested the model of communication complexity with competing provers, where two competing provers try to convince two players that f(x,y)=0 and f(x,y)=1, respectively, where x is an input held by the first player and y is an input held by the second player. By scaling down the competing provers protocols of [3], they showed that strong enough lower bounds for the communication complexity of f, in this model, imply lower bounds for the computational complexity of f.Our results strengthen this connection. More precisely, we show that if f can be computed by a Boolean circuit of size s and depth d then for any r≥1 there is an r rounds protocol for f, in this model, with communication complexity d1/r poly log(s). This can be viewed as a possible direction towards proving circuit lower bounds. For instance, in order to prove f∉NC, it suffices to show that any one round protocol for f, in this model, requires the exchange of ω(poly log(n)) bits. This gives a relatively simple combinatorial property that implies strong circuit lower bounds.

A note on the circuit complexity of PP

In this short note, we show that for any integer k, there are languages in the complexity class PP that do not have Boolean circuits of size n k .

Simulating Boolean Circuits on a DNA Computer

We demonstrate that DNA computers can simulate Boolean circuits with a small overhead. Boolean circuits embody the notion of massively parallel signal processing and are frequently encountered in many parallel algorithms. Many important problems such as sorting, integer arithmetic, and matrix multiplication are known to be computable by small size Boolean circuits much faster than by ordinary sequential digital computers. This paper shows that DNA chemistry allows one to simulate large semi-unbounded fan-in Boolean circuits with a logarithmic slowdown in computation time. Also, for the class NC 1 , the slowdown can be reduced to a constant. In this algorithm we have encoded the inputs, the Boolean AND gates, and the OR gates to DNA oligonucleotide sequences. We operate on the gates and the inputs by standard molecular techniques of sequence-specific annealing, ligation, separation by size, amplification, sequence-specific cleavage, and detection by size. Additional steps of amplification are not necessary for NC 1 circuits. The feasibility of the DNA algorithm has been successfully tested on a small circuit by actual biochemical experiments.

The number of Boolean functions computed by formulas of a given size

Estimates are given of the number B(n, L) of distinct functions computed by propositional formulas of size L in n variables, constructed using only literals and ∧, ∨ connectives. (L is the number of occurrences of variables. L−1 is the number of binary ∧s and ∨s. B(n, L) is also the number of functions computed by two terminal series-parallel networks with L switches.) Enroute the read-once functions, which are closely related to Schroder numbers, are enumerated. Writing B(n, L)=b(n, L)L, we find that if L and β(n) go to infinity with increasing n and L≤2n/nβ(n), then b(n, L)∼cn, where c=2/(ln 4−1). Making a comparison with polynomial size Boolean circuits, this implies the following. For any constant α>1, almost all Boolean functions with formula complexity at most nα cannot be computed by any circuit constructed from literals and fewer than α−1nα two-input ∧, ∨ gates. © 1998 John Wiley & Sons, Inc. Random Struct. Alg., 13: 349–382, 1998

A Lower Bound for Perceptrons and an Oracle Separation of the PPPHHierarchy

We show that there are functions computable by linear size boolean circuits of depthkthat require superpolynomial size perceptrons of depthk−1, fork<logn/(6loglogn). This result implies the existence of an oracleAsuch thatΣp, Ak⊈PPΣp, Ak−2and, in particular, this oracle separates the levels in the PPPHhierarchy. Using the same ideas, we show a lower bound for another function, which makes it possible to strengthen the oracle separation toΔp, Ak⊈PPΣp, Ak−2.

On the Circuit Complexity of Sigmoid Feedforward Neural Networks

This paper aims to examine the circuit complexity of sigmoid activation feedforward artificial neural networks by placing them amongst several classic Boolean and threshold gate circuit complexity classes. The starting point is the class NNk defined by Shawe-Taylor et al. (1992) Classes of feedforward neural nets and their circuit complexity. Neural Networks 5(6), 971–977. For a better characterisation, we introduce two additional classes NNkΔ and NNkΔ,ϵ having less restrictive conditions than NNk concerning fan-in and accuracy, and proceed to prove relations amongst these three classes and well established circuit complexity classes. For doing that, a particular class of Boolean functions FΔ is first introduced and we show how a threshold gate circuit can be recursively built for any fΔ belonging to FΔ. As the G-functions (computing the carries) are fΔ functions, a class of solutions is obtained for threshold gate adders. We then constructively prove the inclusions amongst circuit complexity classes. This is done by converting the sigmoid feedforward artificial neural network into an equivalent threshold gate circuit Shawe-Taylor et al. (1992). Each threshold gate is then replaced by a multiple input adder having a binary tree structure, relaxing the logarithmic fan-in condition from (Shawe-Taylor et al. 1992) to (almost) polynomial. This means that larger classes of sigmoid activation feedforward neural networks can be implemented in polynomial size Boolean circuits with a small constant fan-in at the expense of a logarithmic factor increase in the number of layers. Similar results are obtained for threshold circuits, and are liked with the previous ones. The main conclusion is that there are interesting fan-in dependent depth-size tradeoffs when trying to digitally implement sigmoid activation feedforward neural networks. Copyright © 1996 Elsevier Science Ltd

Subquadratic zero-knowledge

article Free AccessSubquadratic zero-knowledge Authors: Joan Boyar Odense Univ., Odense, Denmark Odense Univ., Odense, DenmarkView Profile , Gilles Brassard Univ. of Montreal, Montreal, P.Q., Canada Univ. of Montreal, Montreal, P.Q., CanadaView Profile , René Peralta Univ. of Wisconsin at Milwaukee Univ. of Wisconsin at MilwaukeeView Profile Authors Info & Claims Journal of the ACMVolume 42Issue 6Nov. 1995 pp 1169–1193https://doi.org/10.1145/227683.227686Published:01 November 1995Publication History 11citation490DownloadsMetricsTotal Citations11Total Downloads490Last 12 Months17Last 6 weeks9 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Multiplication is the easiest nontrivial arithmetic function

It is shown that fixed point multiplication can be reduced to the evaluation of any member of a very large class of functions including most of the nontrivial functions used in practice. That means that whenever any such function can be evaluated by a Boolean circuit of size S( n), multiplication can be done with O( S( n)) Boolean operations, as well.