Bonded Silicon-on-insulator Wafers Research Articles

Enhancement of vertical integration density by engineered BSOI wafers

The lateral and vertical integration density of bulk microelectromechanical systems (MEMS) using bonded silicon-on-insulator (BSOI) wafers is significantly enhanced if the handle wafer is used as an electrical redistribution layer. Therefore isolated conductive paths should be integrated in the handle wafer, which are connected to the surface of the BSOI-wafer by high aspect ratio contacts (VIAs) through the device layer of the BSOI-wafer. In the present study we report on a fabrication process for customer specific designed BSOI wafers with VIAs from the device to the handle layers. Wafer bonding, wafer edge shaping and thinning of the wafers, which are critical processes for the fabrication of the BSOI-wafers, are discussed. The contacts to the handle wafer through the 75 µm thick device layer are created by 10 µm wide and 75 µm deep trenches filled with highly doped n-type poly-silicon. From current–voltage measurements an ohmic behaviour of the contacts with a resistance of around 120 Ω is demonstrated.

Electrical Characterization of Silicon-on-Insulator Wafers Using Photo-Conductance Decay (PCD) Method

In this work the photo-conductance decay (PCD) technique is used to measure the effective carrier lifetime in 160 nm–180 nm thick active layers of silicon-on-insulator (SOI) substrates both SIMOX and bonded. Study was carried out using 405 nm excitation wavelength featuring 200 nm absorption depth in silicon which was selected to coincide with the thickness of the active layers in the SOI wafers studied. The results obtained indicate the effectiveness of PCD methodology adopted for this study in the measurements of the minority carrier lifetime in Si active layers in SOI substrates. They demonstrate differences between PCD characterization of bulk and SOI wafers which are related to the confinement of the depletion region within the Si active layer in the latter case making its electrical properties less sensitive to the variation of the surface chemical condition. On the other hand, the process related physical changes in the SOI surface morphology were readily detectable by PCD measurements. Furthermore, the specific outcome of this investigation is the result indicating higher minority carrier lifetime in the Si active layer of bonded SOI wafers as compared to SIMOX wafers used in this study.

Proximity Gettering of Copper via Oxygen Precipitates for Silicon-on-Insulator Wafer

Silicon-on-insulator (SOI) technology has attributed attention because it enables device to operate in high speed with reducing parasitic capacitance and body effect. However, in the conventional SOI wafer without any gettering site, a very small amount of metallic contaminants degrades the transistor. During fabrication of copper through-silicon-via (TSV) for 3D device structure, copper contaminants after copper damascene chemical-mechanical-polishing (CMP) are accumulated at top silicon layer, BOX layer and silicon substrate resulting in gate oxide leakage, junction leakage current, and threshold voltage shift, etc. Particularly, since the copper solubility in oxide layer is higher than that in silicon, the implementation of gettering sites for copper contaminants in SOI wafers is fundamentally difficult. Thus, a design of gettering for copper contaminants in SOI wafers has been a key engineering to improve device characteristics. In this study, we investigated the effect of oxygen precipitates, produced by rapid-thermal annealing (RTA), on gettering efficiency of copper for SOI wafers after a dynamic-random-access-memory (DRAM) heat-treatment. To design a desirable distribution of oxygen precipitates for the gettering sites, the wafers were subjected to a RTA at 1150, 1175 and 1200 ºC for 10 s in an NH3 and Ar gas mixture. In addition, the substrate wafers were annealed at 800 ºC for 4 h in a nitrogen ambient to grow the oxygen precipitates and then followed at 1000 ºC for 16 h. Then, the bonded SOI wafers with proximity gettering sites and conventional SOI wafer were intentionally contaminated with copper of 1 × 1012 atoms/cm2 on the wafer surface, and then all SOI wafers were subjected to a typical DRAM heat-treatment. We correlated concentration of the oxygen precipitate with gettering efficiency of copper contaminants. Figure. 1 shows the distribution of bulk micro defects (BMDs) in the substrate wafer with a different heat-treatment condition. It shows that the substrate wafer subjected to a RTA and two-step heat-treatment has the highest density of BMDs. A SOI wafer was conventionally fabricated and subjected to a DRAM heat-treatment after copper contamination intentionally. In this wafer, concentration of copper contaminants was measured via dynamic secondary ion mass spectroscopy (D-SIMS). As shown in Fig. 2, concentration of copper on top silicon, BOX layer and bulk silicon is high because there is no gettering site. In Fig. 3, a substrate wafer was subjected to a RTA at 1175 ºC for 10 s and then followed two-step heat-treatment. The concentration of copper contaminants was relatively lower than that of Fig 2. This means that coppers were well gathered at oxygen precipitates located at underneath buried oxide after DRAM heat-treatment, verifying an excellent gettering efficiency for copper contaminants. In our presentation, we will discuss the detailed gettering mechanism for copper contaminants in SOI wafers and report proximity gettering of copper via oxygen precipitates for SOI wafer.* This work was financially supported by the Brain Korea 21 Plus Program in 2013 and SiWEDS (Silicon Wafer Engineering and Defect Science).Reference[1] S.M. Myers et al., J. Appl. Phys. 88 (2000) 3795[2] Lixia Lin et al., Solid-State and Integrated Circuit Technology (2010) 1563

Gettering in silicon-on-insulator wafers with polysilicon layer

We have studied both experimentally and theoretically iron gettering behavior in silicon-on-insulator (SOI) wafers. We show that a deposition of a polysilicon layer between the buried oxide and the device layer is a convenient way to have an effective gettering layer for metals in bonded SOI wafers under various processing conditions. Both our experiments and simulations show that the polysilicon layer decreases the dissolved iron concentration in the device layer and most importantly decreases the precipitation of the metals on the wafer front surface.

A self-priming, high performance, check valve diaphragm micropump made from SOI wafers

In this paper, we describe a self-priming high performance piezoelectrically actuated check valve diaphragm micropump. The micropump was fabricated from three wafers: two silicon-on-insulator (SOI) wafers and one silicon wafer. A process named ‘SOI/SOI wafer bonding and etching back followed by a second wafer bonding’ was developed in order to make the core components of this device which included an inlet check valve, an outlet check valve, a diaphragm and a chamber. The movable structures of this device, i.e. the check valves and the diaphragm, were fabricated from the device layers of the two bonded SOI wafers. Taking advantages of SOI wafer technology and etch-stop layers, the vertical parameters of the movable structures were precisely controlled in fabrication. The micropump was self-priming without any pre-filling process. The pumping rate of the micropump was linearly adjustable from 0 to 650l µm min−1 by adjusting frequency. The maximum pumping rate was 860 µl min−1 and the maximum pumping pressure was approximately 10.5 psi. The power consumption of the device was less than 1.2 mW.

Characterization of Pinhole in Patterned Oxide Buried in Bonded Silicon-on-Insulator Wafers by Near-Infrared Scattering Topography and Transmission Microscopy

Patterned oxides buried in bonded silicon-on-insulator (SOI) wafers before thinning have been characterized by near-IR scattering topography and a microscopy combination system. Micron-scaled pinholes in patterned oxides buried in bonded SOI wafers have been observed by the scattering topography. Edges of the patterned oxides have also been observed by both scattering topography and transmission microscopy. With the combination of scattering topography and transmission and reflection microscopy, this system is effective to evaluate the visibility of patterned oxides buried in bonded SOI wafers.

Characterization of Pinhole in Patterned Oxide Buried in Bonded Silicon-on-Insulator Wafers by Near-Infrared Scattering Topography and Microscopy

Patterned oxides buried in bonded silicon-on-insulator (SOI) wafers before thinning have been characterized by near-infrared scattering topography and microscopy combination system. The micron-scaled pinhole in oxide patterned buried in the bonded SOI wafer has been observed by the scattering topography. The edge of the patterned oxide has also been observed by both scattering topography and transmission microscopy. With the combination of scattering topography, transmission and reflection microscopy, this system is effective to evaluate the visibility of the patterned oxide buried in the bonded SOI wafer.

Low-Frequency-Noise Spectroscopy of SIMOX and Bonded SOI Wafers

Pseudo-MOSFET structures with metal source, drain, and guard electrodes are used to measure the low-frequency-noise characteristics of Separation by IMplantation of OXygen (SIMOX) and bonded silicon-on-insulator (SOI) wafers. The noise power spectra in the devices made from bonded SOI wafers are almost an order of magnitude lower than those made from SIMOX wafers. This is attributed to the lower interface trap density in the bonded wafers, which is extracted using the unified correlated model. The proposed method can be used to determine the 1/f noise characteristics of SOI wafers prior to circuit fabrication.

White X-ray Topography of Lattice Undulation in Bonded Silicon-on-Insulator Wafers

The lattice undulation of a silicon-on-insulator (SOI) layer in bonded SOI wafers was observed by synchrotron white and monochromatic X-ray topographies. Pattern formation for white X-ray topography was discussed using the geometric relation among the Bragg streak and diffracted X-rays in reciprocal space. The diffraction images in white X-ray topographs were simulated using the angular distributions of the lattice inclination in SOI layers obtained by the analysis of monochromatic X-ray topographs. The results of this simulation were in very good agreement with observations including the dependences on camera distance and SOI layer thickness, indicating that the contrast is mainly formed by the divergence/convergence effect of the diffracted X-rays.

Exploration of the Scaling Limits of 3D Integration

ABSTRACTThree dimensional (3D) wafer bonding is an emerging technology that may be used to increase transistor densities by stacking devices over devices. The alignment of the wafers and the devices on them is a function of the mechanical capability of the wafer to wafer alignment tool and the thermal conditions of each wafer when bonded. However, as bonded wafers are thinned to 1% or less of their starting thickness the processes of bonding and thinning as well as previous process history affect wafer planarity and silicon stress. The drive to vertically interconnect circuit blocks at the sub-micron scale requires a high density of vertical interconnects and thinning a wafer to less than 5 μm enables through wafer via processing at a scale found in the first layers of the interconnect stack. In this paper the measurement of wafer to wafer alignment was done by comparing a metal pattern on a face down bonded silicon on insulator (SOI) wafer to a complementary metal pattern on the bulk wafer to which it was bonded. The effect of aggressive thinning is evaluated using thinned back to face bonded SOI wafers with functional devices and face down bonded non-patterned SOI wafers thinned after bonding. The face up bonded SOI wafers with functional devices were temporarily bonded face down to a Si-wafer I, thinned to the buried oxide (BOX), face up bonded with benzocyclobutene (BCB) on a Si-wafer II, followed by release of the temporary bond and electrical test. Raman and XRD stress measurements of the non-patterned SOI wafer silicon 70 nm and 110 nm thick SOI Si were taken before and after thinning, and the radius of curvature of the SOI wafers and the bulk wafer substrates was monitored. Thermo-mechanical models of SOI Si stress and bonded wafer curvature are compared to the measured results.

Transition from wire formation to island formation in thermal agglomeration of a (111) silicon-on-insulator layer

The effects of Si layer thickness on thermal agglomeration of a (111) bonded silicon-on-insulator (SOI) structure were studied. As starting material, (111) bonded SOI wafers with their top Si layer thinned to 2–9 nm were used. The samples were subjected to thermal treatment at 950 °C in ultrahigh vacuum. Atomic force microscopy revealed that, in the 4–9 nm thickness range, the top Si layer is deformed into wire arrays in the 〈112¯〉 directions. However, at thicknesses below 4 nm, randomly formed Si islands were observed. This structural transition from wires to islands is presumably due to the atomic-scale thickness fluctuation in the initial Si layer.

Thermally-induced formation of Si wire array on an ultrathin (111) silicon-on-insulator substrate

We have found that a Si wire array is formed by thermal agglomeration of an ultrathin (111) Si layer in a bonded silicon-on-insulator (SOI) structure, although previous studies for crystalline and amorphous Si layers on SiO2 only showed island formation. As starting material, (111) bonded SOI wafers with the top Si layers thinned to 5–9 nm were used. The samples were then subjected to a thermal treatment at 950 °C in an ultrahigh vacuum. Atomic force microscopy revealed that the (111) top Si layer is deformed into three sets of wire arrays in the three equivalent ⟨112¯⟩ directions. It is also shown that the patterning of a Si layer leads to the wire array selectively formed in one of these three directions.

Integration of CMP Fixed Abrasive Polishing into the Manufacturing of Thick Film SOI Substrates

AbstractThe specification for the total thickness variation (TTV) of the device layers on thick-film silicon on insulator (SOI) wafers tighten for future applications. Therefore, the bulk removal polishing process of current technology after grinding cannot meet the demands in terms of flatness. The currently required amount of material removal for polishing out the induced sub surface damage (SSD) of the grinding is very high. Additionally, slurry-based CMP processes show unsatisfactory grindline and topography removal. This in turn reflects negatively to processing times, throughput and overall flatness performance.Encouraging early results of FA pad use for silicon and SOI polishing have already been further developed [1]. Low SSD grinding has been introduced to silicon manufacturing [[1]]. In this work, an integrated manufacturing process sequence is presented. Starting from low SSD grinding of the bonded SOI wafer couple, an optimized FA CMP step is replacing the conventional bulk polishing with reduced removal. The SSD after FA CMP is investigated by oxide induced stacking fault (OISF) method [[2]] and results are used to adjust the final polishing step of the substrates. The overall process sequence is highly advantageous in terms of performance in TTV and provides a highly competitive and effective method for achieving best possible surface quality with minimized total silicon removal. This method is not only useful for SOI wafers but also in other areas of silicon processing.

Electrical activation in silicon-on-insulator after low energy boron implantation

We have investigated the electrical activation of implanted boron in silicon-on-insulator (SOI) material using Hall effect, four-point probe, and secondary ion mass spectrometry. Boron was implanted at energies ranging from 1keVto6.5keV with a dose of 3×1014cm−2 into bonded SOI wafers with surface silicon thickness ranging from 300Åto1600Å. In one sample set, furnace anneals at 750°C were performed in a nitrogen ambient for times ranging from 5minto48h. A second sample consisted of isochronal furnace anneals performed from 450°Cto1050°C for 30min. Significantly less activation of boron is observed in SOI at temperatures below 750°C, regardless of the implant energy and surface silicon thickness. Between 750°C and 900°C, the active dose of boron in SOI is similar to that of bulk Si. As the implant energy increases, the fractional activation in thin SOI increases, due to a reduction in boron interstitial clusters (BIC) in the surface Si layer. It is concluded that an increase in the BIC population is the likely source of the low activation observed in SOI. This may be due to an increase in the interstitial supersaturation within the surface Si layer, due to the interface acting as a reflective boundary for interstitials.

Characteristic Study for Defect of Top Si and Buried Oxide Layer on the Bonded SOI Wafer

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

Synchrotron X-Ray Topography of Lattice Undulation of Bonded Silicon-On-Insulator Wafers

Lattice undulation of Silicon-on-Insulator (SOI) layers of bonded SOI wafers was observed by synchrotron X-ray topography. Patterns observed on topographs depended on the thickness of the SOI layer, the camera distance between a specimen and an X-ray film, and the diffraction geometry of the Laue and Bragg cases. The dependence was interpreted as the effects of the geometrical relation in reciprocal space among the Ewald sphere, the reciprocal lattice vector, and the surface normal direction. To confirm the origin of the pattern formation, the topographic images were simulated in the framework of the kinematical diffraction theory. Based on the simulation, it was found that a granular pattern observed in the 115 Bragg case was due to the divergence/convergence effect of X-rays diffracted from the undulated SOI layer.

Changes in carrier profiles of bonded SOI wafers with thermal annealing measured by the spreading resistance method

Carrier concentration profiles of both p-type and n-type bonded silicon-on-insulator (SOI) wafers are measured using spreading resistance analysis. A high-resistivity region is observed near the SOI/buried oxide (BOX) interface for the as-received wafers, irrespective of the conduction type. After the high-temperature annealing at about 1000 °C, the high-resistivity region disappears, and the interface region is inverted in p-type SOI and accumulated in n-type SOI. To interpret the results, carrier concentration profiles are theoretically calculated considering a fixed charge in the BOX and electronic states at the SOI/BOX interface. From comparison between the experimental and theoretical results, it is concluded that the SOI/BOX interfaces initially have interface state density of the order of 10 11 cm −2 eV −1, which is decreased to the order of 10 10 cm −2 eV −1 by the annealing.

Measurement of Oxide Etch Rate of SOI Structure using near IR Microscopy

The sacrificial oxide etching is one of the key steps in fabrication of micromechanical devices on bonded silicon on insulator (SOI) wafers. The determination of the etch rate of buried oxide layers in bonded SOI wafers from scanning electron microscopy (SEM) cross-sections is a rather tedious and time consuming task. However, the knowledge of the etch front propagation is essential for ensuring the success of etch release and thus the device operation. In this paper a fast and non-destructive method for measurement of sacrificial oxide layer etch rates is described. The pattern and time dependencies of SOI structure etching in concentrated hydrofluoric acid are studied by near infrared microscopy. The etch length of the SOI can be accurately measured with IR microscope. The measurement results were also verified by SEM cross-sections. The observed variation in etch rates can be explained by the SOI interface quality and not by any aspect ratio dependency caused by varying structure layer thickness. In the used etch times for etching of the thermal oxide the etch-rate seems to be limited by the bonded interface quality and not by transport limitations. The results of these experiments and some application examples are shown. Other possible applications, limitations and error sources of this method are discussed.

Crystal Surface Defects and Oxygen Gettering in Thermally Oxidized Bonded SOI Wafers

This work investigates the role of interstitial oxygen content in the starting Czochralski bonding wafers, and the effects of buried layered implants and thermal processing on the formation of crystalline defects in the surface of bonded silicon on insulator (SOI) material. We found that unimplanted SOI material originating from Si with high oxygen levels were populated with heavy oxygen precipitation and related crystal defects, and were also characterized by low minority carrier lifetime values. However, a dramatic improvement was observed in the behavior of SOI with low oxygen levels where the development of oxygen precipitation in the SOI layer was inhibited. Incorporation of a buried As ion implanted layer in high oxygen level SOI increased the lifetime of the material and suppressed the formation of oxygen precipitates through an oxygen gettering effect. The gettering efficiency of the buried defect layer was found to be related to the dose of the As ion implantation, the annealing temperature, and type of starting silicon material. A dose of was sufficient for effective gettering. © 2001 The Electrochemical Society. All rights reserved.

Heavy-Metal (Fe/Ni/Cu) Behavior in Ultrathin Bonded Silicon-On-Insulator (SOI) Wafers Evaluated Using Radioactive Isotope Tracers

The behavior of Fe, Ni and Cu in bonded silicon-on-insulator (SOI) wafers thinned down to 0.5 µm by plasma-assisted chemical etching (PACE) was investigated for the first time by the radioactive isotope tracer method, which can avoid the evaluation errors due to contamination during sample preparation or analysis. When ultrathin bonded SOI wafers without an intentional gettering site were contaminated with Fe or Ni from the surface, Fe and Ni did not diffuse into the substrate through the buried oxide (BOX) layer after annealing in N2(2%O2) ambient at 900°C and 700°C, respectively. Cu easily diffused into the substrate through the BOX layer after annealing at 700°C for 60 min, and was captured at the bonding interface. It was found that the behavior of Ni, which exhibits the same diffusivity in Si as does Cu, was quite different in ultrathin bonded SOI wafers from that in bulk Si wafers due to the BOX layer of the SOI structure.