Bond Wire Lift-off Research Articles

Estimating of IGBT Bond Wire Lift-Off Trend Using Convolutional Neural Network (CNN)

Estimating of IGBT Bond Wire Lift-Off Trend Using Convolutional Neural Network (CNN)

Bond wire lift-off detection by gate voltage waveform in IGBT turn-off process enhanced by digital gate control

This paper presents a new detection method of bond wire lift-off in Insulated Gate Bipolar Transistor (IGBT) power module. The bond wire lift-off is a major failure mode in power cycle degradation of the IGBT module, and many monitoring methods have been proposed and demonstrated for safety operation of power electronics systems in the previous works. In this study, we focus on the gate voltage waveform as an indicator to detect wire-lift for a simple and straightforward detection method. Due to the increase in parasitic inductance caused by bond wire lift-off, the turn-off switching waveform becomes modulated. The digital gate control (DGC) was employed to control the switching behavior to obtain precision for low-noise and high-performance. Furthermore, the DGC 2-step vector control (2-sVC) can enhance the sensitivity of bond wire lift-off failure detection by gate voltage waveform change. As feature quantities, the gate voltage spike peak, its amplitude and the timing shift were measured at various operating conditions. The DGC obtained larger feature quantities compared with conventional gate control. In particular, high-current conditions were found to be more favorable for achieving high sensitivity due to the high die/dt. From these results, the DGC is effective to achieve both the high sensitivity to detect bond wire lift-off by gate voltage waveform and maintaining the best switching performance.

Influence of SiC chip thickness on the power cycling capability of power electronics assemblies – A comprehensive numerical study

Silicon carbide (SiC), as one of the most favorite wide band gap semiconductor materials, is often applied in power electronics nowadays. The reliability of SiC packages, however, hasn't been sufficiently investigated yet, and unexploited potentials are still expected. One critical impact parameter is the geometric chip design, from which its thickness is the most easily accessible feature. In this paper, finite element simulations are performed to investigate the influence of SiC chip thickness on the power cycling capability based on a “standard” power electronics assembly concept. The results show a potential increase of the power cycling lifetime for solder fatigue by 7 times and bond wire lift-off by 8 times when decreasing the SiC chip thickness from 350 μm to 50 μm. On the other hand, by decreasing the chip thickness, the risk for chip fracture increases due to increasing tensile stresses in the chip surface.

RUL Estimation for Package Failure of Power Electronic Devices Using Integral Mean of Precursor Signal

Package failure like bond-wire lift-off is one common cause of failure for discrete power electronic devices such as Schottky diodes. To estimate their Remaining Useful Lifetime (RUL), forward voltage drop is often used as the precursor signal. Prior researches use the direct forward voltage feature and its derived features to construct neural networks for RUL prediction. These features can reflect the instant health condition of the device in the current time or time window, but miss to represent the accumulated effect of gradually decreasing health conditions. In the paper, we formulate the integral mean feature of forward voltage drop and propose to use it to conduct RUL estimation. By the integral mean feature, we are able to capture the device's health condition in an accumulated fashion. Our experiments show that our approach is superior in generalization performance when compared to the forward voltage feature and its statistical features based neural networks for RUL estimation.

Enhancement of turn-off gate voltage waveform change by digital gate control for bond wire lift-off detection in IGBT module

The bond wire lift-off is the one of main failures for insulated gate bipolar transistors (IGBT) power modules. The wire lift-off increases parasitic inductance LeE in the module and the gate voltage Vge waveform is modulated by LeE·dIe/dt. Therefore, the Vge waveform has the potential for an indicator of condition monitoring. The Digital gate control (DGC) can control switching behavior precisely for low-loss and low-noise switching. It is also effective for sensitivity enhancement of Vge waveform changed by the wire lift-off. This paper reports how the DGC 2-step vector control (2-sVC) can improve the wire lift-off failure detection sensitivity by Vge waveform. The experiment results showed that the Vge spike was generated by LeE·dIe/dt at the turn-off switching and the spike generation timing depended on the wire number. The DGC obtained the larger timing-shift Δtwire and the amplitude ΔVge-surge than those at the conventional gate control. In addition, the best vector condition improved the trade-off between turn-off loss and collector voltage overshoot compared with the conventional gate control. From these results, the DGC is effective to enhance the sensitivity of bond wire lift-off detection by Vge waveform maintaining the best switching performance.

Temperature distribution in multichip IGBT module and its impact on collector current sharing

Multichip Insulated Gate Bipolar Transistor (IGBT) power modules are widely used in high power applications. However, the parallel connection of IGBT chips results in an inhomogeneous temperature/current distribution. In this paper, a thermographic camera is used to capture the temperature distribution of an opened Infineon IGBT module FF600R17ME4 where each IGBT switch has three IGBT chips. The influence of temperature distribution on collector current sharing is then examined in both healthy conditions and bond wire lift-off scenarios. In this research, the critical temperature distribution is demonstrated experimentally at both chip and switch levels. The experimental results reveal that there are, depending on the collector current, 8 °C to 60 °C temperature difference at the chip level and 2 °C to 10 °C maximum temperature variation at the switch level. The severe temperature distribution impacts the collector current sharing less than 1 % variation under healthy conditions and 0.507 % at IC = 240 A upon the first bond wire lift-off. Other findings are that during homogeneous temperature distribution current densities are nearly similar per chip and less dependent on chip temperatures. Findings of this research have the potential to influence multichip Insulated Gate Bipolar Transistor (mIGBT) layout design. For example, having investigated the current density distribution at different operating points, it is recommended to increase the number of bond wires by 11 % for the chip placed in the middle for this particular module in order to increase reliability. Potential future research areas have also been identified.

Power Cycling Method for Power Modules With Low Thermal Resistance

In this article, an advanced power cycling method for power modules with low thermal resistance is proposed. Thermal resistance of power module is getting smaller and smaller, and for power cycling test (PCT), it is more and more difficult to obtain the desired maximum junction temperature <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm {vjmax}}$ </tex-math></inline-formula> and junction temperature swing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta T_{\mathrm {vj}}$ </tex-math></inline-formula> under rated current. By analyzing the influencing factors of parameters in the PCT, this article proposes a new method to affect the parameters of the power cycle by changing the external thermal resistance so that the low thermal resistance module can perform the PCT at the rated current. Then, FZ750R65KE3 modules are selected to analyze the influence of different external thermal resistances on PCT parameters. Finally, PCTs are carried out using discrete devices and power modules to analyze the influence of changing the external thermal resistance on the typical failure modes bond wire liftoff and solder layer degradation. The new method enables power modules with low thermal resistance to perform PCT at rated current without changing lifetime and failure modes.

A Fault Detection Method of IGBT Bond Wire Fatigue Based on the Reduction of Measured Heatsink Thermal Resistance

Bond wire lift-off is one of the major failure mechanisms in the insulated gate bipolar transistor (IGBT) modules. Detecting the fault of bond wires is important to avoid the open-circuit fault of IGBT to ensure the reliable operation of power converters. In this paper, we propose a novel bond wire fatigue detection method for IGBT, which could be used in normal working conditions. Firstly, we investigated the dependence of bond wire fatigue on heatsink thermal resistance. An aging rate K was proposed to compare the measured thermal resistance with the initial value, which could indicate the bond wire fatigue. Then, this proposed method was verified by simulation and experimental results under different current levels. Finally, a power cycling test was used to show the aging process of the IGBT module, which shows the feasibility of proposed method.

Research on the Influence of Bond Wire Lift-Off Position on the Electro-Thermal Characteristics of IGBT

Based on the actual packaging structure of insulated gate bipolar transistor (IGBT) module, this article establishes the power loss model, and analyzes the influence of the position of the lift-off bond wire on the module. Through the theoretical analysis, it is found that the position of the lift-off bond wire is an important factor affecting the aging of the modules. And then the electrothermal coupling model of IGBT is established for simulation, and an experimental platform is built for verification. The results show that the distribution of bond wire lift-off position is one of the characteristics of bond wire failure. When the bond wire lift-off failure is concentrated on a single IGBT chip, it will accelerate the aging process of the modules. Therefore, this article considers that the position of the lift-off bond wire is a significant factor in the aging process of the modules, which should be fully considered in the bond wire state evaluation. In addition, the research results of this article can also provide theoretical reference for the optimization of IGBT module packaging structure.

Aging Monitoring Method of Bond Wires-Based on Phase-Frequency Characteristics of Differential Mode Conducted Interference Signal for IGBT Module

This paper presents an on-line monitoring method of IGBT module bond wires aging based on the phase-frequency characteristics (PFCs) of differential mode (DM) interference signal. Firstly, the collector current variation during IGBT chip switching is analyzed, and the relationship between the aging degree of bond wires and the PFCs of DM interference signal is studied; Secondly, a phase angle characteristic measurement system of DM interference signal is built and used to online monitor the aging of bond wires in IGBT module; Finally, taking the buck converter composed of IGBT module as the equipment under tested, the interference signal is extracted by the RF current probe and processed by the low-pass filter and signal amplifier, then the phase angle characteristics are measured by the oscilloscope board to realize the on-line monitoring of the bond wires aging of IGBT module. The experimental results show that compared with buck converter with healthy IGBT module, the phase angle of DM interference signal in Buck Converter with aging IGBT module is reduced. The proposed method does not need expensive equipment such as spectrum analyzer, and only needs to monitor the aging state of bond wires in IGBT module online through oscilloscope board. Besides, the research method in this paper provides an approximate linear monitoring method for bonding wire lift-off.

High-Frequency Non-Invasive Magnetic Field-Based Condition Monitoring of SiC Power MOSFET Modules

Current distribution anomaly can be used to indicate the onset of package-related failures modes in Silicon Carbide power MOSFET modules. In this paper, we propose to obtain the wire bond’s magnetic field profile using an array of Tunnel Magneto-Resistance (TMR) sensors, and characterise the small changes in the current density distribution to find the onset of the wire bond degradation processes, including wire bond lift-off, wire bond cracking, and wire bond fracture. We propose a novel condition monitoring technique where a non-galvanic high-bandwidth sensing and a reliability model monitor the health of the power switches. We designed a dedicated calibration set-up to examine the sensor array and calibrated to demonstrate the adequate sensitivity to a minimum 5% current anomaly detection in a single wire bond of the switching devices operating with 50 kHz switching frequency. We use a hardware-in-the-loop (HIL) experimental set-up to replicate wire bond-related failures in a 1200 V/55 A SiC MOSFET power module of a DC/DC Boost converter. Signal conditioning circuits are further designed to amplify and buffer the sensor readings. Experimental results showed the proposed technique is able to detect a wide range of package-related failures.

Bond wire lift-off monitoring based on intersection point movement characteristic in IGBT module

Condition monitoring (CM) the insulated-gate bipolar transistor (IGBT) module is of vital significance to improve the reliability of power electronics system. Collector–emitter on-state voltage VCE,ON is a frequently employed failure precursor to identify the bond wire aging. In this paper, a method of separating VCE,ON is proposed to monitor the bond wire lift-off of IGBT module. Firstly, based on the circuit structure of IGBT module, the VCE,ON is divided into voltage drop across IGBT chip VChip and voltage drop across bond wire VBW. Secondly, the working principle of IGBT chip is investigated, and the calculation method of voltage drop across P-i-N diode VPiN is proposed. Finally, the VChip is analyzed, and information provided by collector current IC at the IC–VChip curve intersection point that is not affected by solder layer fatigue is adopted to monitor the lift-off degree of bond wire. The feasibility of the above methods is verified by theory and experiment.

COMPARATIVE ANALYSIS OF THERMAL STRESS OF Si AND SiC MOSFETs

The performance of power MOSFET is affected by high thermal stress exposure. A high level of thermal stress is induced when the MOSFET experiences a temperature change. This finding is about the bonding wire lift-off on the solder pad. The MOSFET model is designed with the heatsink to ensure accurate results are obtained in this research work. The key intention of this research is to investigate the condition of silicon and silicon carbide power MOSFETs during thermal stress. The thermal properties of silicon and silicon carbide MOSFET were investigated by developing a 3D modal and thermal stress simulation in the COMSOL Multiphysics software. Thermal resistance was calculated by randomly selecting a power loss value of 100 Watts. Junction temperature for silicon and silicon carbide MOSFET was taken from several articles mentioned in the results and discussion.&#x0D; Keywords: Thermal stress, bonding wire lift-off, temperature change, MOSFET

A Study on the Effect of Bond Wires Lift-Off on IGBT Thermal Resistance Measurement

Bond wire lift-off will cause an increase of remaining wires’ power dissipation, which usually is ignored for healthy modules. However, only partial wires’ power dissipation transfers through thermal path from junction to case, which will lead to overestimate the whole power dissipation from collector to emitter pole and underestimate the calculated thermal resistance using the proportion of temperature difference to power dissipation. A FEM model is established to show the change of heat flow after bond wires were removed, the temperature of bond wires increases, and the measured thermal resistance decrease after bond wires lift-off. It is validated by experimental results using open package Insulated Gate Bipolar Transistor (IGBT) modules under different current conditions. This conclusion might be helpful to indicate the bond wires lift-off and solder fatigue by comparing the change of measured thermal resistance. Using the Kelvin setup to measure thermal resistance will cause misjudgment of failure mode due to the ignoring of wires’ power dissipation. This paper proposed that the lift-off of bond wires will lead to underestimating the thermal resistance measurement, which will overestimate the lifetime of IGBT module and misjudge its state of health.

Aging Diagnosis of Bond Wire Using On-State Drain-Source Voltage Separation for SiC MOSFET

Bond wire aging is a universal failure form of silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) module. Real-time condition monitoring of bond wire is an important guarantee for the stable operation of power electronics system. In this article, a method of monitoring the aging state of bond wire in SiC MOSFET module using on-state drain-source voltage (OSDSV) separation technique is proposed. Firstly, the temperature dependence of the conduction circuit resistance from drain terminal to source terminal in SiC MOSFET module is analyzed to obtain the temperature characteristics of the OSDSV. Secondly, the resistance of the package structure in SiC MOSFET module is extracted, and the OSDSV is divided into two parts: the package structure voltage and the chip OSDSV, and the analytical model for estimating the junction temperature of SiC MOSFET module in the healthy state is acquired. Finally, the package structure voltage is employed to monitor the aging degree of bond wire in SiC MOSFET module, and the flow chart of aging diagnosis of bond wire is established. The proposed method can accurately identify the failure state of bond wire lift-off. Theoretical and experimental results prove that the method is feasible.

Estimation of Lifetime and Reliability of Input Rectifier in Variable Frequency Drives

This research paper investigates the causes of power module failures in front-end rectifier of variable frequency drive (VFD) and their lifetime estimation. The front-end rectifier plays an important role in the electrical system for energy conversion. However, from the industrial survey it is found that they are sensitive to harsh operating conditions and are prone to damage. Hence, it becomes inevitable to analyse the causes of their failure and lifetime. Due to prolonged usage, sudden variations in supply and load, the power modules will be subjected to stresses such as overvoltage, voltage variations due to sag, phase unbalance, over current, temperature, harmonics and pre-distortions. The major causes of failure are due to several stresses such as solder joint break, bond wire lift-off, cracks in power modules are discussed. In this paper, the lifetime of the power module is estimated for a given mission profile data. The junction temperature profile is obtained from the VFD Front-end rectifier simulation model. The number of temperature cycles from the temperature profile is estimated using cycle counting methods. Lifetime estimation and damage modelling is done using Coffin-Manson rule and Palmgren Miner rules. All these modelling and simulations are done for a specific VFD power size using MATLAB and PLECS.

Real-Time Monitoring of Thermal Response and Life-Time Varying Parameters in Power Modules

This article introduces new technologies for monitoring thermal response and life-time varying parameters of power electronic modules in real time without interrupting normal converter operation. The technologies are embedded in an adaptive thermal observer, which integrates temperature measurements and electrothermal models to estimate device losses and temperatures at reliability-critical locations of the power module. The observer structure includes a model reference adaptive system for adaptively calibrating device switching-loss models. This improves thermal monitoring accuracy, avoids time-consuming offline calibrations, and creates the opportunity for efficiency estimations during power module operation. The adaptive observer together with small-signal loss-excitation and system-identification technologies extract the thermal impedance of the power module in magnitude and phase over multiple frequency decades. This in situ thermal impedance spectroscopy has the unique feature of continuously providing information on the thermal interface of the power devices without interrupting normal inverter operation. The extracted information, i.e., life-time varying electrical and thermal parameters, enables diagnosing power module state-of-health with improved accuracy compared to prior technologies. It even allows separating different degradation effects, such as bond wire lift-off, device and base-plate solder delamination as well as deterioration of the convection process. With these new features, next generation monitoring systems can extract thermal response and degradation and thus protect power modules from severe thermal stress and overload. Furthermore, the obtained state-of-health information can be selectively used to reduce thermal stress and to schedule predictive maintenance leading to a safer and more reliable operation of future converter systems.

Semiconductor Temperature and Condition Monitoring Using Gate-Driver-Integrated Inverter Output Voltage Measurement

Bond-wire liftoff caused by mechanical stress due to thermal cycling is one of the major failures in power electronic systems. Condition monitoring concepts which allow prediction of these failures are often based on voltage-drop detection and thermal monitoring. However, solutions to determine the junction temperature and semiconductor voltage drop during operation often require additional effort and lead to increased cost. In this article, a direct semiconductor temperature detection method is proposed which is based on instantaneous semiconductor voltage-drop monitoring. A <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> inverter system, equipped with a digital integration-based instantaneous output voltage measuring circuit, is extended by software to enable instantaneous semiconductor voltage-drop detection. Experimental results demonstrate that the proposed method is feasible for online temperature measurement and detection of increased resistance due to bond-wire faults. The voltage measurement resolution is sufficient for dynamic temperature monitoring, including fundamental frequency temperature cycles at very low frequency.

Localization and Detection of Bond Wire Faults in Multichip IGBT Power Modules

Multichip insulated gate bipolar transistor (mIGBT) power modules (PMs) degrade over power cycling. Bond wire lift-off is one of the major failure modes. This article presents a technique to diagnose bond wire lift-off by analyzing the on-state voltages across collector and emitter terminals and the voltages across collector and Kelvin emitter terminals. The proposed method can indicate the first lift-off out of 37 bond wires in a mIGBT. The main novelty of the proposed technique is that it can locate the chip that has bond wire lift-off(s). In addition, the temperature dependence of the proposed approach is negligible. The article describes the proposed technique in detail and shows results and discussions based on practical tests which are carried out on two mIGBT PMs with different packages.

Electro-thermal modelling and Tj estimation of wire-bonded IGBT power module with multi-chip switches subject to wire-bond lift-off

Wire-bonded multi-chip IGBT power modules constitute the heart of high-current power electronic motor drives. The most common failure mechanism is the degradation of the top-side wires. This deterioration impacts the electrical path and the individual dies’ temperature. The temperature is thus not only a stressor, but also a failure precursor. It is thus typically sensed in health monitoring methods based on damage-accumulation-models and failure precursors. One way to estimate the temperature is through the on-state voltage at low load current as a temperature sensitive electrical parameter. The on-state voltage being sensitive to the quality of the top-side connection, the obtained temperature estimate is drifting with degradation. This drift typically leads to under-estimating the temperature, thus reducing the precision of health monitoring. Drift compensation methods based on re-calibration are effective in single-chip switches, but their performances are not viable in multi-chip switches. This is due to the different temperature and current conditions during the calibration and the estimation phases. This paper addresses the relation between wire-bond degradation and temperature in multi-chip switches and proposes a simple model to explain and reproduce the electro-thermal behaviours. The model is based on experimental results where the degradation of wire-bonds is reproduced by cutting the wires sequentially. The model is further used to explain the drift in temperature estimation and the performance of the drift compensation methods based on re-calibration. Overall, the paper provides new results and understandings of the thermo-electrical behaviour of multi-chip power IGBT modules subject to wear-out.