Wire Bond Interconnects Research Articles

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.

Investigation of Ultralow Loss Interconnection Technique for LTCC based System-in-Package(SIP) Technology at 60GHz

AbstractThe effects of wire and ribbon bond interconnection on the transmission characteristics at millimeter wave frequency range was presented. The insertion loss and return loss was closely related with the ratio of the signal line width to that of bonded wire or ribbon. The most promise condition for low loss interconnection was that the width of bonded wire or ribbon should be compatible to the width of signal lines. In the actual fabrication of LTCC amp module, the insertion loss of packaging is very small which means that the loss due to bonding is nearly negligible. However, the S11 and S22 degraded severely due to the difference of the types of transmission lines between chip and packaging module. A new transition structure was introduced in order to compensate this difference of transmission lines.

Process and design analysis for ultrafine-pitched wiresweep elimination in advanced copper heat spreader BGA package

The semiconductor device trend for increasing functionalities and performances yet with smaller overall feature sizes presents escalating obstacles to the decreasing form factor along with demanding thermal carrying capability required at the package level. To confront this compounding issue, ultrafine-pitch wirebond interconnect coupled with thermally enhanced copper heat spreader attached to the package are introduced. However, the additional copper heat spreader thickness introduced within the package challenges the design of the package's wire, its loop height, and the molding process control to prevent wire sweeping occurrences. This study investigates the impact of different ultrafine pitched wire types, wire loop designs, copper heat spreader structures, and mold material types on eliminating device short from occurring due to the wire sweeping phenomena. A full factorial experiment is performed using an active silicon device packaged in a thermally enhanced ball grid array (BGA) test vehicle. In addition, test characterization is carried out using x-ray and multiinsertions hot/cold continuity tests. Then, a detailed failure analysis is performed by package decapsulation and scanning electron microscopy/energy-dispersive x-ray (SEM/EDX) to confirm the experimental findings. In conclusion, the study finds that for an ultrafine-pitched thermally enhanced BGA package, wire type is insignificant to reduce wire shorting occurrences. However, mold material and copper heat spreader structure using an optimized wire loop design are significant factors in eliminating wiresweep shorting phenomena. This study concludes with a wirebond interconnect and heat slug design recommended along with an improved process parameters and assembly material sets found from the experiment.

Evaluation of wire bonding performance, process conditions, and metallurgical integrity of chip on board wire bonds

Chip on board wire bonding presents challenges to modern wire bonding technology which include smaller, closely spaced wire bond pads; bonding to soft substrates without special processing and pad construction; and diverse first bond and second bond metallurgies. These challenges are addressed by extensive bonding accuracy tests, a design of experiments approach for optimizing wire bond process parameters, reliability testing, and detailed materials characterization of the metallurgical integrity of the wire bonds. The thermo-mechanical integrity of the wire bond interconnects was evaluated by wire pull and hot storage tests. Hot storage testing allowed for detection of samples with an electrolytic gold surface finish that was too thin, and exhibited a contamination-corrosion condition of the nickel under-plating. Other samples with an excessively thick, rough textured nickel under-plating layer exhibited poor wire bond-ability. The methodology of materials analyses of the metallurgy of the wire bond interconnects is described. The paper illustrates a wire bond lift technique that is used to inspect for cratering damage and the “area-uniformity” of gold aluminum intermetallics. An improved understanding of the wire bonding process was achieved by showing the dependence of the visual appearance of the wire bonds on wire bond process parameters.

The future of gold in electronics

Gold-based materials have been a mainstay of the electronics and semiconductor industry since the physics was just a laboratory curiosity. Gold is the workhorse material in wire bond, flip chip and off wafer interconnections due to its corrosion resistance, ability to form metallurgical bonds by soldering or cold welding, and ease of fabrication. As the electronics and semiconductor industries grew, so did the use, of gold in spite of the feature size reduction so elegantly demonstrated in Moore's law. However, several revolutions in the Silicon miracle are threatening gold's place as the material of choice. Although cost is always an issue, the limitations are associated with the chemistry of gold based alloys. Will gold remain? Emerging requirements of bioelectronics, photonics and power requirements in conventional device represent new opportunities for gold to shine. Additionally, as the world market demand for electronic, semiconducting, bio-electronic and photonic technology increases, given the right technology, gold still can provide value proposition.

Interconnecting to aluminum- and copper-based semiconductors (electroless-nickel/gold for solder bumping and wire bonding)

Electroless nickel and immersion gold plating technologies (e-Ni/Au) have traditionally been used almost exclusively within the electronics industry to create a solderable surface on substrate materials, e.g. laminate boards. Recent advances in these plating technologies, along with the inherent low costs associated with electroless plating processes, have enabled the extension of their utilization into a variety of semiconductor applications, e.g. wafer level pad metallization. This paper describes the electroless nickel and immersion gold processes for both aluminum- and copper-based semiconductors. The nickel plating bath is a hypophosphite-based solution and the gold bath is a cyanide-free sulfate-based solution. For aluminum-based integrated circuits a zincation process is used to initiate nickel growth, and for copper, palladium is used to catalyze the surface. Tight control of the chemistries, equipment, and run-time process variables are required to ensure repeatability. Thin film Auger analysis of the as-plated films shows well-defined layers of high purity gold and nickel/phosphorous. Adhesion of the e-Ni/Au layers was evaluated by measuring the load required to shear I/O pads plated with tall nickel bumps. Integrity of the nickel was further evaluated by subjecting the structures to multiple temperature cycles and test for pad shear strength. Results show no degradation in shear load or failure mode. The deposition of nickel and gold onto the I/O pad surfaces enables the subsequent use of both wire bond and flip chip (lead-based and lead-free alloys) interconnect methods. The integrity of gold wire bonds to the e-Ni/Au plated I/O pad was evaluated using ball shear, wire pull, and the corresponding failure analysis of each. Results show values well above product specifications, with wire pull failure modes in the wire and intermetallic failure in the ball shear studies. For flip chip applications, the e-Ni/Au layer was evaluated using stencil-printing technology to deposit several different solder alloys. In the current investigation, two test vehicles were successfully bumped with both 63Sn/37Pb and 90Pb/10Sn lead-based solder alloys, as well as the 95.5Sn/3.8Ag/0.7Cu lead-free alloy. In order to evaluate the compatibility of these alloys with the electroless nickel layer, solder bump shear tests were performed as a function of number of reflow cycles. Results show no degradation in shear load or failure mode among all three of the alloys tested, indicating no critical nickel consumption (i.e., excessive intermetallic growth) during reflow. Additional tests were performed comparing nickel under-bump-metallurgy (UBM) thicknesses of 1, 2 and 5 μm. Again, no critical nickel consumption was detected.

Wide-bandwidth millimeter-wave bond-wire interconnects

A new type of interconnect has been developed that significantly extends the bandwidth of fixed-length bond-wire interconnects between microwave circuits. This interconnect maximizes bond-wire length, as well as landing pad size while simultaneously extending the cutoff frequency of the interconnect. The bond-wire interconnect is treated as a five-stage low-pass filter where basic filter theory is used to develop an interconnect prototype. Microstrip interconnects are designed using electromagnetic simulators, which match a specific low-pass filter response on a 5-mil thick (127 /spl mu/m) glass substrates. The measurements indicate a return loss greater than 12 dB and an insertion loss from 0.0 to 0.3 dB from DC to 80 GHz using two 17-mil-long (432 /spl mu/m) 1-mil-diameter (25 /spl mu/m) ball bonds with a tolerance of /spl plusmn/2 mil (50 /spl mu/m). For comparison, an uncompensated interconnect with two 17-mil-long (432 /spl mu/m) bond wires has 1-dB insertion loss and 10-dB return loss at 40 GHz and continues to degrade at higher frequencies.

Experimental modeling, repeatability investigation and optimization of microwave bond wire interconnects

We present the first comprehensive experimental characterization of bond wire interconnects at microwave frequencies which includes a repeatability study, modeling and optimization. Wire bond interconnects with two different bond types (ball-crescent and wedge), two different loop types (tight and loose) and two different lengths (15 and 25 mils), were fabricated and experimentally investigated. We report the performance and repeatability comparison of these configurations and develop an electromagnetic as well as a simple wide band lumped-element equivalent circuit model to 40 GHz. A novel ribbon bond interconnect topology has also been proposed and experimentally tested demonstrating 65% less reflection compared to the conventional bond wire or ribbon configuration.

Modeling and characterization of the bonding-wire interconnection

In this paper, the bonding-wire interconnection has been studied from the points of view of its modeling and electrical characterization. Both singleand double-wire structures have been considered, the latter under the assumption of parallel wires. Two electrical models of the bonding wire are discussed. First, the finite-difference time-domain (FDTD) method is proposed for the rigorous analysis of such structures. This method uses a suitable discretization technique, which accounts for the wire curvature by means of a polygonal approximation. A quasi-static model of the bonding wire, suitable for commercial microwave computer-aided-design tools is then proposed. This model is based on the representation of the structure with four sections of a uniform transmission line and the model parameters are evaluated analytically from the dimensions of the interconnection. Accuracy and applicability of the quasi-static model have been assessed by analyzing several test structures, the reference results being obtained with the FDTD method. Finally, the quasi-static model has been used to provide an extensive electrical characterization of the bonding wire versus its main geometrical parameters. This characterization is given in terms of an equivalent series inductance and two equivalent shunt capacitances forming a /spl pi/ low-pass network. This representation is particularly useful in the matching of the bonding-wire discontinuity.

Microstrip-to-microstrip interconnects with adhesive bonded ribbons for micro- and millimeterwave applications

A simple chip-to-chip interconnect technique with adhesive bonded ribbons is presented. It solves the insertion loss problem of wire bond interconnects in micro- and millimeterwave assemblies. The following paper discusses design and fabrication of such interconnects. A quasistatic model is developed to ease the quality assessment of their electrical behavior. It is validated by measurements on microstrip resonators with and without interconnects. The chip-to-chip interconnect technique with adhesive bonded ribbons exhibit low loss and is useable up to 50 GHz or more.

Development of an alternative wire bond test technique : Michael Pecht, Donald Barker and Pradeep Lall. IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part A, 17, 4, 610 (December 1994)

An alternative test technique to the wire bond pull test is presented for wire bond interconnects. The new test technique, based on electromagnetic resonance, has the potential for on-line use as a quality assurance and operational life evaluation method. The new technique greatly reduces the test time in comparison with the existing MIL-STD-883 pull test and internal visual inspection. This new test technique more closely simulates the operational stress than the wire bond pull test and has also shown a sensitivity to defects that would otherwise escape visual inspection

296 lead fine pitch (0.4 mm) thin plastic QFP package with TAB interconnect

The quad flat pack (QFP) package has become the surface mount technology (SMT) package of choice for microprocessors and peripheral devices and is well suited for hand held computer application. To address this market segment Intel has developed a new package with a thin (2.0 mm) body for light weight, low standoff (0.25 mm maximum) for overall lower profile, in a 32 mm/spl times/32 mm body format. Tape automated bonding (TAB) interconnect from die to the leadframe is used to overcome wirebond interconnect limitations. This package provides a more manufacturable package system by using flat handling during test operation. The package is trimmed and formed subsequent to test operation and shipped in standard JEDEC thin matrix plastic trays, ready to use for SMT operation with good lead coplanarity. Package reliability is equivalent to other plastic packages. Sample packages were supplied to selected customers to help develop the 0.4 mm pin pitch SMT process, equipment and materials. The feedback/results indicate that the current base of installed SMT equipment is capable of assembling such 0.4-mm pitch packages with very little or no modification and at acceptable quality levels.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Development of an alternative wire bond test technique

An alternative test technique to the wire bond pull test is presented for wire bond interconnects. The new test technique, based on electromagnetic resonance, has the potential for on-line use as a quality assurance and operational life evaluation method. The new technique greatly reduces the test time in comparison with the existing MIL-STD-883 pull test and internal visual inspection. This new test technique more closely simulates the operational stress than the wire bond pull test and has also shown a sensitivity to defects that would otherwise escape visual inspection. >

Scanning Electron Microscopy in Hybrid Microelectronics

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.