Bondwire Inductor Research Articles

A Robust LC-π Matching Network for 112 Gb/s PAM4 Receiver in 28 nm CMOS

This article presents analysis, design details, and simulation results of an impedance matching network designed for a 112 Gb/s pulse-amplitude-modulation-4 (PAM4) receiver using an LC-π structure. We designed the bonding wire as a part of the matching network, which reduced design pressure on the equalizer as there will be no need to compensate the loss of the chip package. To avoid robustness issues caused by the fluctuation of the bonding wire inductance, the matching network is designed to bw adjustable by the capacitance on PCB and the terminal resistance. We analyzed the parasitics in the layout and the influence of nearby and dummy metals and obtained reliable simulation results through electromagnetic field simulation. This matching network is designed with a 28 nm CMOS process. Post-layout simulation results show that with bonding wire inductance changing from 150 pH to 250 pH, it can always meet CEI-112G-XSR-PAM4 Extra Short Reach Interface requirements.

A Fully Integrated Multi-Phase Buck Converter With On-Chip Capacitor Dynamic Re-Allocation and Fine-Grained Phase-Shedding Techniques

This article presents a fully integrated multi-phase (MP) buck converter for on-chip power management units. A peak-and-valley differential sensing (PVDS) scheme based on a flying capacitor is proposed to evenly balance the multiple inductor currents without significant power overhead even under mismatches in inductances, parasitic series resistances, and control-signal skews among phases. In addition, dynamic re-allocation of on-chip capacitors enables an even more optimal frequency response and output ripple based on the number of activated phases. It also improves the chip area efficiency, resulting in a higher power density. The proposed DLL-based MP clock generation provides high granularity in the phase-shedding control to achieve high efficiency over a wide load range. The proposed fully integrated buck converter using six bond-wire inductors (1 nH) was fabricated in a 28-nm CMOS process. The chip running at a frequency of 400 MHz/phase can finely adjust the number of active phases by an integer step ranging from 1 to 6 through sensing a load current. A maximum power density of 1.23 W/mm2 and a peak efficiency of 83.7% were measured. This work achieved an ultra-fast dynamic voltage scaling (DVS) rate of 75 mV/ns.

A Compact On-Chip Pad Structure With an Embedded Capacitor for Broadband Millimeter-Wave Bond-Wire Interconnection

This article presents a compact on-chip pad structure with an embedded capacitor for millimeter-wave bond-wire interconnection, which is realized by 65-nm complementary metal–oxide–semiconductor (CMOS) process and able to compensate the parasitic inductance introduced by bonding wires. The proposed pad structure implemented by metal stacking is equivalent to an on-chip series capacitor. Moreover, a deep N-well structure is loaded at the bottom of the pad to reduce the parasitic pad-to-ground capacitance. This pad structure has been applied to the chip-to-chip interconnection with a measured minimum insertion loss (IL) of 2.179 dB and a measured 3-dB bandwidth of 11.9 GHz from 35.6 to 47.5 GHz. In addition, it has been applied to the chip-to-printed circuit board (PCB) interconnect ion with a measured one-sided loss of 1.7475 dB and a measured 3-dB bandwidth of 12 GHz from 22.7 to 34.7 GHz. Both applications using bond-wire interconnections prove that the proposed pad structure can compensate bond-wire inductance and realize broadband low-loss impedance matching.

X-band CMOS VCO for 5 GHz Wireless LAN

The implementation of a low phase noise voltage controlled oscillator (VCO) is important for the signal integrity of wireless communication terminal. A low phase noise wideband VCO for a wireless local area network (WLAN) application is presented in this paper. A 6-bit coarse tune capacitor bank (capbank) and a fine tune varactor are used in the VCO to cover the target band. The simulated oscillation frequency tuning range is from 8.6 to 11.6 GHz. The proposed VCO is desgned using 65 nm CMOS technology with a high quality (Q) factor bondwire inductor. The VCO is biased with 1.8 V VDD and shows 9.7 mA current consumption. The VCO exhibits a phase noise of –122.77 and -111.14 dBc/Hz at 1 MHz offset from 8.6 and 11.6 GHz carrier frequency, respectively. The calculated figure of merit(FOM) is -189 dBC/Hz at 1 MHz offset from 8.6 GHz carrier. The simulated results show that the proposed VCO performance satisfies the required specification of WLAN standard.

A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery

This brief presents a successive-approximation-register (SAR) analog-to-digital converter (ADC) assisted DC-DC buck converter, which operates in discontinuous conduction mode (DCM) and achieves fast load transient recovery characteristics. The power inductor of the buck converter uses the bondwire inductance. During the load transient, the dynamic low-power SAR ADC samples the converter's undershoot/overshoot output voltage and controls the programmable current pump circuit to charge/discharge the output capacitor, thus speeding up and smoothing the load transient response. An additional compensation circuit is also designed to ensure the stability of the voltage mode control loop and the current pump. The chip fabricated in a 65-nm CMOS technology occupies an area of 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The converter, switching at 100 MHz, achieves a peak power efficiency of 81% when V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub> = 1.2 V, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> = 1 V and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Load</sub> = 50 mA. When the load current steps from 2 mA to 50 mA, the measured undershoot/overshoot voltage is 101/92 mV, and the recovery time is 175/406 ns.

A Hybrid, Fully-Integrated, Dual-Output DC–DC Converter for Portable Electronics

This article describes a hybrid, dual-output dc-dc converter suitable for low-power application. It consists of inductor based subconverter providing one output, which is cascaded with a switched-capacitor based subconverter providing the second output. The converter uses bondwire inductance, and on-chip metal-oxide-semiconductor (MOS) capacitance to realize the passive components making it a fully-integrated solution. For target specification of output voltage levels, and input voltage range, the stepped-up output is generated by the inductor-based, high-frequency, voltage-mode boost converter. And, a switched capacitor based, frequency-controlled step-down converter generates the second output. The hybrid converter uses a π-filter to attenuate the switching ripple to an acceptable value. The filter also helps to isolate the internal ground from the noisy power ground connected to boost converter power stage. By the virtue of time-interleaved switching pattern, switching noise induced in its supply rails by the S-C stage is significantly less, which makes the S-C stage an equivalent quiescent load to the boost stage. A prototype of the proposed hybrid converter has been designed, and implemented in 0.18-μm CMOS process. It consumes 0.82 mm2 area, and provides -1.45V, and 3.2V from an input voltage varying from 1.2V to 2.7V at an efficiency > 52% (maximum 77%) for all load conditions.

Digitally-Controlled Bondwire Inductor with High Quality Factor and Wide Tuning Range

A tunable bondwire inductor (TBI) with high-quality factor and wide tuning range is presented. The proposed TBI is fabricated on a single chip by combining a single-pole four-throw (SP4T) switch integrated circuit (IC) and four bondwire inductors on a package substrate. The SP4T switch IC is fabricated using 180 nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The fabricated TBI chip exhibits a 521% tuning range of inductance from 1.77 to 11 nH at 0.1 GHz and a relatively high-quality factor. To the knowledge of the authors, the results of this work demonstrate the best combined performance of inductance tuning range and quality factor.

Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering

This paper demonstrates the improved power and electromagnetic (EM) side-channel attack (SCA) resistance of 128-bit Advanced Encryption Standard (AES) engines in 130-nm CMOS using random fast voltage dithering (RFVD) enabled by integrated voltage regulator (IVR) with the bond-wire inductors and an on-chip all-digital clock modulation (ADCM) circuit. RFVD scheme transforms the current signatures with random variations in AES input supply while adding random shifts in the clock edges in the presence of global and local supply noises. The measured power signatures at the supply node of the AES engines show upto 37× reduction in peak for higher order test vector leakage assessment (TVLA) metric and upto 692× increase in minimum traces required to disclose (MTD) the secret encryption key with correlation power analysis (CPA). Similarly, SCA on the measured EM signatures from the chip demonstrates a reduction of upto 11.3× in TVLA peak and upto 37× increase in correlation EM analysis (CEMA) MTD.

Performance Improvement of Microwave Vector Modulator Through Coupler Characteristic Impedance Optimization and Bond-Wire Inductance Utilization

An improved technique for the design of an unbalanced analog reflection-type on-chip vector modulator is presented. At microwave frequencies, voltage-controlled high-electron-mobility transistor (HEMT) like pseudomorphic HEMT (pHEMT) is often chosen as the variable termination in vector modulator. However, the parasitic elements of the transistor introduce amplitude and phase errors, which will degrade the overall performance of the vector modulator. Based on the establishment of pHEMT scalable parasitic model and characterization of bond-wire interconnection, we propose a method and a corresponding design procedure that mitigate the parasitic effects of pHEMT and achieve optimum performance of the vector modulator. The influences of Lange coupler characteristic impedance and compensation inductance on the vector modulator are analyzed first. Then, a method to determine the optimal values of characteristic impedance and compensation inductance is given, which relieves parasitic effects and obtains symmetric constellation. In our proposed design, the compensation inductance is realized through bond-wire inductance, eliminating the requirement of the on-chip inductor. To validate the design concept, a vector modulator module, composed of power divider, Lange coupler, and variable termination, is designed with each part fabricated separately using 0.15- $\mu \text{m}$ GaAs pHEMT process and assembled on Rogers 5880 substrate with 10-mil-thick printed circuit board. The assembled vector modulator is characterized using an automatic test setup. The measured symmetric constellation is in good agreement with the simulation result, which indicates the effectiveness of the proposed design method and assembly process.

A New Analog-based LO Harmonic Rejection Technique with Tunable Notch Frequency

An effective technique for mixer LO harmonic rejection in a SAW-less wideband receiver front-end is proposed. The proposed technique provides a tunable notch that can be placed at any frequency like mixer LO harmonics, to avoid the aliasing in baseband after mixing. An analog LC notch is used in a cascode transconductor, and it can reject one of the 3rd or 5th harmonics. This notch frequency is tunable using the bond wire inductors or fixed Gyrator-C active inductor, and a capacitor array, without any significant Power/Area overhead on overall system. Since the accurate value of inductance is not clear, a calibration circuit is proposed to tune this LC notch. This tuning phase runs in forground, and consumes very low additional power. This technique is used in a wideband receiver front-end. Post-layout simulation in 130nm CMOS results in an average 3rd harmonic rejection ratio of 36 dB. The overall circuit consums 34mW power and a has a noise figure of 3.4dB at 1GHz frequency.

Cost-effective 400-Gbps micro-intradyne coherent receiver using optical butt-coupling and FPCB wirings.

We present a cost-effective and bandwidth-enhanced 64-Gbaud micro-intradyne coherent receiver based on hybrid integration of InP waveguide-photodetector (WG-PD) and silica planar lightwave circuit (PLC). InP waveguide-photodetector (WG-PD) arrays are simply chip-to-chip bonded and optically butt-coupled to a silica-based dual-polarization optical hybrid chip. Multiple flexible printed circuit boards are adapted for electrical RF and DC wirings, which provide low-cost integration and good RF performance of the receiver. A 3-dB bandwidth of the fabricated coherent receiver is extended to ~36 GHz by optimization of bondwire inductance between the WG-PD array and the transimpedance amplifier (TIA), even when commercial TIAs with a typical bandwidth of ~29 GHz are used. Through optimization of the silica hybrid integrated coherent receiver, 64-Gbaud DP-16QAM signal transmission over 1050-km standard single-mode fiber is successfully demonstrated below a bit error rate of 2 × 10-3. This is the threshold for a soft decision-based forward error correction, at the optical signal to noise ratio of 23.8 dB.

PCB Embedded Bondwire Inductors With Discrete Thin-Film Magnetic Core for Power Supply in Package

This paper details the design, assembly, and detailed characterization of printed circuit board (PCB) embedded thin magnetic film inductors for Power Supply in Package applications. Solenoidal inductors were assembled on copper tracks printed on PCB with wire bonds to complete the copper loop. Furthermore, the solenoid inductors have laminated amorphous soft magnetic thin films embedded between the two conductor layers. The devices have chemically thinned Vitrovac films laminated as core material. Three different designs of solenoid inductors with different numbers of turns are assembled and characterized. The assembled PCB inductor measured a highest quality factor of 8.5 for a three-turn device at 10 MHz.

An Integrated DC–DC Boost Converter Having Low-Output Ripple Suitable for Analog Applications

This paper presents an integrated boost converter having very low output voltage ripple making it suitable for analog applications, which are sensitive to supply noise. Architecturally, the converter consists of a conventional boost converter followed by an L–C filter, which drastically reduces the output ripple. The L–C filter has been realized using 30-nH bondwire inductance and 0.54-nF on-chip capacitance. The converter switches at 118 MHz and produces a regulated 3.2-V output from an input voltage ranging from 1.0 to 2.7 V. The converter is able to deliver up to 65-mA current for input voltage $\geq$ 2.4 V. The prototype has been implemented in 0.18- $\mu$ m standard digital CMOS process and the entire design consumes only 0.52-mm $^2$ chip area resulting in a maximum power density of 0.387 W/mm $^2$ . Peak efficiency of the converter is 77.4% at 32.2-mA current for 2.7-V input supply. The measured maximum output ripple noise is 21 mV that is less than 0.65% of the regulated output voltage.

Analysis and Design of Broadband &lt;italic&gt;LC&lt;/italic&gt;-Ladder FET LNAs Using Noise Match Network

A noise match network for the LC -ladder input network of a broadband inductively source-degenerated common-source (CS) field effect transistor (FET) low-noise amplifier (LNA) is established through noise transformation matrix to derive the noise parameters of a broadband LNA. Analytical formulas for the noise factors of a CS FET LNA with a three-section LC-ladder input network are thus obtained based on the design algorithm of optimal noise and input match developed in this paper. Two 3.7–10.5 GHz two-stage LNAs of the same topology are demonstrated using 0.15- $\mu \text{m}$ pHEMT technology to validate the design methodology. One LNA has all the fully integrated inductors and the other uses two on-chip inductors replaced by two high-Q bondwire inductors for better noise performance. The measurement results show 11-dB power gain with 2.1-dB noise figure for the LNA with the fully integrated inductors and 11-dB power gain with 1.6-dB noise figure for the LNA with two bondwire inductors, respectively.

Design of efficient power amplifier for low power transmitters

This paper presents a fully integrated, low transmit-power and high-efficiency 2.4 GHz class-E power amplifier (PA) in TSMC 0.18 μm CMOS process for low-power transmitters such as wireless sensor networks (WSN). In this paper, a new output load has been proposed. Also, analytical design equations have been included to design an efficient low power circuit. This PA, employs the pad capacitance and bond-wire inductance of the output node, for satisfying class-E zero-voltage switching (ZVS) condition and matching the antenna's 50 Ω resistance. By using bond-wire inductance instead of inductor in the output filter, smaller chip size and higher efficiency has been achieved compared to other works for low transmit-power applications. Also, the effectiveness of bulk-drive technique on faster switching and increasing efficiency have been evaluated. It has been proved that this technique leads to increase the efficiency of switching PAs. This PA delivers a range of output power from 2.7 to 7.2 dBm with a supply voltage range from 500 to 850 mV while achieving overall power efficiency range of 57.3---60.7%.

Low Phase Noise CMOS VCO with Hybrid Inductor

A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multistandard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.

A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25bits at a supply voltage of 1.2V, typical process corner and sampling frequency of 50MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697μW and achieves an energy efficiency of 25fJ/conversion-step while occupying a core area of 0.055mm2.

A 4 × 2 switch matrix in QFN24 package for 0.5–3 GHz application

This paper presents a 4 × 2 switching matrix implemented in the Win 0.5 μm GaAs pseudomorphic high electron mobility transistor process, it covers the 0.5–3 GHz frequency range. The switch matrix is composed of 4 SPDT switch whose two output ports can simultaneously select the input port and a 4 to 8 bit digital decoder, both the radio frequency (RF) part and the digital part are integrated into one single chip. The chip is packaged in a low cost QFN24 plastic package. On chip shunt, capacitors at the input ports are taken to compensate for the bonding wire inductance effect. The designed switch matrix shows a good measured performance: the insertion loss is less than 5.5 dB, the isolation is no worse than 30 dB, the return loss of input ports and output ports is better than −10 dB, the input 1 dB compression point is better than 25.6 dBm, and the OIP3 is better than 37 dBm. The chip size of the switch matrix is only 1.45 × 1.45 mm2.

25-Gb/s Optical Transmitter with Si Ring Modulator and CMOS Driver

We present a 25-Gb/s optical transmitter composed of a Si ring modulator and CMOS driver circuit. The Si ring modulator is realized with 220-nm Si-on-insulator process and the driver circuit with 65-nm CMOS process. The modulator and the driver are hybrid-integrated on the printed circuit board with bonding wires. The driver is designed so that the parasitic bonding wire inductance provides enhanced driver bandwidth. The transmitter successfully demonstrates 25-Gb/s operation.

Transient Behavior and Phase Noise Performance of Pulsed-Harmonic Oscillators

The analysis of a low-power, temperature- and supply voltage-independent oscillator based on a pulsed LC tank is presented. The frequency is determined by a bondwire inductor and a MiM capacitor to obtain a high-Q LC tank. Due to a novel way of driving the LC tank, the power consumption is reduced. Since the driving technique only interacts with the LC tank during a very short period, the frequency mainly depends on the stable LC tank, hence the temperature and supply voltage dependency is lowered drastically. The phase noise of the tank, the noise propagation and the transient effects of the driving technique are analyzed theoretically. The results are compared to a 130 nm test chip. The samples were measured over a 0.6 to 1.6 V supply range and a -40 to 100 ° C temperature range showing a very low temperature dependency of 92 ppm/ ° C and a voltage dependency of 73 ppm/V. The frequency standard deviation over 12 automatically bonded samples of the same wafer is 0.76% (359 KHz).